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realtek: eth: convert set_rx_mode() to regmap

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Make use of regmap in all device specific set_rx_mode() functions.
Adapt the constant prefixes to the rest of the driver. While we
are here:

- align the RTL931x function name with the other targets
- replace constants with GENMASK()
- use new lowercase style for hexadecimal values

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22757
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Markus Stockhausen 2026-04-03 12:25:59 +02:00 committed by Robert Marko
parent 99a0cf9c44
commit 063223da70
2 changed files with 50 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

68
target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c
View File

@ -802,80 +802,88 @@ static int rteth_stop(struct net_device *ndev)
static void rteth_838x_set_rx_mode(struct net_device *ndev)
{
struct rteth_ctrl *ctrl = netdev_priv(ndev);
/* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
* CTRL_0_FULL = GENMASK(21, 0) = 0x3FFFFF
*/
if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
sw_w32(0x0, RTL838X_RMA_CTRL_0);
sw_w32(0x0, RTL838X_RMA_CTRL_1);
regmap_write(ctrl->map, RTETH_838X_RMA_CTRL_0, 0);
regmap_write(ctrl->map, RTETH_838X_RMA_CTRL_1, 0);
}
if (ndev->flags & IFF_ALLMULTI)
sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0);
regmap_write(ctrl->map, RTETH_838X_RMA_CTRL_0, GENMASK(21, 0));
if (ndev->flags & IFF_PROMISC) {
sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0);
sw_w32(0x7fff, RTL838X_RMA_CTRL_1);
regmap_write(ctrl->map, RTETH_838X_RMA_CTRL_0, GENMASK(21, 0));
regmap_write(ctrl->map, RTETH_838X_RMA_CTRL_1, GENMASK(14, 0));
}
}
static void rteth_839x_set_rx_mode(struct net_device *ndev)
{
struct rteth_ctrl *ctrl = netdev_priv(ndev);
/* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
* CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC
* Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00
* CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0)
*/
if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
sw_w32(0x0, RTL839X_RMA_CTRL_0);
sw_w32(0x0, RTL839X_RMA_CTRL_1);
sw_w32(0x0, RTL839X_RMA_CTRL_2);
sw_w32(0x0, RTL839X_RMA_CTRL_3);
regmap_write(ctrl->map, RTETH_839X_RMA_CTRL_0, 0);
regmap_write(ctrl->map, RTETH_839X_RMA_CTRL_1, 0);
regmap_write(ctrl->map, RTETH_839X_RMA_CTRL_2, 0);
regmap_write(ctrl->map, RTETH_839X_RMA_CTRL_3, 0);
}
if (ndev->flags & IFF_ALLMULTI) {
sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0);
sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1);
sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2);
regmap_write(ctrl->map, RTETH_839X_RMA_CTRL_0, GENMASK(31, 2));
regmap_write(ctrl->map, RTETH_839X_RMA_CTRL_1, GENMASK(31, 0));
regmap_write(ctrl->map, RTETH_839X_RMA_CTRL_2, GENMASK(31, 0));
}
if (ndev->flags & IFF_PROMISC) {
sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0);
sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1);
sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2);
sw_w32(0x3ff, RTL839X_RMA_CTRL_3);
regmap_write(ctrl->map, RTETH_839X_RMA_CTRL_0, GENMASK(31, 2));
regmap_write(ctrl->map, RTETH_839X_RMA_CTRL_1, GENMASK(31, 0));
regmap_write(ctrl->map, RTETH_839X_RMA_CTRL_2, GENMASK(31, 0));
regmap_write(ctrl->map, RTETH_839X_RMA_CTRL_3, GENMASK(9, 0));
}
}
static void rteth_930x_set_rx_mode(struct net_device *ndev)
{
struct rteth_ctrl *ctrl = netdev_priv(ndev);
/* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
* CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC
* Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00
* CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0)
*/
if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) {
sw_w32(GENMASK(31, 2), RTL930X_RMA_CTRL_0);
sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_1);
sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_2);
regmap_write(ctrl->map, RTETH_930X_RMA_CTRL_0, GENMASK(31, 2));
regmap_write(ctrl->map, RTETH_930X_RMA_CTRL_1, GENMASK(31, 0));
regmap_write(ctrl->map, RTETH_930X_RMA_CTRL_2, GENMASK(31, 0));
} else {
sw_w32(0x0, RTL930X_RMA_CTRL_0);
sw_w32(0x0, RTL930X_RMA_CTRL_1);
sw_w32(0x0, RTL930X_RMA_CTRL_2);
regmap_write(ctrl->map, RTETH_930X_RMA_CTRL_0, 0);
regmap_write(ctrl->map, RTETH_930X_RMA_CTRL_1, 0);
regmap_write(ctrl->map, RTETH_930X_RMA_CTRL_2, 0);
}
}
static void rtl931x_eth_set_multicast_list(struct net_device *ndev)
static void rteth_931x_set_rx_mode(struct net_device *ndev)
{
struct rteth_ctrl *ctrl = netdev_priv(ndev);
/* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
* CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC
* Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00.
* CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0)
*/
if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) {
sw_w32(GENMASK(31, 2), RTL931X_RMA_CTRL_0);
sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_1);
sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_2);
regmap_write(ctrl->map, RTETH_931X_RMA_CTRL_0, GENMASK(31, 2));
regmap_write(ctrl->map, RTETH_931X_RMA_CTRL_1, GENMASK(31, 0));
regmap_write(ctrl->map, RTETH_931X_RMA_CTRL_2, GENMASK(31, 0));
} else {
sw_w32(0x0, RTL931X_RMA_CTRL_0);
sw_w32(0x0, RTL931X_RMA_CTRL_1);
sw_w32(0x0, RTL931X_RMA_CTRL_2);
regmap_write(ctrl->map, RTETH_931X_RMA_CTRL_0, 0);
regmap_write(ctrl->map, RTETH_931X_RMA_CTRL_1, 0);
regmap_write(ctrl->map, RTETH_931X_RMA_CTRL_2, 0);
}
}
@ -1410,7 +1418,7 @@ static const struct net_device_ops rteth_931x_netdev_ops = {
.ndo_start_xmit = rteth_start_xmit,
.ndo_set_mac_address = rteth_set_mac_address,
.ndo_validate_addr = eth_validate_addr,
.ndo_set_rx_mode = rtl931x_eth_set_multicast_list,
.ndo_set_rx_mode = rteth_931x_set_rx_mode,
.ndo_tx_timeout = rteth_tx_timeout,
.ndo_set_features = rteth_93xx_set_features,
.ndo_fix_features = rteth_fix_features,

26
target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.h
View File

@ -18,6 +18,8 @@
#define RTETH_838X_QM_PKT2CPU_INTPRI_MAP (0x5f10)
#define RTETH_838X_QM_PKT2CPU_INTPRI_0 (0x5f04)
#define RTETH_838X_QM_PKT2CPU_INTPRI_CNT 3
#define RTETH_838X_RMA_CTRL_0 (0x4300)
#define RTETH_838X_RMA_CTRL_1 (0x4304)
#define RTETH_839X_CPU_PORT 52
#define RTETH_839X_DMA_IF_INTR_MSK (0x7864)
@ -28,6 +30,10 @@
#define RTETH_839X_QM_PKT2CPU_INTPRI_MAP (0x1154)
#define RTETH_839X_QM_PKT2CPU_INTPRI_0 (0x1148)
#define RTETH_839X_QM_PKT2CPU_INTPRI_CNT 3
#define RTETH_839X_RMA_CTRL_0 (0x1200)
#define RTETH_839X_RMA_CTRL_1 (0x1204)
#define RTETH_839X_RMA_CTRL_2 (0x1208)
#define RTETH_839X_RMA_CTRL_3 (0x120c)
#define RTETH_930X_CPU_PORT 28
#define RTETH_930X_DMA_IF_INTR_MSK (0xe010)
@ -37,6 +43,9 @@
#define RTETH_930X_MAC_L2_PORT_CTRL (0x3268 + RTETH_930X_CPU_PORT * 64)
#define RTETH_930X_QM_RSN2CPUQID_CTRL_0 (0xa344)
#define RTETH_930X_QM_RSN2CPUQID_CTRL_CNT 11
#define RTETH_930X_RMA_CTRL_0 (0x9e60)
#define RTETH_930X_RMA_CTRL_1 (0x9e64)
#define RTETH_930X_RMA_CTRL_2 (0x9e68)
#define RTETH_931X_CPU_PORT 56
#define RTETH_931X_DMA_IF_INTR_MSK (0x0910)
@ -46,6 +55,9 @@
#define RTETH_931X_MAC_L2_PORT_CTRL (0x6000 + RTETH_931X_CPU_PORT * 128)
#define RTETH_931X_QM_RSN2CPUQID_CTRL_0 (0xa9f4)
#define RTETH_931X_QM_RSN2CPUQID_CTRL_CNT 14
#define RTETH_931X_RMA_CTRL_0 (0x8800)
#define RTETH_931X_RMA_CTRL_1 (0x8804)
#define RTETH_931X_RMA_CTRL_2 (0x8808)
/*
* Reset
@ -146,24 +158,10 @@
/* TRAPPING to CPU-PORT */
#define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984)
#define RTL838X_RMA_CTRL_0 (0x4300)
#define RTL838X_RMA_CTRL_1 (0x4304)
#define RTL839X_RMA_CTRL_0 (0x1200)
#define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058)
#define RTL839X_RMA_CTRL_1 (0x1204)
#define RTL839X_RMA_CTRL_2 (0x1208)
#define RTL839X_RMA_CTRL_3 (0x120C)
#define RTL930X_VLAN_APP_PKT_CTRL (0xA23C)
#define RTL930X_RMA_CTRL_0 (0x9E60)
#define RTL930X_RMA_CTRL_1 (0x9E64)
#define RTL930X_RMA_CTRL_2 (0x9E68)
#define RTL931X_VLAN_APP_PKT_CTRL (0x96b0)
#define RTL931X_RMA_CTRL_0 (0x8800)
#define RTL931X_RMA_CTRL_1 (0x8804)
#define RTL931X_RMA_CTRL_2 (0x8808)
/* Chip configuration registers of the RTL9310 */
#define RTL931X_MEM_ENCAP_INIT (0x4854)