From 12d41dce0681301713a99f67a383eae47c656b25 Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Fri, 17 Apr 2026 08:50:26 +0200 Subject: [PATCH] realtek: rtl930x: psx8: specify RTL8224 reset GPIO The nRESET pins of the RTL8224 PHYs on the PSX8/PSX10 are wired to GPIO6 (lan1-4) + GPIO10 (lan5-8) of the SoC, but this was never described in the devicetree. GPIO 6 is the global reset shared by (logical) PHYs 0-3 on MDIO bus0. GPIO 10 is the global reset shared by (logical) PHYs 8-11 on mdio bus0. It is intentionally not declared as reset-gpios on any bus: the MDIO driver / phylink only support a single reset GPIO per bus, not two (or more). And a GPIO can only be used as reset-gpio on a single PHY. Attaching it to a single PHY would still reset the other PHYs on the same chip as a side effect, leaving their software state out of sync with the hardware and likely breaking them. Signed-off-by: Sven Eckelmann Link: https://github.com/openwrt/openwrt/pull/23297 Signed-off-by: Robert Marko --- .../dts/rtl9302_plasmacloud_common.dtsi | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/target/linux/realtek/dts/rtl9302_plasmacloud_common.dtsi b/target/linux/realtek/dts/rtl9302_plasmacloud_common.dtsi index bd3845fac3..630ea90e9c 100644 --- a/target/linux/realtek/dts/rtl9302_plasmacloud_common.dtsi +++ b/target/linux/realtek/dts/rtl9302_plasmacloud_common.dtsi @@ -210,3 +210,37 @@ nvmem-cells = <&macaddr_ubootenv_ethaddr 8>; nvmem-cell-names = "mac-address"; }; + +&gpio0 { + /* + * GPIO 6 is the global reset shared by (logical) PHYs 0-3 on MDIO bus0. + * It is intentionally not declared as reset-gpios on any bus: the MDIO + * driver / phylink only support a single reset GPIO per bus, not two + * (or more). And a GPIO can only be used as reset-gpio on a single PHY. + * Attaching it to a single PHY would still reset the other PHYs on + * the same chip as a side effect, leaving their software state out of + * sync with the hardware and likely breaking them. + */ + phy_reset1 { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "phy-reset-lan1-4"; + }; + + /* + * GPIO 10 is the global reset shared by (logical) PHYs 8-11 on MDIO + * bus0. It is intentionally not declared as reset-gpios on any bus: + * the MDIO driver / phylink only support a single reset GPIO per bus, + * not two (or more). And a GPIO can only be used as reset-gpio on a + * single PHY. Attaching it to a single PHY would still reset the other + * PHYs on the same chip as a side effect, leaving their software state + * out of sync with the hardware and likely breaking them. + */ + phy_reset2 { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-low; + line-name = "phy-reset-lan5-8"; + }; +};