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mediatek: rax3000m: add Airoha AN8855 switch support

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This commit adds support for Airoha AN8855 switch to RAX000Me

Fixes: https://github.com/openwrt/openwrt/issues/21230
Signed-off-by: air jinkela <air_jinkela@163.com>
Link: https://github.com/openwrt/openwrt/pull/21171
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
air jinkela 2025-12-15 22:24:08 +08:00 committed by Hauke Mehrtens
parent 53931f03dd
commit 14d09b78b5
1 changed files with 147 additions and 0 deletions
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147
target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts
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@ -105,6 +105,11 @@
interrupt-parent = <&pio>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
};
mfd: mfd@1 {
compatible = "airoha,an8855-mfd";
reg = <1>;
};
};
&switch {
@ -141,6 +146,148 @@
};
};
&mfd {
efuse {
compatible = "airoha,an8855-efuse";
#nvmem-cell-cells = <0>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
reg = <0xc 0x4>;
};
shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
reg = <0x10 0x4>;
};
shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
reg = <0x14 0x4>;
};
shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
reg = <0x18 0x4>;
};
shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
reg = <0x1c 0x4>;
};
shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
reg = <0x20 0x4>;
};
shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
reg = <0x24 0x4>;
};
shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
reg = <0x28 0x4>;
};
shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c {
reg = <0x2c 0x4>;
};
shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 {
reg = <0x30 0x4>;
};
shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 {
reg = <0x34 0x4>;
};
shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 {
reg = <0x38 0x4>;
};
};
};
ethernet-switch {
compatible = "airoha,an8855-switch";
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
airoha,ext-surge;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&internal_phy1>;
};
port@1 {
reg = <1>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&internal_phy2>;
};
port@2 {
reg = <2>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&internal_phy3>;
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
mdio {
compatible = "airoha,an8855-mdio";
#address-cells = <1>;
#size-cells = <0>;
internal_phy1: phy@1 {
reg = <1>;
nvmem-cells = <&shift_sel_port0_tx_a>,
<&shift_sel_port0_tx_b>,
<&shift_sel_port0_tx_c>,
<&shift_sel_port0_tx_d>;
nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
};
internal_phy2: phy@2 {
reg = <2>;
nvmem-cells = <&shift_sel_port1_tx_a>,
<&shift_sel_port1_tx_b>,
<&shift_sel_port1_tx_c>,
<&shift_sel_port1_tx_d>;
nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
};
internal_phy3: phy@3 {
reg = <3>;
nvmem-cells = <&shift_sel_port2_tx_a>,
<&shift_sel_port2_tx_b>,
<&shift_sel_port2_tx_c>,
<&shift_sel_port2_tx_d>;
nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
};
};
};
&uart0 {
status = "okay";
};