diff --git a/target/linux/mediatek/patches-6.18/001-clk-mediatek-add-MUX_CLR_SET-macro.patch b/target/linux/mediatek/patches-6.18/001-clk-mediatek-add-MUX_CLR_SET-macro.patch new file mode 100644 index 0000000000..d377e19bbb --- /dev/null +++ b/target/linux/mediatek/patches-6.18/001-clk-mediatek-add-MUX_CLR_SET-macro.patch @@ -0,0 +1,33 @@ +From 2aa7f2c64ef2ebbfbf08df5a86b9fadf1498c34e Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 26 Mar 2026 05:09:35 +0000 +Subject: [PATCH 1/3] clk: mediatek: add MUX_CLR_SET macro + +Some MediaTek SoCs (e.g. MT7988) define infra muxes that have neither +a clock gate nor an update register. + +Add a MUX_CLR_SET convenience macro that takes only the mux register +offsets, bit shift, and width, hardcoding upd_ofs = 0 and +upd_shift = -1 so callers cannot accidentally pass bogus sentinel +values to wrongly-typed fields. + +Signed-off-by: Daniel Golle +Reviewed-by: Chen-Yu Tsai +--- + drivers/clk/mediatek/clk-mux.h | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/clk/mediatek/clk-mux.h ++++ b/drivers/clk/mediatek/clk-mux.h +@@ -126,6 +126,11 @@ extern const struct clk_ops mtk_mux_gate + 0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \ + mtk_mux_clr_set_upd_ops) + ++#define MUX_CLR_SET(_id, _name, _parents, _mux_ofs, \ ++ _mux_set_ofs, _mux_clr_ofs, _shift, _width) \ ++ MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ ++ _mux_set_ofs, _mux_clr_ofs, _shift, _width, 0, -1) ++ + #define MUX_GATE_HWV_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs, \ diff --git a/target/linux/mediatek/patches-6.18/002-clk-mediatek-mt8192-use-MUX_CLR_SET.patch b/target/linux/mediatek/patches-6.18/002-clk-mediatek-mt8192-use-MUX_CLR_SET.patch new file mode 100644 index 0000000000..92a2f17d0e --- /dev/null +++ b/target/linux/mediatek/patches-6.18/002-clk-mediatek-mt8192-use-MUX_CLR_SET.patch @@ -0,0 +1,35 @@ +From 3799622e1c3a181f995ce1da7415f38299138630 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 26 Mar 2026 05:10:47 +0000 +Subject: [PATCH 2/3] clk: mediatek: mt8192: use MUX_CLR_SET + +The mfg_pll_sel mux has neither a clock gate nor an update register, +and upd_ofs is stored as u32, so the -1 truncates to 0xFFFFFFFF. + +While upd_shift being -1 (as s8) prevents the update path from +executing at runtime, the bogus upd_ofs value is still stored in the +struct. + +Use MUX_CLR_SET to avoid passing sentinel values to wrongly-typed +fields. + +Fixes: 710573dee31b4 ("clk: mediatek: Add MT8192 basic clocks support") +Signed-off-by: Daniel Golle +Reviewed-by: Chen-Yu Tsai +--- + drivers/clk/mediatek/clk-mt8192.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/clk/mediatek/clk-mt8192.c ++++ b/drivers/clk/mediatek/clk-mt8192.c +@@ -579,8 +579,8 @@ static const struct mtk_mux top_mtk_muxe + dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel", + mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18), +- MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", +- mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1), ++ MUX_CLR_SET(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", mfg_pll_parents, ++ 0x050, 0x054, 0x058, 18, 1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", + camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19), + /* CLK_CFG_5 */ diff --git a/target/linux/mediatek/patches-6.18/003-clk-mediatek-mt7988-use-MUX_CLR_SET-for-gate-less-mu.patch b/target/linux/mediatek/patches-6.18/003-clk-mediatek-mt7988-use-MUX_CLR_SET-for-gate-less-mu.patch new file mode 100644 index 0000000000..0e3322803e --- /dev/null +++ b/target/linux/mediatek/patches-6.18/003-clk-mediatek-mt7988-use-MUX_CLR_SET-for-gate-less-mu.patch @@ -0,0 +1,127 @@ +From 70acfc3433040fa9c26a070d4c2fdaf205e29b03 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 26 Mar 2026 05:11:12 +0000 +Subject: [PATCH 3/3] clk: mediatek: mt7988: use MUX_CLR_SET for gate-less + muxes + +All 19 muxes in the infra_muxes[] array are pure mux selectors without +a clock gate or update register, yet they were defined using +MUX_GATE_CLR_SET_UPD with gate_shift = -1. + +This macro assigns mtk_mux_gate_clr_set_upd_ops, whose +enable/disable/is_enabled callbacks perform BIT(gate_shift). Since +gate_shift is stored as u8, the -1 truncates to 255, causing a +shift-out-of-bounds at runtime: + +UBSAN: shift-out-of-bounds in drivers/clk/mediatek/clk-mux.c:76:8 +shift exponent 255 is too large for 64-bit type 'long unsigned int' + +UBSAN: shift-out-of-bounds in drivers/clk/mediatek/clk-mux.c:102:4 +shift exponent 255 is too large for 64-bit type 'long unsigned int' + +UBSAN: shift-out-of-bounds in drivers/clk/mediatek/clk-mux.c:122:16 +shift exponent 255 is too large for 64-bit type 'long unsigned int' + +Switch these definitions to MUX_CLR_SET, which uses +mtk_mux_clr_set_upd_ops (no gate callbacks) and does not require +callers to pass sentinel values for unused update register fields. +The actual clock gating for these peripherals is handled by the +separate GATE_INFRA* definitions further down. + +Fixes: 4b4719437d85f ("clk: mediatek: add drivers for MT7988 SoC") +Signed-off-by: Daniel Golle +Reviewed-by: Chen-Yu Tsai +--- + drivers/clk/mediatek/clk-mt7988-infracfg.c | 80 ++++++++++------------ + 1 file changed, 38 insertions(+), 42 deletions(-) + +--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c ++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c +@@ -56,49 +56,45 @@ static const char *const infra_pcie_gfmu + + static const struct mtk_mux infra_muxes[] = { + /* MODULE_CLK_SEL_0 */ +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", +- infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", +- infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", +- infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents, +- 0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents, +- 0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents, +- 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018, +- 0x0010, 0x0014, 14, 2, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents, +- 0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents, +- 0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents, +- 0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents, +- 0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents, +- 0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents, +- 0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents, +- 0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents, +- 0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1), ++ MUX_CLR_SET(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", ++ infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1), ++ MUX_CLR_SET(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", ++ infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1), ++ MUX_CLR_SET(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", ++ infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1), ++ MUX_CLR_SET(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", ++ infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1), ++ MUX_CLR_SET(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", ++ infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1), ++ MUX_CLR_SET(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", ++ infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1), ++ MUX_CLR_SET(CLK_INFRA_PWM_SEL, "infra_pwm_sel", ++ infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14, 2), ++ MUX_CLR_SET(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", ++ infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16, 2), ++ MUX_CLR_SET(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", ++ infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18, 2), ++ MUX_CLR_SET(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", ++ infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20, 2), ++ MUX_CLR_SET(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", ++ infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22, 2), ++ MUX_CLR_SET(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", ++ infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24, 2), ++ MUX_CLR_SET(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", ++ infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26, 2), ++ MUX_CLR_SET(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", ++ infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28, 2), ++ MUX_CLR_SET(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", ++ infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30, 2), + /* MODULE_CLK_SEL_1 */ +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel", +- infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1, +- -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel", +- infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1, +- -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel", +- infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1, +- -1, -1), +- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel", +- infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1, +- -1, -1), ++ MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel", ++ infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2), ++ MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel", ++ infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2), ++ MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel", ++ infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2), ++ MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel", ++ infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2), + }; + + static const struct mtk_gate_regs infra0_cg_regs = { diff --git a/target/linux/mediatek/patches-6.18/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch b/target/linux/mediatek/patches-6.18/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch deleted file mode 100644 index 2dcdbcffe4..0000000000 --- a/target/linux/mediatek/patches-6.18/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 1673d720b7e2862a5ff1994922558b7427f8a56b Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 17 Dec 2024 09:54:26 +0100 -Subject: [PATCH 1/2] pinctrl: mediatek: add support for MTK_PULL_PD_TYPE - -The MediaTek MT7988 SoC got some pins which only got configurable -pull-down but unlike previous designs there is no pull-up option. -Add new type MTK_PULL_PD_TYPE to support configuring such pins. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/20241217085435.9586-2-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 73 ++++++++++++++++--- - .../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 + - 2 files changed, 63 insertions(+), 11 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -@@ -573,7 +573,7 @@ EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_r - */ - static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, -- u32 pullup, u32 arg) -+ u32 pullup, u32 arg, bool pd_only) - { - int err, pu, pd; - -@@ -587,18 +587,34 @@ static int mtk_pinconf_bias_set_pu_pd(st - pu = 0; - pd = 1; - } else { -- err = -EINVAL; -- goto out; -+ return -EINVAL; - } - -- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu); -- if (err) -- goto out; -+ if (!pd_only) { -+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu); -+ if (err) -+ return err; -+ } - -- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); -+ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); -+} -+ -+static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 pullup, u32 arg) -+{ -+ int err, pd; -+ -+ if (arg != MTK_DISABLE && arg != MTK_ENABLE) -+ return -EINVAL; -+ -+ if (arg == MTK_DISABLE || pullup) -+ pd = 0; -+ else if (!pullup) -+ pd = 1; -+ -+ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); - --out: -- return err; - } - - static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, -@@ -737,7 +753,7 @@ static int mtk_pinconf_bias_set_pu_pd_rs - return err; - } - -- return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable); -+ return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable, false); - } - - int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, -@@ -758,8 +774,14 @@ int mtk_pinconf_bias_set_combo(struct mt - return 0; - } - -+ if (try_all_type & MTK_PULL_PD_TYPE) { -+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, true); -+ if (!err) -+ return err; -+ } -+ - if (try_all_type & MTK_PULL_PU_PD_TYPE) { -- err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); -+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, false); - if (!err) - return 0; - } -@@ -878,6 +900,29 @@ out: - return err; - } - -+static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 *pullup, u32 *enable) -+{ -+ int err, pd; -+ -+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); -+ if (err) -+ goto out; -+ -+ if (pd == 0) { -+ *pullup = 0; -+ *enable = MTK_DISABLE; -+ } else if (pd == 1) { -+ *pullup = 0; -+ *enable = MTK_ENABLE; -+ } else -+ err = -EINVAL; -+ -+out: -+ return err; -+} -+ - static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, - u32 *pullup, u32 *enable) -@@ -947,6 +992,12 @@ int mtk_pinconf_bias_get_combo(struct mt - return 0; - } - -+ if (try_all_type & MTK_PULL_PD_TYPE) { -+ err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable); -+ if (!err) -+ return err; -+ } -+ - if (try_all_type & MTK_PULL_PU_PD_TYPE) { - err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); - if (!err) ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h -@@ -24,6 +24,7 @@ - * turned on/off itself. But it can't be selected pull up/down - */ - #define MTK_PULL_RSEL_TYPE BIT(3) -+#define MTK_PULL_PD_TYPE BIT(4) - /* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by - * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE. - */ diff --git a/target/linux/mediatek/patches-6.18/010-v7.0-mtd-spinand-add-support-for-Dosilicon-DS35Q1GA-DS35M.patch b/target/linux/mediatek/patches-6.18/010-v7.0-mtd-spinand-add-support-for-Dosilicon-DS35Q1GA-DS35M.patch new file mode 100644 index 0000000000..9e2498cc58 --- /dev/null +++ b/target/linux/mediatek/patches-6.18/010-v7.0-mtd-spinand-add-support-for-Dosilicon-DS35Q1GA-DS35M.patch @@ -0,0 +1,158 @@ +From a75a1dec037ff3de863375fa3a74569619667184 Mon Sep 17 00:00:00 2001 +From: Ahmed Naseef +Date: Tue, 9 Dec 2025 11:16:02 +0400 +Subject: [PATCH] mtd: spinand: add support for Dosilicon DS35Q1GA/DS35M1GA + +Add support for Dosilicon DS35Q1GA (3.3V) and DS35M1GA (1.8V) SPI NAND. + +These are 1Gbit (128MB) devices with: + - 2048 byte pages + 64 byte OOB + - 64 pages per block, 1024 blocks + - On-die 4-bit ECC per 512 byte sector + +The 64-byte OOB area is divided into 4 segments of 16 bytes, with each +segment containing 8 bytes of user data (M2+M1) and 8 bytes of ECC +parity (R1). This provides 30 bytes of usable OOB space after reserving +2 bytes for the bad block marker. + +Tested on Genexis Platinum 4410 (EcoNet EN751221) by writing known +patterns to OOB and verifying ECC parity placement in R1 regions. + +Datasheet: + https://www.dosilicon.com/resources/SPI%20NAND/DS35X1GAXXX_rev08.pdf + +Signed-off-by: Ahmed Naseef +Signed-off-by: Miquel Raynal +--- + drivers/mtd/nand/spi/Makefile | 4 +- + drivers/mtd/nand/spi/core.c | 1 + + drivers/mtd/nand/spi/dosilicon.c | 91 ++++++++++++++++++++++++++++++++ + include/linux/mtd/spinand.h | 1 + + 4 files changed, 95 insertions(+), 2 deletions(-) + create mode 100644 drivers/mtd/nand/spi/dosilicon.c + +--- a/drivers/mtd/nand/spi/Makefile ++++ b/drivers/mtd/nand/spi/Makefile +@@ -1,5 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0 + spinand-objs := core.o otp.o +-spinand-objs += alliancememory.o ato.o esmt.o etron.o fmsh.o foresee.o gigadevice.o +-spinand-objs += macronix.o micron.o paragon.o skyhigh.o toshiba.o winbond.o xtx.o ++spinand-objs += alliancememory.o ato.o dosilicon.o esmt.o etron.o fmsh.o foresee.o ++spinand-objs += gigadevice.o macronix.o micron.o paragon.o skyhigh.o toshiba.o ++spinand-objs += winbond.o xtx.o + obj-$(CONFIG_MTD_SPI_NAND) += spinand.o +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -1235,6 +1235,7 @@ static const struct nand_ops spinand_ops + static const struct spinand_manufacturer *spinand_manufacturers[] = { + &alliancememory_spinand_manufacturer, + &ato_spinand_manufacturer, ++ &dosilicon_spinand_manufacturer, + &esmt_8c_spinand_manufacturer, + &esmt_c8_spinand_manufacturer, + &etron_spinand_manufacturer, +--- /dev/null ++++ b/drivers/mtd/nand/spi/dosilicon.c +@@ -0,0 +1,91 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Author: Ahmed Naseef ++ */ ++ ++#include ++#include ++#include ++ ++#define SPINAND_MFR_DOSILICON 0xE5 ++ ++static SPINAND_OP_VARIANTS(read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(0, 1, NULL, 0, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 0)); ++ ++static SPINAND_OP_VARIANTS(write_cache_variants, ++ SPINAND_PROG_LOAD_1S_1S_4S_OP(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(update_cache_variants, ++ SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0), ++ SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); ++ ++static int ds35xx_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = 8 + (section * 16); ++ region->length = 8; ++ ++ return 0; ++} ++ ++static int ds35xx_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ if (section == 0) { ++ /* reserve 2 bytes for the BBM */ ++ region->offset = 2; ++ region->length = 6; ++ } else { ++ region->offset = section * 16; ++ region->length = 8; ++ } ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops ds35xx_ooblayout = { ++ .ecc = ds35xx_ooblayout_ecc, ++ .free = ds35xx_ooblayout_free, ++}; ++ ++static const struct spinand_info dosilicon_spinand_table[] = { ++ SPINAND_INFO("DS35Q1GA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xx_ooblayout, NULL)), ++ SPINAND_INFO("DS35M1GA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x21), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xx_ooblayout, NULL)), ++}; ++ ++static const struct spinand_manufacturer_ops dosilicon_spinand_manuf_ops = { ++}; ++ ++const struct spinand_manufacturer dosilicon_spinand_manufacturer = { ++ .id = SPINAND_MFR_DOSILICON, ++ .name = "Dosilicon", ++ .chips = dosilicon_spinand_table, ++ .nchips = ARRAY_SIZE(dosilicon_spinand_table), ++ .ops = &dosilicon_spinand_manuf_ops, ++}; +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -354,6 +354,7 @@ struct spinand_manufacturer { + /* SPI NAND manufacturers */ + extern const struct spinand_manufacturer alliancememory_spinand_manufacturer; + extern const struct spinand_manufacturer ato_spinand_manufacturer; ++extern const struct spinand_manufacturer dosilicon_spinand_manufacturer; + extern const struct spinand_manufacturer esmt_8c_spinand_manufacturer; + extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; + extern const struct spinand_manufacturer etron_spinand_manufacturer; diff --git a/target/linux/mediatek/patches-6.18/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch b/target/linux/mediatek/patches-6.18/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch deleted file mode 100644 index d94a0ba60b..0000000000 --- a/target/linux/mediatek/patches-6.18/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch +++ /dev/null @@ -1,1610 +0,0 @@ -From 08bec851118226cc8c4397692542b855de2e0d73 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 17 Dec 2024 09:54:27 +0100 -Subject: [PATCH 2/2] pinctrl: mediatek: add MT7988 pinctrl driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add pinctrl driver for the MediaTek MT7988 SoC. - -Signed-off-by: Sam Shih -Signed-off-by: Daniel Golle -[correctly initialise for the function_desc structure] -Signed-off-by: Arınç ÜNAL -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/20241217085435.9586-3-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/Kconfig | 7 + - drivers/pinctrl/mediatek/Makefile | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1556 +++++++++++++++++++++ - 3 files changed, 1564 insertions(+) - create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7988.c - ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -187,6 +187,13 @@ config PINCTRL_MT7986 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7988 -+ bool "Mediatek MT7988 pin control" -+ depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARM64 && ARCH_MEDIATEK -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT8167 - bool "MediaTek MT8167 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o - obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o -+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o - obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o ---- /dev/null -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c -@@ -0,0 +1,1556 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * The MT7988 driver based on Linux generic pinctrl binding. -+ * -+ * Copyright (C) 2020 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#include "pinctrl-moore.h" -+ -+enum mt7988_pinctrl_reg_page { -+ GPIO_BASE, -+ IOCFG_TR_BASE, -+ IOCFG_BR_BASE, -+ IOCFG_RB_BASE, -+ IOCFG_LB_BASE, -+ IOCFG_TL_BASE, -+}; -+ -+#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) -+ -+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits) \ -+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 0) -+ -+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits) \ -+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 1) -+ -+static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { -+ PIN_FIELD(0, 83, 0x300, 0x10, 0, 4), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { -+ PIN_FIELD(0, 83, 0x0, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { -+ PIN_FIELD(0, 83, 0x200, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { -+ PIN_FIELD(0, 83, 0x100, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { -+ PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1), -+ PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1), -+ PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1), -+ PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), -+ PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1), -+ PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1), -+ PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), -+ PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), -+ PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1), -+ PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1), -+ -+ PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1), -+ -+ PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), -+ PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), -+ -+ PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1), -+ PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1), -+ PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1), -+ PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { -+ PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1), -+ PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1), -+ PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1), -+ PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1), -+ PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), -+ PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), -+ PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), -+ PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1), -+ PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1), -+ PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1), -+ PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1), -+ PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), -+ PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1), -+ PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1), -+ PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), -+ PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1), -+ PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1), -+ PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1), -+ PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), -+ PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), -+ PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), -+ PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1), -+ PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1), -+ PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1), -+ PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1), -+ PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1), -+ -+ PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1), -+ PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1), -+ PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1), -+ -+ PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), -+ PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), -+ PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), -+ PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1), -+ PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), -+ PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), -+ PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), -+ -+ PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1), -+ PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1), -+ PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1), -+ PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { -+ PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), -+ PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), -+ PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), -+ PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { -+ PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { -+ PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3), -+ -+ PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), -+ PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), -+ -+ PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), -+ PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), -+ -+ PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), -+ PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), -+ PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), -+ PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), -+ PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3), -+ PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3), -+ PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), -+ PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3), -+ PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3), -+ PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3), -+ PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), -+ PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), -+ PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), -+ PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3), -+ PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3), -+ PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3), -+ PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), -+ PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), -+ PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), -+ PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3), -+ PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3), -+ PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3), -+ PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), -+ -+ PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3), -+ PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3), -+ PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), -+ PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), -+ PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3), -+ PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), -+ PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3), -+ PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3), -+ PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3), -+ PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { -+ PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), -+ -+ PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1), -+ PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1), -+ PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), -+ PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1), -+ PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), -+ PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1), -+ PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1), -+ PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1), -+ PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1), -+ PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), -+ -+ PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1), -+ PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1), -+ PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1), -+ PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { -+ PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1), -+ PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1), -+ PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), -+ -+ PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1), -+ PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1), -+ PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), -+ PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1), -+ PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1), -+ PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1), -+ PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), -+ PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), -+ PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1), -+ PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1), -+ PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1), -+ PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1), -+ PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), -+ -+ PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1), -+ PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1), -+ PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1), -+ PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { -+ PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1), -+ PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1), -+ PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), -+ -+ PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1), -+ PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1), -+ PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), -+ PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), -+ PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1), -+ PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), -+ PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), -+ -+ PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1), -+ PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1), -+ PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1), -+ PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1), -+}; -+ -+static const unsigned int mt7988_pull_type[] = { -+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE, /*7*/ -+ MTK_PULL_PU_PD_TYPE, /*8*/ MTK_PULL_PU_PD_TYPE, /*9*/ -+ MTK_PULL_PU_PD_TYPE, /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE, /*13*/ -+ MTK_PULL_PU_PD_TYPE, /*14*/ MTK_PULL_PD_TYPE, /*15*/ -+ MTK_PULL_PD_TYPE, /*16*/ MTK_PULL_PD_TYPE, /*17*/ -+ MTK_PULL_PD_TYPE, /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE, /*63*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE, /*71*/ -+ MTK_PULL_PD_TYPE, /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE, /*75*/ -+ MTK_PULL_PU_PD_TYPE, /*76*/ MTK_PULL_PU_PD_TYPE, /*77*/ -+ MTK_PULL_PU_PD_TYPE, /*78*/ MTK_PULL_PU_PD_TYPE, /*79*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/ -+}; -+ -+static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { -+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), -+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), -+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), -+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), -+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), -+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), -+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), -+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), -+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), -+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), -+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), -+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), -+}; -+ -+static const struct mtk_pin_desc mt7988_pins[] = { -+ MT7988_PIN(0, "UART2_RXD"), -+ MT7988_PIN(1, "UART2_TXD"), -+ MT7988_PIN(2, "UART2_CTS"), -+ MT7988_PIN(3, "UART2_RTS"), -+ MT7988_PIN(4, "GPIO_A"), -+ MT7988_PIN(5, "SMI_0_MDC"), -+ MT7988_PIN(6, "SMI_0_MDIO"), -+ MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"), -+ MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"), -+ MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"), -+ MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"), -+ MT7988_PIN(11, "GPIO_P"), -+ MT7988_PIN(12, "WATCHDOG"), -+ MT7988_PIN(13, "GPIO_RESET"), -+ MT7988_PIN(14, "GPIO_WPS"), -+ MT7988_PIN(15, "PMIC_I2C_SCL"), -+ MT7988_PIN(16, "PMIC_I2C_SDA"), -+ MT7988_PIN(17, "I2C_1_SCL"), -+ MT7988_PIN(18, "I2C_1_SDA"), -+ MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"), -+ MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"), -+ MT7988_PIN(21, "PWMD1"), -+ MT7988_PIN(22, "SPI0_WP"), -+ MT7988_PIN(23, "SPI0_HOLD"), -+ MT7988_PIN(24, "SPI0_CSB"), -+ MT7988_PIN(25, "SPI0_MISO"), -+ MT7988_PIN(26, "SPI0_MOSI"), -+ MT7988_PIN(27, "SPI0_CLK"), -+ MT7988_PIN(28, "SPI1_CSB"), -+ MT7988_PIN(29, "SPI1_MISO"), -+ MT7988_PIN(30, "SPI1_MOSI"), -+ MT7988_PIN(31, "SPI1_CLK"), -+ MT7988_PIN(32, "SPI2_CLK"), -+ MT7988_PIN(33, "SPI2_MOSI"), -+ MT7988_PIN(34, "SPI2_MISO"), -+ MT7988_PIN(35, "SPI2_CSB"), -+ MT7988_PIN(36, "SPI2_HOLD"), -+ MT7988_PIN(37, "SPI2_WP"), -+ MT7988_PIN(38, "EMMC_RSTB"), -+ MT7988_PIN(39, "EMMC_DSL"), -+ MT7988_PIN(40, "EMMC_CK"), -+ MT7988_PIN(41, "EMMC_CMD"), -+ MT7988_PIN(42, "EMMC_DATA_7"), -+ MT7988_PIN(43, "EMMC_DATA_6"), -+ MT7988_PIN(44, "EMMC_DATA_5"), -+ MT7988_PIN(45, "EMMC_DATA_4"), -+ MT7988_PIN(46, "EMMC_DATA_3"), -+ MT7988_PIN(47, "EMMC_DATA_2"), -+ MT7988_PIN(48, "EMMC_DATA_1"), -+ MT7988_PIN(49, "EMMC_DATA_0"), -+ MT7988_PIN(50, "PCM_FS_I2S_LRCK"), -+ MT7988_PIN(51, "PCM_CLK_I2S_BCLK"), -+ MT7988_PIN(52, "PCM_DRX_I2S_DIN"), -+ MT7988_PIN(53, "PCM_DTX_I2S_DOUT"), -+ MT7988_PIN(54, "PCM_MCK_I2S_MCLK"), -+ MT7988_PIN(55, "UART0_RXD"), -+ MT7988_PIN(56, "UART0_TXD"), -+ MT7988_PIN(57, "PWMD0"), -+ MT7988_PIN(58, "JTAG_JTDI"), -+ MT7988_PIN(59, "JTAG_JTDO"), -+ MT7988_PIN(60, "JTAG_JTMS"), -+ MT7988_PIN(61, "JTAG_JTCLK"), -+ MT7988_PIN(62, "JTAG_JTRST_N"), -+ MT7988_PIN(63, "USB_DRV_VBUS_P1"), -+ MT7988_PIN(64, "LED_A"), -+ MT7988_PIN(65, "LED_B"), -+ MT7988_PIN(66, "LED_C"), -+ MT7988_PIN(67, "LED_D"), -+ MT7988_PIN(68, "LED_E"), -+ MT7988_PIN(69, "GPIO_B"), -+ MT7988_PIN(70, "GPIO_C"), -+ MT7988_PIN(71, "I2C_2_SCL"), -+ MT7988_PIN(72, "I2C_2_SDA"), -+ MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"), -+ MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"), -+ MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"), -+ MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"), -+ MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"), -+ MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"), -+ MT7988_PIN(79, "USB_DRV_VBUS_P0"), -+ MT7988_PIN(80, "UART1_RXD"), -+ MT7988_PIN(81, "UART1_TXD"), -+ MT7988_PIN(82, "UART1_CTS"), -+ MT7988_PIN(83, "UART1_RTS"), -+}; -+ -+/* jtag */ -+static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; -+static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; -+ -+static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; -+static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; -+ -+static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; -+static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; -+ -+static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; -+static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; -+ -+static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; -+static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; -+ -+static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; -+static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; -+ -+/* int_usxgmii */ -+static const int mt7988_int_usxgmii_pins[] = { 2, 3 }; -+static int mt7988_int_usxgmii_funcs[] = { 3, 3 }; -+ -+/* pwm */ -+static const int mt7988_pwm0_pins[] = { 57 }; -+static int mt7988_pwm0_funcs[] = { 1 }; -+ -+static const int mt7988_pwm1_pins[] = { 21 }; -+static int mt7988_pwm1_funcs[] = { 1 }; -+ -+static const int mt7988_pwm2_pins[] = { 80 }; -+static int mt7988_pwm2_funcs[] = { 2 }; -+ -+static const int mt7988_pwm2_0_pins[] = { 58 }; -+static int mt7988_pwm2_0_funcs[] = { 5 }; -+ -+static const int mt7988_pwm3_pins[] = { 81 }; -+static int mt7988_pwm3_funcs[] = { 2 }; -+ -+static const int mt7988_pwm3_0_pins[] = { 59 }; -+static int mt7988_pwm3_0_funcs[] = { 5 }; -+ -+static const int mt7988_pwm4_pins[] = { 82 }; -+static int mt7988_pwm4_funcs[] = { 2 }; -+ -+static const int mt7988_pwm4_0_pins[] = { 60 }; -+static int mt7988_pwm4_0_funcs[] = { 5 }; -+ -+static const int mt7988_pwm5_pins[] = { 83 }; -+static int mt7988_pwm5_funcs[] = { 2 }; -+ -+static const int mt7988_pwm5_0_pins[] = { 61 }; -+static int mt7988_pwm5_0_funcs[] = { 5 }; -+ -+static const int mt7988_pwm6_pins[] = { 69 }; -+static int mt7988_pwm6_funcs[] = { 3 }; -+ -+static const int mt7988_pwm6_0_pins[] = { 62 }; -+static int mt7988_pwm6_0_funcs[] = { 5 }; -+ -+static const int mt7988_pwm7_pins[] = { 70 }; -+static int mt7988_pwm7_funcs[] = { 3 }; -+ -+static const int mt7988_pwm7_0_pins[] = { 4 }; -+static int mt7988_pwm7_0_funcs[] = { 3 }; -+ -+/* dfd */ -+static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; -+static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; -+ -+/* i2c */ -+static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; -+static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; -+ -+static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; -+static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; -+ -+static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; -+static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; -+ -+static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; -+static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; -+ -+static const int mt7988_i2c0_0_pins[] = { 5, 6 }; -+static int mt7988_i2c0_0_funcs[] = { 2, 2 }; -+ -+static const int mt7988_i2c1_sfp_pins[] = { 5, 6 }; -+static int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; -+ -+static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; -+static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; -+ -+static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; -+static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; -+ -+static const int mt7988_i2c0_1_pins[] = { 15, 16 }; -+static int mt7988_i2c0_1_funcs[] = { 1, 1 }; -+ -+static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; -+static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; -+ -+static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; -+static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; -+ -+static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; -+static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; -+ -+static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; -+static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; -+ -+static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; -+static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; -+ -+static const int mt7988_i2c1_0_pins[] = { 17, 18 }; -+static int mt7988_i2c1_0_funcs[] = { 1, 1 }; -+ -+static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; -+static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; -+ -+static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; -+static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; -+ -+static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; -+static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; -+ -+static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; -+static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; -+ -+static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; -+static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; -+ -+static const int mt7988_i2c1_2_pins[] = { 69, 70 }; -+static int mt7988_i2c1_2_funcs[] = { 2, 2 }; -+ -+static const int mt7988_i2c2_0_pins[] = { 69, 70 }; -+static int mt7988_i2c2_0_funcs[] = { 4, 4 }; -+ -+static const int mt7988_i2c2_1_pins[] = { 71, 72 }; -+static int mt7988_i2c2_1_funcs[] = { 1, 1 }; -+ -+/* eth */ -+static const int mt7988_mdc_mdio0_pins[] = { 5, 6 }; -+static int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; -+ -+static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; -+static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; -+ -+static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; -+static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; -+ -+static const int mt7988_mdc_mdio1_pins[] = { 69, 70 }; -+static int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; -+ -+/* pcie */ -+static const int mt7988_pcie_wake_n0_0_pins[] = { 7 }; -+static int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; -+static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_wake_n3_0_pins[] = { 9 }; -+static int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n3_pins[] = { 10 }; -+static int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; -+static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; -+ -+static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; -+static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; -+ -+static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; -+static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; -+ -+static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; -+static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; -+ -+static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; -+static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; -+ -+static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; -+static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; -+ -+static const int mt7988_pcie_wake_n0_1_pins[] = { 13 }; -+static int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; -+ -+static const int mt7988_pcie_wake_n3_1_pins[] = { 14 }; -+static int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; -+ -+static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; -+static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; -+static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; -+static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; -+ -+static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; -+static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; -+static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_wake_n1_0_pins[] = { 75 }; -+static int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n1_pins[] = { 76 }; -+static int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_wake_n2_0_pins[] = { 77 }; -+static int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; -+static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_wake_n2_1_pins[] = { 79 }; -+static int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; -+ -+/* pmic */ -+static const int mt7988_pmic_pins[] = { 11 }; -+static int mt7988_pmic_funcs[] = { 1 }; -+ -+/* watchdog */ -+static const int mt7988_watchdog_pins[] = { 12 }; -+static int mt7988_watchdog_funcs[] = { 1 }; -+ -+/* spi */ -+static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; -+static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; -+ -+static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; -+static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; -+static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; -+static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; -+static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; -+ -+/* flash */ -+static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; -+static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; -+ -+static const int mt7988_emmc_45_pins[] = { -+ 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 -+}; -+static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; -+ -+static const int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 }; -+static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 }; -+ -+static const int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43, -+ 44, 45, 46, 47, 48, 49 }; -+static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; -+ -+/* uart */ -+static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; -+static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_tops_uart0_0_pins[] = { 22, 23 }; -+static int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; -+ -+static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; -+static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; -+ -+static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; -+static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; -+ -+static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; -+static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; -+ -+static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; -+static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; -+ -+static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; -+static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; -+ -+static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; -+static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; -+ -+static const int mt7988_tops_uart1_0_pins[] = { 28, 29 }; -+static int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; -+ -+static const int mt7988_tops_uart0_1_pins[] = { 30, 31 }; -+static int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; -+ -+static const int mt7988_tops_uart1_1_pins[] = { 36, 37 }; -+static int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; -+ -+static const int mt7988_uart0_pins[] = { 55, 56 }; -+static int mt7988_uart0_funcs[] = { 1, 1 }; -+ -+static const int mt7988_tops_uart0_2_pins[] = { 55, 56 }; -+static int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; -+ -+static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; -+static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; -+ -+static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; -+static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; -+ -+static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; -+static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; -+ -+static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; -+static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_uart1_2_lite_pins[] = { 80, 81 }; -+static int mt7988_uart1_2_lite_funcs[] = { 1, 1 }; -+ -+static const int mt7988_tops_uart1_2_pins[] = { 80, 81 }; -+static int mt7988_tops_uart1_2_funcs[] = { 4, 4, }; -+ -+static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; -+static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; -+ -+static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; -+static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; -+ -+static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; -+static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; -+ -+/* udi */ -+static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; -+static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; -+ -+/* i2s */ -+static const int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 }; -+static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 }; -+ -+/* pcm */ -+static const int mt7988_pcm_pins[] = { 50, 51, 52, 53 }; -+static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 }; -+ -+/* led */ -+static const int mt7988_gbe0_led1_pins[] = { 58 }; -+static int mt7988_gbe0_led1_funcs[] = { 6 }; -+static const int mt7988_gbe1_led1_pins[] = { 59 }; -+static int mt7988_gbe1_led1_funcs[] = { 6 }; -+static const int mt7988_gbe2_led1_pins[] = { 60 }; -+static int mt7988_gbe2_led1_funcs[] = { 6 }; -+static const int mt7988_gbe3_led1_pins[] = { 61 }; -+static int mt7988_gbe3_led1_funcs[] = { 6 }; -+ -+static const int mt7988_2p5gbe_led1_pins[] = { 62 }; -+static int mt7988_2p5gbe_led1_funcs[] = { 6 }; -+ -+static const int mt7988_gbe0_led0_pins[] = { 64 }; -+static int mt7988_gbe0_led0_funcs[] = { 1 }; -+static const int mt7988_gbe1_led0_pins[] = { 65 }; -+static int mt7988_gbe1_led0_funcs[] = { 1 }; -+static const int mt7988_gbe2_led0_pins[] = { 66 }; -+static int mt7988_gbe2_led0_funcs[] = { 1 }; -+static const int mt7988_gbe3_led0_pins[] = { 67 }; -+static int mt7988_gbe3_led0_funcs[] = { 1 }; -+ -+static const int mt7988_2p5gbe_led0_pins[] = { 68 }; -+static int mt7988_2p5gbe_led0_funcs[] = { 1 }; -+ -+/* usb */ -+static const int mt7988_drv_vbus_p1_pins[] = { 63 }; -+static int mt7988_drv_vbus_p1_funcs[] = { 1 }; -+ -+static const int mt7988_drv_vbus_pins[] = { 79 }; -+static int mt7988_drv_vbus_funcs[] = { 1 }; -+ -+static const struct group_desc mt7988_groups[] = { -+ /* @GPIO(0,1,2,3): uart2 */ -+ PINCTRL_PIN_GROUP("uart2", mt7988_uart2), -+ /* @GPIO(0,1,2,3,4): tops_jtag0_0 */ -+ PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), -+ /* @GPIO(2,3): int_usxgmii */ -+ PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), -+ /* @GPIO(0,1,2,3,4): dfd */ -+ PINCTRL_PIN_GROUP("dfd", mt7988_dfd), -+ /* @GPIO(0,1): xfi_phy0_i2c0 */ -+ PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), -+ /* @GPIO(0,1): xfi_phy1_i2c0 */ -+ PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), -+ /* @GPIO(3,4): xfi_phy_pll_i2c0 */ -+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), -+ /* @GPIO(3,4): xfi_phy_pll_i2c1 */ -+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), -+ /* @GPIO(4): pwm7 */ -+ PINCTRL_PIN_GROUP("pwm7_0", mt7988_pwm7_0), -+ /* @GPIO(5,6) i2c0_0 */ -+ PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), -+ /* @GPIO(5,6) i2c1_sfp */ -+ PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), -+ /* @GPIO(5,6) xfi_pextp_phy0_i2c */ -+ PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), -+ /* @GPIO(5,6) xfi_pextp_phy1_i2c */ -+ PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), -+ /* @GPIO(5,6) mdc_mdio0 */ -+ PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), -+ /* @GPIO(7): pcie_wake_n0_0 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), -+ /* @GPIO(8): pcie_clk_req_n0_0 */ -+ PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), -+ /* @GPIO(9): pcie_wake_n3_0 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), -+ /* @GPIO(10): pcie_clk_req_n3 */ -+ PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), -+ /* @GPIO(10): pcie_clk_req_n0_1 */ -+ PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), -+ /* @GPIO(7,8) pcie_p0_phy_i2c */ -+ PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), -+ /* @GPIO(7,8) pcie_p1_phy_i2c */ -+ PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), -+ /* @GPIO(7,8) pcie_p2_phy_i2c */ -+ PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), -+ /* @GPIO(9,10) pcie_p3_phy_i2c */ -+ PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), -+ /* @GPIO(9,10) ckm_phy_i2c */ -+ PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), -+ /* @GPIO(11): pmic */ -+ PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), -+ /* @GPIO(12): watchdog */ -+ PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), -+ /* @GPIO(13): pcie_wake_n0_1 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), -+ /* @GPIO(14): pcie_wake_n3_1 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), -+ /* @GPIO(15,16) i2c0_1 */ -+ PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), -+ /* @GPIO(15,16) u30_phy_i2c0 */ -+ PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), -+ /* @GPIO(15,16) u32_phy_i2c0 */ -+ PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), -+ /* @GPIO(15,16) xfi_phy0_i2c1 */ -+ PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), -+ /* @GPIO(15,16) xfi_phy1_i2c1 */ -+ PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), -+ /* @GPIO(15,16) xfi_phy_pll_i2c2 */ -+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), -+ /* @GPIO(17,18) i2c1_0 */ -+ PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), -+ /* @GPIO(17,18) u30_phy_i2c1 */ -+ PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), -+ /* @GPIO(17,18) u32_phy_i2c1 */ -+ PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), -+ /* @GPIO(17,18) xfi_phy_pll_i2c3 */ -+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), -+ /* @GPIO(17,18) sgmii0_i2c */ -+ PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), -+ /* @GPIO(17,18) sgmii1_i2c */ -+ PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), -+ /* @GPIO(19): pcie_2l_0_pereset */ -+ PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), -+ /* @GPIO(20): pcie_1l_1_pereset */ -+ PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), -+ /* @GPIO(21): pwm1 */ -+ PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), -+ /* @GPIO(22,23) spi0_wp_hold */ -+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), -+ /* @GPIO(24,25,26,27) spi0 */ -+ PINCTRL_PIN_GROUP("spi0", mt7988_spi0), -+ /* @GPIO(28,29,30,31) spi1 */ -+ PINCTRL_PIN_GROUP("spi1", mt7988_spi1), -+ /* @GPIO(32,33,34,35) spi2 */ -+ PINCTRL_PIN_GROUP("spi2", mt7988_spi2), -+ /* @GPIO(36,37) spi2_wp_hold */ -+ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), -+ /* @GPIO(22,23,24,25,26,27) snfi */ -+ PINCTRL_PIN_GROUP("snfi", mt7988_snfi), -+ /* @GPIO(22,23) tops_uart0_0 */ -+ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), -+ /* @GPIO(28,29,30,31) uart2_0 */ -+ PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), -+ /* @GPIO(32,33,34,35) uart1_0 */ -+ PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), -+ /* @GPIO(32,33,34,35) uart2_1 */ -+ PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), -+ /* @GPIO(28) net_wo0_uart_txd_0 */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), -+ /* @GPIO(29) net_wo1_uart_txd_0 */ -+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), -+ /* @GPIO(30) net_wo2_uart_txd_0 */ -+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), -+ /* @GPIO(28,29) tops_uart1_0 */ -+ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), -+ /* @GPIO(30,31) tops_uart0_1 */ -+ PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), -+ /* @GPIO(36,37) tops_uart1_1 */ -+ PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), -+ /* @GPIO(32,33,34,35,36) udi */ -+ PINCTRL_PIN_GROUP("udi", mt7988_udi), -+ /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */ -+ PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), -+ /* @GPIO(32,33,34,35,36,37) sdcard */ -+ PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard), -+ /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */ -+ PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), -+ /* @GPIO(28,29) 2p5g_ext_mdio */ -+ PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), -+ /* @GPIO(30,31) gbe_ext_mdio */ -+ PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), -+ /* @GPIO(50,51,52,53,54) i2s */ -+ PINCTRL_PIN_GROUP("i2s", mt7988_i2s), -+ /* @GPIO(50,51,52,53) pcm */ -+ PINCTRL_PIN_GROUP("pcm", mt7988_pcm), -+ /* @GPIO(55,56) uart0 */ -+ PINCTRL_PIN_GROUP("uart0", mt7988_uart0), -+ /* @GPIO(55,56) tops_uart0_2 */ -+ PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), -+ /* @GPIO(50,51,52,53) uart2_2 */ -+ PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), -+ /* @GPIO(50,51,52,53,54) wo0_jtag */ -+ PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), -+ /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */ -+ PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), -+ /* @GPIO(50,51,52,53,54) wo2_jtag */ -+ PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), -+ /* @GPIO(57) pwm0 */ -+ PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), -+ /* @GPIO(58) pwm2_0 */ -+ PINCTRL_PIN_GROUP("pwm2_0", mt7988_pwm2_0), -+ /* @GPIO(59) pwm3_0 */ -+ PINCTRL_PIN_GROUP("pwm3_0", mt7988_pwm3_0), -+ /* @GPIO(60) pwm4_0 */ -+ PINCTRL_PIN_GROUP("pwm4_0", mt7988_pwm4_0), -+ /* @GPIO(61) pwm5_0 */ -+ PINCTRL_PIN_GROUP("pwm5_0", mt7988_pwm5_0), -+ /* @GPIO(58,59,60,61,62) jtag */ -+ PINCTRL_PIN_GROUP("jtag", mt7988_jtag), -+ /* @GPIO(58,59,60,61,62) tops_jtag0_1 */ -+ PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), -+ /* @GPIO(58,59,60,61) uart2_3 */ -+ PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), -+ /* @GPIO(58,59,60,61) uart1_1 */ -+ PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), -+ /* @GPIO(58,59,60,61) gbe_led1 */ -+ PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1), -+ PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1), -+ PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1), -+ PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1), -+ /* @GPIO(62) pwm6_0 */ -+ PINCTRL_PIN_GROUP("pwm6_0", mt7988_pwm6_0), -+ /* @GPIO(62) 2p5gbe_led1 */ -+ PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), -+ /* @GPIO(64,65,66,67) gbe_led0 */ -+ PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0), -+ PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0), -+ PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0), -+ PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0), -+ /* @GPIO(68) 2p5gbe_led0 */ -+ PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), -+ /* @GPIO(63) drv_vbus_p1 */ -+ PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), -+ /* @GPIO(63) pcie_clk_req_n2_1 */ -+ PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), -+ /* @GPIO(69, 70) mdc_mdio1 */ -+ PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), -+ /* @GPIO(69, 70) i2c1_2 */ -+ PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), -+ /* @GPIO(69) pwm6 */ -+ PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), -+ /* @GPIO(70) pwm7 */ -+ PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), -+ /* @GPIO(69,70) i2c2_0 */ -+ PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), -+ /* @GPIO(71,72) i2c2_1 */ -+ PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), -+ /* @GPIO(73) pcie_2l_1_pereset */ -+ PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), -+ /* @GPIO(74) pcie_1l_0_pereset */ -+ PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), -+ /* @GPIO(75) pcie_wake_n1_0 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), -+ /* @GPIO(76) pcie_clk_req_n1 */ -+ PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), -+ /* @GPIO(77) pcie_wake_n2_0 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), -+ /* @GPIO(78) pcie_clk_req_n2_0 */ -+ PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), -+ /* @GPIO(79) drv_vbus */ -+ PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), -+ /* @GPIO(79) pcie_wake_n2_1 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), -+ /* @GPIO(80,81,82,83) uart1_2 */ -+ PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), -+ /* @GPIO(80,81) uart1_2_lite */ -+ PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite), -+ /* @GPIO(80) pwm2 */ -+ PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), -+ /* @GPIO(81) pwm3 */ -+ PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), -+ /* @GPIO(82) pwm4 */ -+ PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), -+ /* @GPIO(83) pwm5 */ -+ PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), -+ /* @GPIO(80) net_wo0_uart_txd_0 */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), -+ /* @GPIO(81) net_wo1_uart_txd_0 */ -+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), -+ /* @GPIO(82) net_wo2_uart_txd_0 */ -+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), -+ /* @GPIO(80,81) tops_uart1_2 */ -+ PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), -+ /* @GPIO(80) net_wo0_uart_txd_1 */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), -+ /* @GPIO(81) net_wo1_uart_txd_1 */ -+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), -+ /* @GPIO(82) net_wo2_uart_txd_1 */ -+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), -+}; -+ -+/* Joint those groups owning the same capability in user point of view which -+ * allows that people tend to use through the device tree. -+ */ -+static const char * const mt7988_jtag_groups[] = { -+ "tops_jtag0_0", "wo0_jtag", "wo1_jtag", -+ "wo2_jtag", "jtag", "tops_jtag0_1", -+}; -+static const char * const mt7988_int_usxgmii_groups[] = { -+ "int_usxgmii", -+}; -+static const char * const mt7988_pwm_groups[] = { -+ "pwm0", "pwm1", "pwm2", "pwm2_0", "pwm3", "pwm3_0", "pwm4", "pwm4_0", -+ "pwm5", "pwm5_0", "pwm6", "pwm6_0", "pwm7", "pwm7_0", -+ -+}; -+static const char * const mt7988_dfd_groups[] = { -+ "dfd", -+}; -+static const char * const mt7988_i2c_groups[] = { -+ "xfi_phy0_i2c0", -+ "xfi_phy1_i2c0", -+ "xfi_phy_pll_i2c0", -+ "xfi_phy_pll_i2c1", -+ "i2c0_0", -+ "i2c1_sfp", -+ "xfi_pextp_phy0_i2c", -+ "xfi_pextp_phy1_i2c", -+ "i2c0_1", -+ "u30_phy_i2c0", -+ "u32_phy_i2c0", -+ "xfi_phy0_i2c1", -+ "xfi_phy1_i2c1", -+ "xfi_phy_pll_i2c2", -+ "i2c1_0", -+ "u30_phy_i2c1", -+ "u32_phy_i2c1", -+ "xfi_phy_pll_i2c3", -+ "sgmii0_i2c", -+ "sgmii1_i2c", -+ "i2c1_2", -+ "i2c2_0", -+ "i2c2_1", -+}; -+static const char * const mt7988_ethernet_groups[] = { -+ "mdc_mdio0", -+ "2p5g_ext_mdio", -+ "gbe_ext_mdio", -+ "mdc_mdio1", -+}; -+static const char * const mt7988_pcie_groups[] = { -+ "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", -+ "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", -+ "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", -+ "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset", -+ "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset", -+ "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1", -+ "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", -+ "pcie_clk_req_n0_1" -+}; -+static const char * const mt7988_pmic_groups[] = { -+ "pmic", -+}; -+static const char * const mt7988_wdt_groups[] = { -+ "watchdog", -+}; -+static const char * const mt7988_spi_groups[] = { -+ "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", -+}; -+static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", -+ "emmc_51" }; -+static const char * const mt7988_uart_groups[] = { -+ "uart2", -+ "tops_uart0_0", -+ "uart2_0", -+ "uart1_0", -+ "uart2_1", -+ "net_wo0_uart_txd_0", -+ "net_wo1_uart_txd_0", -+ "net_wo2_uart_txd_0", -+ "tops_uart1_0", -+ "ops_uart0_1", -+ "ops_uart1_1", -+ "uart0", -+ "tops_uart0_2", -+ "uart1_1", -+ "uart2_3", -+ "uart1_2", -+ "uart1_2_lite", -+ "tops_uart1_2", -+ "net_wo0_uart_txd_1", -+ "net_wo1_uart_txd_1", -+ "net_wo2_uart_txd_1", -+}; -+static const char * const mt7988_udi_groups[] = { -+ "udi", -+}; -+static const char * const mt7988_audio_groups[] = { -+ "i2s", "pcm", -+}; -+static const char * const mt7988_led_groups[] = { -+ "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", -+ "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", -+ "wf5g_led0", "wf5g_led1", -+}; -+static const char * const mt7988_usb_groups[] = { -+ "drv_vbus", -+ "drv_vbus_p1", -+}; -+ -+static const struct function_desc mt7988_functions[] = { -+ { { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) }, -+ NULL }, -+ { { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) }, -+ NULL }, -+ { { "int_usxgmii", mt7988_int_usxgmii_groups, -+ ARRAY_SIZE(mt7988_int_usxgmii_groups) }, -+ NULL }, -+ { { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) }, NULL }, -+ { { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) }, NULL }, -+ { { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) }, NULL }, -+ { { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) }, -+ NULL }, -+ { { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) }, -+ NULL }, -+ { { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) }, -+ NULL }, -+ { { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) }, -+ NULL }, -+ { { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) }, NULL }, -+ { { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) }, -+ NULL }, -+ { { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) }, -+ NULL }, -+ { { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) }, NULL }, -+ { { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) }, NULL }, -+ { { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) }, NULL }, -+}; -+ -+static const struct mtk_eint_hw mt7988_eint_hw = { -+ .port_mask = 7, -+ .ports = 7, -+ .ap_num = ARRAY_SIZE(mt7988_pins), -+ .db_cnt = 16, -+}; -+ -+static const char * const mt7988_pinctrl_register_base_names[] = { -+ "gpio", "iocfg_tr", "iocfg_br", -+ "iocfg_rb", "iocfg_lb", "iocfg_tl", -+}; -+ -+static const struct mtk_pin_soc mt7988_data = { -+ .reg_cal = mt7988_reg_cals, -+ .pins = mt7988_pins, -+ .npins = ARRAY_SIZE(mt7988_pins), -+ .grps = mt7988_groups, -+ .ngrps = ARRAY_SIZE(mt7988_groups), -+ .funcs = mt7988_functions, -+ .nfuncs = ARRAY_SIZE(mt7988_functions), -+ .eint_hw = &mt7988_eint_hw, -+ .gpio_m = 0, -+ .ies_present = false, -+ .base_names = mt7988_pinctrl_register_base_names, -+ .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), -+ .bias_disable_set = mtk_pinconf_bias_disable_set, -+ .bias_disable_get = mtk_pinconf_bias_disable_get, -+ .bias_set = mtk_pinconf_bias_set, -+ .bias_get = mtk_pinconf_bias_get, -+ .pull_type = mt7988_pull_type, -+ .bias_set_combo = mtk_pinconf_bias_set_combo, -+ .bias_get_combo = mtk_pinconf_bias_get_combo, -+ .drive_set = mtk_pinconf_drive_set_rev1, -+ .drive_get = mtk_pinconf_drive_get_rev1, -+ .adv_pull_get = mtk_pinconf_adv_pull_get, -+ .adv_pull_set = mtk_pinconf_adv_pull_set, -+}; -+ -+static const struct of_device_id mt7988_pinctrl_of_match[] = { -+ { .compatible = "mediatek,mt7988-pinctrl" }, -+ {} -+}; -+ -+static int mt7988_pinctrl_probe(struct platform_device *pdev) -+{ -+ return mtk_moore_pinctrl_probe(pdev, &mt7988_data); -+} -+ -+static struct platform_driver mt7988_pinctrl_driver = { -+ .driver = { -+ .name = "mt7988-pinctrl", -+ .of_match_table = mt7988_pinctrl_of_match, -+ }, -+ .probe = mt7988_pinctrl_probe, -+}; -+ -+static int __init mt7988_pinctrl_init(void) -+{ -+ return platform_driver_register(&mt7988_pinctrl_driver); -+} -+arch_initcall(mt7988_pinctrl_init); diff --git a/target/linux/mediatek/patches-6.18/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch b/target/linux/mediatek/patches-6.18/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch deleted file mode 100644 index e615e39345..0000000000 --- a/target/linux/mediatek/patches-6.18/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 0e18b099672160698dfbd7c3c82e03e011c907e6 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Wed, 8 Jan 2025 22:52:44 +0100 -Subject: [PATCH] pinctrl: mediatek: Drop mtk_pinconf_bias_set_pd() - -This function is unused and causing compile errors, delete it. - -Reported-by: Stephen Rothwell -Link: https://lore.kernel.org/linux-next/20250106164630.4447cd0d@canb.auug.org.au/ -Signed-off-by: Linus Walleij ---- - .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 18 ------------------ - 1 file changed, 18 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -@@ -599,24 +599,6 @@ static int mtk_pinconf_bias_set_pu_pd(st - return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); - } - --static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw, -- const struct mtk_pin_desc *desc, -- u32 pullup, u32 arg) --{ -- int err, pd; -- -- if (arg != MTK_DISABLE && arg != MTK_ENABLE) -- return -EINVAL; -- -- if (arg == MTK_DISABLE || pullup) -- pd = 0; -- else if (!pullup) -- pd = 1; -- -- return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); -- --} -- - static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, - u32 pullup, u32 arg) diff --git a/target/linux/mediatek/patches-6.18/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch b/target/linux/mediatek/patches-6.18/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch deleted file mode 100644 index 2c0afbe01c..0000000000 --- a/target/linux/mediatek/patches-6.18/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 52e2ca3be4b6d451fef0a2cd337157dd021b830f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 5 Jun 2024 10:54:33 +0200 -Subject: [PATCH 01/32] arm64: dts: mediatek: mt7988: add UART controllers -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -MT7988 has three on-SoC UART controllers that support M16C450 and -M16550A modes. - -Signed-off-by: Rafał Miłecki -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20240605085433.26513-2-zajec5@gmail.com -Signed-off-by: Matthias Brugger -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 35 ++++++++++++++++++++++- - 1 file changed, 34 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -86,7 +86,7 @@ - #clock-cells = <1>; - }; - -- clock-controller@1001b000 { -+ topckgen: clock-controller@1001b000 { - compatible = "mediatek,mt7988-topckgen", "syscon"; - reg = <0 0x1001b000 0 0x1000>; - #clock-cells = <1>; -@@ -124,6 +124,39 @@ - status = "disabled"; - }; - -+ serial@11000000 { -+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; -+ reg = <0 0x11000000 0 0x100>; -+ interrupts = ; -+ interrupt-names = "uart", "wakeup"; -+ clocks = <&topckgen CLK_TOP_UART_SEL>, -+ <&infracfg CLK_INFRA_52M_UART0_CK>; -+ clock-names = "baud", "bus"; -+ status = "disabled"; -+ }; -+ -+ serial@11000100 { -+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; -+ reg = <0 0x11000100 0 0x100>; -+ interrupts = ; -+ interrupt-names = "uart", "wakeup"; -+ clocks = <&topckgen CLK_TOP_UART_SEL>, -+ <&infracfg CLK_INFRA_52M_UART1_CK>; -+ clock-names = "baud", "bus"; -+ status = "disabled"; -+ }; -+ -+ serial@11000200 { -+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; -+ reg = <0 0x11000200 0 0x100>; -+ interrupts = ; -+ interrupt-names = "uart", "wakeup"; -+ clocks = <&topckgen CLK_TOP_UART_SEL>, -+ <&infracfg CLK_INFRA_52M_UART2_CK>; -+ clock-names = "baud", "bus"; -+ status = "disabled"; -+ }; -+ - i2c@11003000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11003000 0 0x1000>, diff --git a/target/linux/mediatek/patches-6.18/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch b/target/linux/mediatek/patches-6.18/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch deleted file mode 100644 index bf4e7a3b63..0000000000 --- a/target/linux/mediatek/patches-6.18/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 390529e00d5586eb6d7f4c33c23dee7f43ac14e7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 13 Jun 2024 21:59:33 +0200 -Subject: [PATCH 02/32] arm64: dts: mediatek: mt7988: add efuse block -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -MT7988 (AKA MediaTek Filogic 880) uses efuse for storing calibration -data. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20240613195933.31089-2-zajec5@gmail.com -Signed-off-by: Matthias Brugger -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -234,6 +234,13 @@ - #clock-cells = <1>; - }; - -+ efuse@11f50000 { -+ compatible = "mediatek,mt7988-efuse", "mediatek,efuse"; -+ reg = <0 0x11f50000 0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ }; -+ - clock-controller@15000000 { - compatible = "mediatek,mt7988-ethsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.18/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch b/target/linux/mediatek/patches-6.18/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch deleted file mode 100644 index 90ec3186eb..0000000000 --- a/target/linux/mediatek/patches-6.18/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch +++ /dev/null @@ -1,85 +0,0 @@ -From a01cc71a8c55e7fc12cb37109953ad9c58a12d4f Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 09:54:29 +0100 -Subject: [PATCH 03/32] arm64: dts: mediatek: mt7988: Add pinctrl support - -Add mt7988a pinctrl node. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217085435.9586-5-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 54 +++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -3,6 +3,7 @@ - #include - #include - #include -+#include - - / { - compatible = "mediatek,mt7988a"; -@@ -105,6 +106,59 @@ - #clock-cells = <1>; - }; - -+ pio: pinctrl@1001f000 { -+ compatible = "mediatek,mt7988-pinctrl"; -+ reg = <0 0x1001f000 0 0x1000>, -+ <0 0x11c10000 0 0x1000>, -+ <0 0x11d00000 0 0x1000>, -+ <0 0x11d20000 0 0x1000>, -+ <0 0x11e00000 0 0x1000>, -+ <0 0x11f00000 0 0x1000>, -+ <0 0x1000b000 0 0x1000>; -+ reg-names = "gpio", "iocfg_tr", -+ "iocfg_br", "iocfg_rb", -+ "iocfg_lb", "iocfg_tl", "eint"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-ranges = <&pio 0 0 84>; -+ interrupt-controller; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <2>; -+ -+ pcie0_pins: pcie0-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", -+ "pcie_wake_n0_0"; -+ }; -+ }; -+ -+ pcie1_pins: pcie1-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", -+ "pcie_wake_n1_0"; -+ }; -+ }; -+ -+ pcie2_pins: pcie2-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", -+ "pcie_wake_n2_0"; -+ }; -+ }; -+ -+ pcie3_pins: pcie3-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", -+ "pcie_wake_n3_0"; -+ }; -+ }; -+ }; -+ - pwm@10048000 { - compatible = "mediatek,mt7988-pwm"; - reg = <0 0x10048000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.18/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch b/target/linux/mediatek/patches-6.18/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch deleted file mode 100644 index 043530c994..0000000000 --- a/target/linux/mediatek/patches-6.18/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch +++ /dev/null @@ -1,37 +0,0 @@ -From b3bb498ff23f5bcaa95614e0f8c9176690af8acb Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:15 +0100 -Subject: [PATCH 04/32] arm64: dts: mediatek: mt7988: Add reserved memory - -Add memory range handled by ATF to not be touched by linux kernel. -ATF is SoC specific and not board-specific so add it to mt7988.dtsi. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-2-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -62,6 +62,18 @@ - method = "smc"; - }; - -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ -+ secmon@43000000 { -+ reg = <0 0x43000000 0 0x50000>; -+ no-map; -+ }; -+ }; -+ - soc { - compatible = "simple-bus"; - ranges; diff --git a/target/linux/mediatek/patches-6.18/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch b/target/linux/mediatek/patches-6.18/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch deleted file mode 100644 index a52f443d83..0000000000 --- a/target/linux/mediatek/patches-6.18/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch +++ /dev/null @@ -1,52 +0,0 @@ -From de6ba1a3ef621762394e841888de3e0ed127e20a Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:16 +0100 -Subject: [PATCH 05/32] arm64: dts: mediatek: mt7988: Add mmc support - -Add devicetree node for MMC controller. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-3-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 21 ++++++++++++++++++++- - 1 file changed, 20 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -112,7 +112,7 @@ - #reset-cells = <1>; - }; - -- clock-controller@1001e000 { -+ apmixedsys: clock-controller@1001e000 { - compatible = "mediatek,mt7988-apmixedsys"; - reg = <0 0x1001e000 0 0x1000>; - #clock-cells = <1>; -@@ -293,6 +293,25 @@ - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; - }; - -+ mmc0: mmc@11230000 { -+ compatible = "mediatek,mt7988-mmc"; -+ reg = <0 0x11230000 0 0x1000>, -+ <0 0x11D60000 0 0x1000>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_MSDC400>, -+ <&infracfg CLK_INFRA_MSDC2_HCK>, -+ <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, -+ <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; -+ assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, -+ <&topckgen CLK_TOP_EMMC_400M_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, -+ <&apmixedsys CLK_APMIXED_MSDCPLL>; -+ clock-names = "source", "hclk", "axi_cg", "ahb_cg"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - clock-controller@11f40000 { - compatible = "mediatek,mt7988-xfi-pll"; - reg = <0 0x11f40000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.18/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch b/target/linux/mediatek/patches-6.18/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch deleted file mode 100644 index b878d20f2e..0000000000 --- a/target/linux/mediatek/patches-6.18/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch +++ /dev/null @@ -1,62 +0,0 @@ -From f07e0e093c42736df56f4830179c19f48f8b0725 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:17 +0100 -Subject: [PATCH 06/32] arm64: dts: mediatek: mt7988: Add lvts node - -Add Low Voltage Thermal Sensor (LVTS) node for mt7988 SoC. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-4-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -4,6 +4,7 @@ - #include - #include - #include -+#include - - / { - compatible = "mediatek,mt7988a"; -@@ -97,6 +98,7 @@ - compatible = "mediatek,mt7988-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; -+ #reset-cells = <1>; - }; - - topckgen: clock-controller@1001b000 { -@@ -265,6 +267,17 @@ - status = "disabled"; - }; - -+ lvts: lvts@1100a000 { -+ compatible = "mediatek,mt7988-lvts-ap"; -+ #thermal-sensor-cells = <1>; -+ reg = <0 0x1100a000 0 0x1000>; -+ clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; -+ interrupts = ; -+ resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>; -+ nvmem-cells = <&lvts_calibration>; -+ nvmem-cell-names = "lvts-calib-data-1"; -+ }; -+ - usb@11190000 { - compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; - reg = <0 0x11190000 0 0x2e00>, -@@ -324,6 +337,10 @@ - reg = <0 0x11f50000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; -+ -+ lvts_calibration: calib@918 { -+ reg = <0x918 0x28>; -+ }; - }; - - clock-controller@15000000 { diff --git a/target/linux/mediatek/patches-6.18/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch b/target/linux/mediatek/patches-6.18/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch deleted file mode 100644 index e0ff078164..0000000000 --- a/target/linux/mediatek/patches-6.18/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 122ed9fc41b948d79ac357f95f5438a4bd6786b8 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:18 +0100 -Subject: [PATCH 07/32] arm64: dts: mediatek: mt7988: Add thermal-zone - -Add basic thermal-zone node. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-5-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -358,6 +358,21 @@ - }; - }; - -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <1000>; -+ thermal-sensors = <&lvts 0>; -+ trips { -+ cpu_trip_crit: crit { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; diff --git a/target/linux/mediatek/patches-6.18/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch b/target/linux/mediatek/patches-6.18/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch deleted file mode 100644 index 551dca3c09..0000000000 --- a/target/linux/mediatek/patches-6.18/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 7fa08d530548ed57752703e9f011eeeb809ef9b0 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:20 +0100 -Subject: [PATCH 08/32] arm64: dts: mediatek: mt7988: Add mcu-sys node for cpu - -In preparation for adding support for CPU DVFS and clock tables for it, -add the MCUSYS clock controller node. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-7-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -192,6 +192,12 @@ - status = "disabled"; - }; - -+ mcusys: mcusys@100e0000 { -+ compatible = "mediatek,mt7988-mcusys", "syscon"; -+ reg = <0 0x100e0000 0 0x1000>; -+ #clock-cells = <1>; -+ }; -+ - serial@11000000 { - compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; - reg = <0 0x11000000 0 0x100>; diff --git a/target/linux/mediatek/patches-6.18/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch b/target/linux/mediatek/patches-6.18/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch deleted file mode 100644 index e2bec750e4..0000000000 --- a/target/linux/mediatek/patches-6.18/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch +++ /dev/null @@ -1,84 +0,0 @@ -From b10331c8faa1208c61fb98d9b65da2828e239113 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:21 +0100 -Subject: [PATCH 09/32] arm64: dts: mediatek: mt7988: Add CPU OPP table for - clock scaling - -Add operating points defining frequency/voltages of cpu cores. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-8-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 38 +++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -21,6 +21,10 @@ - reg = <0x0>; - device_type = "cpu"; - enable-method = "psci"; -+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, -+ <&topckgen CLK_TOP_XTAL>; -+ clock-names = "cpu", "intermediate"; -+ operating-points-v2 = <&cluster0_opp>; - }; - - cpu@1 { -@@ -28,6 +32,10 @@ - reg = <0x1>; - device_type = "cpu"; - enable-method = "psci"; -+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, -+ <&topckgen CLK_TOP_XTAL>; -+ clock-names = "cpu", "intermediate"; -+ operating-points-v2 = <&cluster0_opp>; - }; - - cpu@2 { -@@ -35,6 +43,10 @@ - reg = <0x2>; - device_type = "cpu"; - enable-method = "psci"; -+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, -+ <&topckgen CLK_TOP_XTAL>; -+ clock-names = "cpu", "intermediate"; -+ operating-points-v2 = <&cluster0_opp>; - }; - - cpu@3 { -@@ -42,6 +54,32 @@ - reg = <0x3>; - device_type = "cpu"; - enable-method = "psci"; -+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, -+ <&topckgen CLK_TOP_XTAL>; -+ clock-names = "cpu", "intermediate"; -+ operating-points-v2 = <&cluster0_opp>; -+ }; -+ -+ cluster0_opp: opp-table-0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-1100000000 { -+ opp-hz = /bits/ 64 <1100000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-1500000000 { -+ opp-hz = /bits/ 64 <1500000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <900000>; -+ }; - }; - }; - diff --git a/target/linux/mediatek/patches-6.18/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch b/target/linux/mediatek/patches-6.18/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch deleted file mode 100644 index f65d23bc0a..0000000000 --- a/target/linux/mediatek/patches-6.18/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 39bb12c26f556046e55f3638e2e4184bfbfd0564 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:22 +0100 -Subject: [PATCH 10/32] arm64: dts: mediatek: mt7988: Disable usb controllers - by default - -The controllers should be enabled at board level if used. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-9-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -334,6 +334,7 @@ - <&infracfg CLK_INFRA_133M_USB_HCK>, - <&infracfg CLK_INFRA_USB_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; -+ status = "disabled"; - }; - - usb@11200000 { -@@ -348,6 +349,7 @@ - <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, - <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; -+ status = "disabled"; - }; - - mmc0: mmc@11230000 { diff --git a/target/linux/mediatek/patches-6.18/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch b/target/linux/mediatek/patches-6.18/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch deleted file mode 100644 index c53db06c39..0000000000 --- a/target/linux/mediatek/patches-6.18/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 46d056b6c2376d3ef866f9ab5212879c97588892 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:23 +0100 -Subject: [PATCH 11/32] arm64: dts: mediatek: mt7988: Add t-phy for ssusb1 - -USB controller needs phys for working properly. -On mt7988 ssusb0 uses a xs-phy, ssusb uses t-phy. -For now add the t-phy for ssusb1. We can reuse the mt7986 compatible -here. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-10-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 25 +++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -349,6 +349,8 @@ - <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, - <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; -+ phys = <&tphyu2port0 PHY_TYPE_USB2>, -+ <&tphyu3port0 PHY_TYPE_USB3>; - status = "disabled"; - }; - -@@ -371,6 +373,29 @@ - status = "disabled"; - }; - -+ t-phy@11c50000 { -+ compatible = "mediatek,mt7986-tphy", -+ "mediatek,generic-tphy-v2"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ tphyu2port0: usb-phy@11c50000 { -+ reg = <0 0x11c50000 0 0x700>; -+ clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ }; -+ -+ tphyu3port0: usb-phy@11c50700 { -+ reg = <0 0x11c50700 0 0x900>; -+ clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ }; -+ }; -+ - clock-controller@11f40000 { - compatible = "mediatek,mt7988-xfi-pll"; - reg = <0 0x11f40000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.18/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch b/target/linux/mediatek/patches-6.18/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch deleted file mode 100644 index fe27e5223c..0000000000 --- a/target/linux/mediatek/patches-6.18/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch +++ /dev/null @@ -1,176 +0,0 @@ -From aac2eb27ee500ca2828fe0fd1895ec6f9ef83787 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:24 +0100 -Subject: [PATCH 12/32] arm64: dts: mediatek: mt7988: Add pcie nodes - -Add pcie controllers for mt7988. Reuse mt7986 compatible. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-11-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 152 ++++++++++++++++++++++ - 1 file changed, 152 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -373,6 +373,158 @@ - status = "disabled"; - }; - -+ pcie@11280000 { -+ compatible = "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0 0x11280000 0 0x2000>; -+ reg-names = "pcie-mac"; -+ linux,pci-domain = <3>; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0x00 0x20000000 0x00 -+ 0x20000000 0x00 0x00200000>, -+ <0x82000000 0x00 0x20200000 0x00 -+ 0x20200000 0x00 0x07e00000>; -+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, -+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, -+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, -+ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", -+ "top_133m"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_pins>; -+ status = "disabled"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc2 0>, -+ <0 0 0 2 &pcie_intc2 1>, -+ <0 0 0 3 &pcie_intc2 2>, -+ <0 0 0 4 &pcie_intc2 3>; -+ pcie_intc2: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ pcie@11290000 { -+ compatible = "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0 0x11290000 0 0x2000>; -+ reg-names = "pcie-mac"; -+ linux,pci-domain = <2>; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0x00 0x28000000 0x00 -+ 0x28000000 0x00 0x00200000>, -+ <0x82000000 0x00 0x28200000 0x00 -+ 0x28200000 0x00 0x07e00000>; -+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, -+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, -+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, -+ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", -+ "top_133m"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie3_pins>; -+ status = "disabled"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc3 0>, -+ <0 0 0 2 &pcie_intc3 1>, -+ <0 0 0 3 &pcie_intc3 2>, -+ <0 0 0 4 &pcie_intc3 3>; -+ pcie_intc3: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ pcie@11300000 { -+ compatible = "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0 0x11300000 0 0x2000>; -+ reg-names = "pcie-mac"; -+ linux,pci-domain = <0>; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0x00 0x30000000 0x00 -+ 0x30000000 0x00 0x00200000>, -+ <0x82000000 0x00 0x30200000 0x00 -+ 0x30200000 0x00 0x07e00000>; -+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, -+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, -+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, -+ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", -+ "top_133m"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie0_pins>; -+ status = "disabled"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc0 0>, -+ <0 0 0 2 &pcie_intc0 1>, -+ <0 0 0 3 &pcie_intc0 2>, -+ <0 0 0 4 &pcie_intc0 3>; -+ pcie_intc0: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ pcie@11310000 { -+ compatible = "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0 0x11310000 0 0x2000>; -+ reg-names = "pcie-mac"; -+ linux,pci-domain = <1>; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0x00 0x38000000 0x00 -+ 0x38000000 0x00 0x00200000>, -+ <0x82000000 0x00 0x38200000 0x00 -+ 0x38200000 0x00 0x07e00000>; -+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, -+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, -+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, -+ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", -+ "top_133m"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "disabled"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc1 0>, -+ <0 0 0 2 &pcie_intc1 1>, -+ <0 0 0 3 &pcie_intc1 2>, -+ <0 0 0 4 &pcie_intc1 3>; -+ pcie_intc1: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ - t-phy@11c50000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; diff --git a/target/linux/mediatek/patches-6.18/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch b/target/linux/mediatek/patches-6.18/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch deleted file mode 100644 index 6f0080e6ec..0000000000 --- a/target/linux/mediatek/patches-6.18/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch +++ /dev/null @@ -1,211 +0,0 @@ -From 6b116c43782a153bcde18bd54d3220d81b476859 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 09:54:30 +0100 -Subject: [PATCH 13/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add pinctrl - subnodes for bpi-r4 - -Add board specific pinctrl configurations on Bananapi R4. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217085435.9586-6-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 189 ++++++++++++++++++ - 1 file changed, 189 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -9,3 +9,192 @@ - model = "Banana Pi BPI-R4"; - chassis-type = "embedded"; - }; -+ -+&pio { -+ mdio0_pins: mdio0-pins { -+ mux { -+ function = "eth"; -+ groups = "mdc_mdio0"; -+ }; -+ -+ conf { -+ pins = "SMI_0_MDC", "SMI_0_MDIO"; -+ drive-strength = <8>; -+ }; -+ }; -+ -+ i2c0_pins: i2c0-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c0_1"; -+ }; -+ }; -+ -+ i2c1_pins: i2c1-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c1_0"; -+ }; -+ }; -+ -+ i2c1_sfp_pins: i2c1-sfp-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c1_sfp"; -+ }; -+ }; -+ -+ i2c2_0_pins: i2c2-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c2_0"; -+ }; -+ }; -+ -+ i2c2_1_pins: i2c2-g1-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c2_1"; -+ }; -+ }; -+ -+ gbe0_led0_pins: gbe0-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe0_led0"; -+ }; -+ }; -+ -+ gbe1_led0_pins: gbe1-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe1_led0"; -+ }; -+ }; -+ -+ gbe2_led0_pins: gbe2-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe2_led0"; -+ }; -+ }; -+ -+ gbe3_led0_pins: gbe3-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe3_led0"; -+ }; -+ }; -+ -+ gbe0_led1_pins: gbe0-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe0_led1"; -+ }; -+ }; -+ -+ gbe1_led1_pins: gbe1-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe1_led1"; -+ }; -+ }; -+ -+ gbe2_led1_pins: gbe2-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe2_led1"; -+ }; -+ }; -+ -+ gbe3_led1_pins: gbe3-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe3_led1"; -+ }; -+ }; -+ -+ i2p5gbe_led0_pins: 2p5gbe-led0-pins { -+ mux { -+ function = "led"; -+ groups = "2p5gbe_led0"; -+ }; -+ }; -+ -+ i2p5gbe_led1_pins: 2p5gbe-led1-pins { -+ mux { -+ function = "led"; -+ groups = "2p5gbe_led1"; -+ }; -+ }; -+ -+ mmc0_pins_emmc_45: mmc0-emmc-45-pins { -+ mux { -+ function = "flash"; -+ groups = "emmc_45"; -+ }; -+ }; -+ -+ mmc0_pins_emmc_51: mmc0-emmc-51-pins { -+ mux { -+ function = "flash"; -+ groups = "emmc_51"; -+ }; -+ }; -+ -+ mmc0_pins_sdcard: mmc0-sdcard-pins { -+ mux { -+ function = "flash"; -+ groups = "sdcard"; -+ }; -+ }; -+ -+ uart0_pins: uart0-pins { -+ mux { -+ function = "uart"; -+ groups = "uart0"; -+ }; -+ }; -+ -+ snfi_pins: snfi-pins { -+ mux { -+ function = "flash"; -+ groups = "snfi"; -+ }; -+ }; -+ -+ spi0_pins: spi0-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0"; -+ }; -+ }; -+ -+ spi0_flash_pins: spi0-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spi1_pins: spi1-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1"; -+ }; -+ }; -+ -+ spi2_pins: spi2-pins { -+ mux { -+ function = "spi"; -+ groups = "spi2"; -+ }; -+ }; -+ -+ spi2_flash_pins: spi2-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi2", "spi2_wp_hold"; -+ }; -+ }; -+}; diff --git a/target/linux/mediatek/patches-6.18/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch b/target/linux/mediatek/patches-6.18/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch deleted file mode 100644 index 2ce47ed12a..0000000000 --- a/target/linux/mediatek/patches-6.18/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 6b6f2f1ee88b8b5763f4112babbc9fc45a94999a Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:25 +0100 -Subject: [PATCH 14/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable watchdog - -Enable the watchdog on Bananapi R4 board. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-12-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -198,3 +198,7 @@ - }; - }; - }; -+ -+&watchdog { -+ status = "okay"; -+}; diff --git a/target/linux/mediatek/patches-6.18/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch b/target/linux/mediatek/patches-6.18/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch deleted file mode 100644 index fb383d041b..0000000000 --- a/target/linux/mediatek/patches-6.18/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 72b0a6f181c5ca417405e594c80d724baee54813 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:26 +0100 -Subject: [PATCH 15/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add fixed - regulators for 1v8 and 3v3 - -Add regulator nodes used for mmc to Bananapi R4 board. -This board has 1 MMC controller used for SDMMC and eMMC where only one can -be used at one time, selected by hardware switches. SD uses 3v3 for both -supplies and emmc uses both regulators. -So defining both regulators in board dts and referencing them in the dt -overlay. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-13-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -8,6 +8,24 @@ - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; - model = "Banana Pi BPI-R4"; - chassis-type = "embedded"; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-1.8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; - }; - - &pio { diff --git a/target/linux/mediatek/patches-6.18/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch b/target/linux/mediatek/patches-6.18/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch deleted file mode 100644 index 3273e7444c..0000000000 --- a/target/linux/mediatek/patches-6.18/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 67511ea667d3c4da827588fd460772562d7b054e Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:28 +0100 -Subject: [PATCH 16/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add thermal - configuration - -Add additional thermal trips to Bananapi R4 board. -SoC only contains the critical trip. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-15-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 28 +++++++++++++++++++ - 1 file changed, 28 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -28,6 +28,34 @@ - }; - }; - -+&cpu_thermal { -+ trips { -+ cpu_trip_hot: hot { -+ temperature = <120000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ -+ cpu_trip_active_high: active-high { -+ temperature = <115000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_active_med: active-med { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_active_low: active-low { -+ temperature = <40000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+}; -+ - &pio { - mdio0_pins: mdio0-pins { - mux { diff --git a/target/linux/mediatek/patches-6.18/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch b/target/linux/mediatek/patches-6.18/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch deleted file mode 100644 index c1d872d1db..0000000000 --- a/target/linux/mediatek/patches-6.18/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch +++ /dev/null @@ -1,41 +0,0 @@ -From a9df5ed2333b01546b4f906e2f6fd21dd5b146aa Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:29 +0100 -Subject: [PATCH 17/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable serial0 - debug uart - -Enable the debug uart on Bananapi R4 board. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-16-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -245,6 +245,10 @@ - }; - }; - -+&serial0 { -+ status = "okay"; -+}; -+ - &watchdog { - status = "okay"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -236,7 +236,7 @@ - #clock-cells = <1>; - }; - -- serial@11000000 { -+ serial0: serial@11000000 { - compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; - reg = <0 0x11000000 0 0x100>; - interrupts = ; diff --git a/target/linux/mediatek/patches-6.18/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch b/target/linux/mediatek/patches-6.18/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch deleted file mode 100644 index d75b3e57ad..0000000000 --- a/target/linux/mediatek/patches-6.18/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 3dfb0dcb194e3f32ed931747131be08bfc429522 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:30 +0100 -Subject: [PATCH 18/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add default UART - stdout - -Add chosen node on Bananapi R4 board with stdout and default bootargs. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-17-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -9,6 +9,10 @@ - model = "Banana Pi BPI-R4"; - chassis-type = "embedded"; - -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; diff --git a/target/linux/mediatek/patches-6.18/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch b/target/linux/mediatek/patches-6.18/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch deleted file mode 100644 index 4f48edd412..0000000000 --- a/target/linux/mediatek/patches-6.18/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 90d4eb65db14a3f2e776d2a8b1dc832e70198328 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:31 +0100 -Subject: [PATCH 19/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable I2C - controllers - -Enable the I2C0, I2C2 controllers found on the BananaPi R4 board. -Both controllers are not accessible from user and having fixed spare -devices. I2C0 have a pmic connected, I2C2 is used with I2C-multiplexer -for e.g. SFP cages. -The missing I2C1 is connected to GPIO header which can have either GPIO -mode or I2C mode. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-18-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 12 ++++++++++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 +++--- - 2 files changed, 15 insertions(+), 3 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -60,6 +60,18 @@ - }; - }; - -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ status = "okay"; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_1_pins>; -+ status = "okay"; -+}; -+ - &pio { - mdio0_pins: mdio0-pins { - mux { ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -269,7 +269,7 @@ - status = "disabled"; - }; - -- i2c@11003000 { -+ i2c0: i2c@11003000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11003000 0 0x1000>, - <0 0x10217080 0 0x80>; -@@ -283,7 +283,7 @@ - status = "disabled"; - }; - -- i2c@11004000 { -+ i2c1: i2c@11004000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11004000 0 0x1000>, - <0 0x10217100 0 0x80>; -@@ -297,7 +297,7 @@ - status = "disabled"; - }; - -- i2c@11005000 { -+ i2c2: i2c@11005000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11005000 0 0x1000>, - <0 0x10217180 0 0x80>; diff --git a/target/linux/mediatek/patches-6.18/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch b/target/linux/mediatek/patches-6.18/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch deleted file mode 100644 index 117479b789..0000000000 --- a/target/linux/mediatek/patches-6.18/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch +++ /dev/null @@ -1,74 +0,0 @@ -From dde7d741329616025e4cfa350eb3935b495ae140 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:32 +0100 -Subject: [PATCH 20/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add PCA9545 I2C - Mux - -Bananapi R4 uses an i2c multiplexer for SFP slots, rtc and eeprom. -Add its node to the right i2c controller. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-19-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 41 +++++++++++++++++++ - 1 file changed, 41 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -2,6 +2,8 @@ - - /dts-v1/; - -+#include -+ - #include "mt7988a.dtsi" - - / { -@@ -70,6 +72,45 @@ - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_1_pins>; - status = "okay"; -+ -+ pca9545: i2c-mux@70 { -+ compatible = "nxp,pca9545"; -+ reg = <0x70>; -+ reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ -+ pcf8563: rtc@51 { -+ compatible = "nxp,pcf8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ }; -+ -+ eeprom@57 { -+ compatible = "atmel,24c02"; -+ reg = <0x57>; -+ size = <256>; -+ }; -+ -+ }; -+ -+ i2c_sfp1: i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ }; -+ -+ i2c_sfp2: i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ }; -+ }; - }; - - &pio { diff --git a/target/linux/mediatek/patches-6.18/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch b/target/linux/mediatek/patches-6.18/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch deleted file mode 100644 index e16b30ef30..0000000000 --- a/target/linux/mediatek/patches-6.18/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch +++ /dev/null @@ -1,41 +0,0 @@ -From dfe00be85da20d9823d39775c92139c569a7960d Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:33 +0100 -Subject: [PATCH 21/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable t-phy for - ssusb1 - -Bananapi R4 uses t-phy for usb. Enable its node at board level. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-20-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -306,6 +306,10 @@ - status = "okay"; - }; - -+&tphy { -+ status = "okay"; -+}; -+ - &watchdog { - status = "okay"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -525,7 +525,7 @@ - }; - }; - -- t-phy@11c50000 { -+ tphy: t-phy@11c50000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; - #address-cells = <2>; diff --git a/target/linux/mediatek/patches-6.18/041-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch b/target/linux/mediatek/patches-6.18/041-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch deleted file mode 100644 index d1892c6cc1..0000000000 --- a/target/linux/mediatek/patches-6.18/041-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 2b03ef47273db52e0c0010e963c3626e6842204f Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:34 +0100 -Subject: [PATCH 22/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable ssusb1 on - bpi-r4 - -Enable usb on Bananapi R4 board. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-21-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -306,6 +306,10 @@ - status = "okay"; - }; - -+&ssusb1 { -+ status = "okay"; -+}; -+ - &tphy { - status = "okay"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -337,7 +337,7 @@ - status = "disabled"; - }; - -- usb@11200000 { -+ ssusb1: usb@11200000 { - compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; diff --git a/target/linux/mediatek/patches-6.18/042-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pwm.patch b/target/linux/mediatek/patches-6.18/042-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pwm.patch deleted file mode 100644 index 4e24607e5d..0000000000 --- a/target/linux/mediatek/patches-6.18/042-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pwm.patch +++ /dev/null @@ -1,40 +0,0 @@ -From b074487a4180aeee440b61fc00a865fc2a4bd32a Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:35 +0100 -Subject: [PATCH 23/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable pwm - -Enable pwm on Bananapi R4 board. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-22-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -302,6 +302,10 @@ - }; - }; - -+&pwm { -+ status = "okay"; -+}; -+ - &serial0 { - status = "okay"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -211,7 +211,7 @@ - }; - }; - -- pwm@10048000 { -+ pwm: pwm@10048000 { - compatible = "mediatek,mt7988-pwm"; - reg = <0 0x10048000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, diff --git a/target/linux/mediatek/patches-6.18/043-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pcie.patch b/target/linux/mediatek/patches-6.18/043-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pcie.patch deleted file mode 100644 index a25d235630..0000000000 --- a/target/linux/mediatek/patches-6.18/043-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pcie.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 72bc814e8609e8be59dff8bc6e0e185b5005ace8 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:36 +0100 -Subject: [PATCH 24/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable pcie - -Enable the pci controllers on BPI-R4. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-23-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 20 +++++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 8 ++++---- - 2 files changed, 24 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -113,6 +113,26 @@ - }; - }; - -+/* mPCIe SIM2 */ -+&pcie0 { -+ status = "okay"; -+}; -+ -+/* mPCIe SIM3 */ -+&pcie1 { -+ status = "okay"; -+}; -+ -+/* M.2 key-B SIM1 */ -+&pcie2 { -+ status = "okay"; -+}; -+ -+/* M.2 key-M SSD */ -+&pcie3 { -+ status = "okay"; -+}; -+ - &pio { - mdio0_pins: mdio0-pins { - mux { ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -373,7 +373,7 @@ - status = "disabled"; - }; - -- pcie@11280000 { -+ pcie2: pcie@11280000 { - compatible = "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; -@@ -411,7 +411,7 @@ - }; - }; - -- pcie@11290000 { -+ pcie3: pcie@11290000 { - compatible = "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; -@@ -449,7 +449,7 @@ - }; - }; - -- pcie@11300000 { -+ pcie0: pcie@11300000 { - compatible = "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; -@@ -487,7 +487,7 @@ - }; - }; - -- pcie@11310000 { -+ pcie1: pcie@11310000 { - compatible = "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; diff --git a/target/linux/mediatek/patches-6.18/044-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch b/target/linux/mediatek/patches-6.18/044-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch deleted file mode 100644 index 26a5990b60..0000000000 --- a/target/linux/mediatek/patches-6.18/044-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 84087157052afba2f61cea7c99ccabfe9681b643 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 20 Dec 2024 17:38:35 +0100 -Subject: [PATCH 25/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add MediaTek - MT6682A/RT5190A PMIC - -Bananapi R4 Board contains a MT6682A pmic which is compatible to rt5190a. -Add its node to the i2 controller. - -The BananaPi R4 board has a MediaTek MT6682A PMIC, a rebrand of the -Richtek RT5190A chip, connected to the I2C0 bus. - -Add the relevant node and, while at it, also configure the regulators -from this PMIC that are used on this board. - -Only Buck2/Buck3 voltage can be controlled by software. - -BUCK4 input is 5V from BUCK1 output, and the resistor (mapped to RP30/RP31 -on BPI-R4) configures BUCK4 output to 1.8V. -LDO input is 3.3V from 3.3VD, and the resistor (mapped to RP38/RP40 on -BPI-R4) configures LDO output to 1.8V. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241220163838.114786-2-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 50 +++++++++++++++++++ - 1 file changed, 50 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -3,6 +3,7 @@ - /dts-v1/; - - #include -+#include - - #include "mt7988a.dtsi" - -@@ -66,6 +67,55 @@ - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; -+ -+ rt5190a_64: rt5190a@64 { -+ compatible = "richtek,rt5190a"; -+ reg = <0x64>; -+ vin2-supply = <&rt5190_buck1>; -+ vin3-supply = <&rt5190_buck1>; -+ vin4-supply = <&rt5190_buck1>; -+ -+ regulators { -+ rt5190_buck1: buck1 { -+ regulator-name = "rt5190a-buck1"; -+ regulator-min-microvolt = <5090000>; -+ regulator-max-microvolt = <5090000>; -+ regulator-allowed-modes = -+ , ; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ buck2 { -+ regulator-name = "vcore"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ rt5190_buck3: buck3 { -+ regulator-name = "vproc"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ }; -+ buck4 { -+ regulator-name = "rt5190a-buck4"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-allowed-modes = -+ , ; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ ldo { -+ regulator-name = "rt5190a-ldo"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; - }; - - &i2c2 { diff --git a/target/linux/mediatek/patches-6.18/045-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-proc-supply-fo.patch b/target/linux/mediatek/patches-6.18/045-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-proc-supply-fo.patch deleted file mode 100644 index c605e90e5d..0000000000 --- a/target/linux/mediatek/patches-6.18/045-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-proc-supply-fo.patch +++ /dev/null @@ -1,80 +0,0 @@ -From c0a17ddd90c2094dfe4610b0d965db8a3b987e32 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 20 Dec 2024 17:38:36 +0100 -Subject: [PATCH 26/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add proc-supply - for cpus - -Add proc-supply property to cpus on Bananapi R4 board. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241220163838.114786-3-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 16 ++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 8 ++++---- - 2 files changed, 20 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -35,6 +35,22 @@ - }; - }; - -+&cpu0 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu1 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu2 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu3 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ - &cpu_thermal { - trips { - cpu_trip_hot: hot { ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -16,7 +16,7 @@ - #address-cells = <1>; - #size-cells = <0>; - -- cpu@0 { -+ cpu0: cpu@0 { - compatible = "arm,cortex-a73"; - reg = <0x0>; - device_type = "cpu"; -@@ -27,7 +27,7 @@ - operating-points-v2 = <&cluster0_opp>; - }; - -- cpu@1 { -+ cpu1: cpu@1 { - compatible = "arm,cortex-a73"; - reg = <0x1>; - device_type = "cpu"; -@@ -38,7 +38,7 @@ - operating-points-v2 = <&cluster0_opp>; - }; - -- cpu@2 { -+ cpu2: cpu@2 { - compatible = "arm,cortex-a73"; - reg = <0x2>; - device_type = "cpu"; -@@ -49,7 +49,7 @@ - operating-points-v2 = <&cluster0_opp>; - }; - -- cpu@3 { -+ cpu3: cpu@3 { - compatible = "arm,cortex-a73"; - reg = <0x3>; - device_type = "cpu"; diff --git a/target/linux/mediatek/patches-6.18/050-v6.16-phy-mediatek-xsphy-support-type-switch-by-pericfg.patch b/target/linux/mediatek/patches-6.18/050-v6.16-phy-mediatek-xsphy-support-type-switch-by-pericfg.patch deleted file mode 100644 index a543ecbaa3..0000000000 --- a/target/linux/mediatek/patches-6.18/050-v6.16-phy-mediatek-xsphy-support-type-switch-by-pericfg.patch +++ /dev/null @@ -1,169 +0,0 @@ -From b7ae3528a588a4006ff9c9cc581efa317df1c1ed Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 22 Apr 2025 15:24:29 +0200 -Subject: [PATCH] phy: mediatek: xsphy: support type switch by pericfg - -Patch from Sam Shih found in MediaTek SDK -released under GPL. - -Get syscon and use it to set the PHY type. -Extend support to PCIe and SGMII mode in addition to USB2 and USB3. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno ---- - drivers/phy/mediatek/phy-mtk-xsphy.c | 85 +++++++++++++++++++++++++++- - 1 file changed, 84 insertions(+), 1 deletion(-) - ---- a/drivers/phy/mediatek/phy-mtk-xsphy.c -+++ b/drivers/phy/mediatek/phy-mtk-xsphy.c -@@ -11,10 +11,12 @@ - #include - #include - #include -+#include - #include - #include - #include - #include -+#include - - #include "phy-mtk-io.h" - -@@ -81,12 +83,22 @@ - #define XSP_SR_COEF_DIVISOR 1000 - #define XSP_FM_DET_CYCLE_CNT 1024 - -+/* PHY switch between pcie/usb3/sgmii */ -+#define USB_PHY_SWITCH_CTRL 0x0 -+#define RG_PHY_SW_TYPE GENMASK(3, 0) -+#define RG_PHY_SW_PCIE 0x0 -+#define RG_PHY_SW_USB3 0x1 -+#define RG_PHY_SW_SGMII 0x2 -+ - struct xsphy_instance { - struct phy *phy; - void __iomem *port_base; - struct clk *ref_clk; /* reference clock of anolog phy */ - u32 index; - u32 type; -+ struct regmap *type_sw; -+ u32 type_sw_reg; -+ u32 type_sw_index; - /* only for HQA test */ - int efuse_intr; - int efuse_tx_imp; -@@ -259,6 +271,10 @@ static void phy_parse_property(struct mt - inst->efuse_intr, inst->efuse_tx_imp, - inst->efuse_rx_imp); - break; -+ case PHY_TYPE_PCIE: -+ case PHY_TYPE_SGMII: -+ /* nothing to do */ -+ break; - default: - dev_err(xsphy->dev, "incompatible phy type\n"); - return; -@@ -305,6 +321,62 @@ static void u3_phy_props_set(struct mtk_ - RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp); - } - -+/* type switch for usb3/pcie/sgmii */ -+static int phy_type_syscon_get(struct xsphy_instance *instance, -+ struct device_node *dn) -+{ -+ struct of_phandle_args args; -+ int ret; -+ -+ /* type switch function is optional */ -+ if (!of_property_present(dn, "mediatek,syscon-type")) -+ return 0; -+ -+ ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type", -+ 2, 0, &args); -+ if (ret) -+ return ret; -+ -+ instance->type_sw_reg = args.args[0]; -+ instance->type_sw_index = args.args[1] & 0x3; /* <=3 */ -+ instance->type_sw = syscon_node_to_regmap(args.np); -+ of_node_put(args.np); -+ dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n", -+ instance->type_sw_reg, instance->type_sw_index); -+ -+ return PTR_ERR_OR_ZERO(instance->type_sw); -+} -+ -+static int phy_type_set(struct xsphy_instance *instance) -+{ -+ int type; -+ u32 offset; -+ -+ if (!instance->type_sw) -+ return 0; -+ -+ switch (instance->type) { -+ case PHY_TYPE_USB3: -+ type = RG_PHY_SW_USB3; -+ break; -+ case PHY_TYPE_PCIE: -+ type = RG_PHY_SW_PCIE; -+ break; -+ case PHY_TYPE_SGMII: -+ type = RG_PHY_SW_SGMII; -+ break; -+ case PHY_TYPE_USB2: -+ default: -+ return 0; -+ } -+ -+ offset = instance->type_sw_index * BITS_PER_BYTE; -+ regmap_update_bits(instance->type_sw, instance->type_sw_reg, -+ RG_PHY_SW_TYPE << offset, type << offset); -+ -+ return 0; -+} -+ - static int mtk_phy_init(struct phy *phy) - { - struct xsphy_instance *inst = phy_get_drvdata(phy); -@@ -325,6 +397,10 @@ static int mtk_phy_init(struct phy *phy) - case PHY_TYPE_USB3: - u3_phy_props_set(xsphy, inst); - break; -+ case PHY_TYPE_PCIE: -+ case PHY_TYPE_SGMII: -+ /* nothing to do, only used to set type */ -+ break; - default: - dev_err(xsphy->dev, "incompatible phy type\n"); - clk_disable_unprepare(inst->ref_clk); -@@ -403,12 +479,15 @@ static struct phy *mtk_phy_xlate(struct - - inst->type = args->args[0]; - if (!(inst->type == PHY_TYPE_USB2 || -- inst->type == PHY_TYPE_USB3)) { -+ inst->type == PHY_TYPE_USB3 || -+ inst->type == PHY_TYPE_PCIE || -+ inst->type == PHY_TYPE_SGMII)) { - dev_err(dev, "unsupported phy type: %d\n", inst->type); - return ERR_PTR(-EINVAL); - } - - phy_parse_property(xsphy, inst); -+ phy_type_set(inst); - - return inst->phy; - } -@@ -510,6 +589,10 @@ static int mtk_xsphy_probe(struct platfo - dev_err(dev, "failed to get ref_clk(id-%d)\n", port); - return PTR_ERR(inst->ref_clk); - } -+ -+ retval = phy_type_syscon_get(inst, child_np); -+ if (retval) -+ return retval; - } - - provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); diff --git a/target/linux/mediatek/patches-6.18/051-v6.16-hwrng-mtk-Add-struct-device-pointer-to-device-contex.patch b/target/linux/mediatek/patches-6.18/051-v6.16-hwrng-mtk-Add-struct-device-pointer-to-device-contex.patch deleted file mode 100644 index 70c771d2df..0000000000 --- a/target/linux/mediatek/patches-6.18/051-v6.16-hwrng-mtk-Add-struct-device-pointer-to-device-contex.patch +++ /dev/null @@ -1,60 +0,0 @@ -From f9c0c36eefaa8c6ee224634bf9c0b8b4ed87b43a Mon Sep 17 00:00:00 2001 -From: Sakari Ailus -Date: Thu, 10 Apr 2025 18:22:38 +0300 -Subject: [PATCH] hwrng: mtk - Add struct device pointer to device context struct - -Add a struct device pointer field to the device's context struct. This -makes using the unsigned long priv pointer in struct hwrng unnecessary, so -remove that one as well. - -Signed-off-by: Sakari Ailus -Signed-off-by: Herbert Xu ---- - drivers/char/hw_random/mtk-rng.c | 9 +++++---- - 1 file changed, 5 insertions(+), 4 deletions(-) - ---- a/drivers/char/hw_random/mtk-rng.c -+++ b/drivers/char/hw_random/mtk-rng.c -@@ -36,6 +36,7 @@ struct mtk_rng { - void __iomem *base; - struct clk *clk; - struct hwrng rng; -+ struct device *dev; - }; - - static int mtk_rng_init(struct hwrng *rng) -@@ -85,7 +86,7 @@ static int mtk_rng_read(struct hwrng *rn - struct mtk_rng *priv = to_mtk_rng(rng); - int retval = 0; - -- pm_runtime_get_sync((struct device *)priv->rng.priv); -+ pm_runtime_get_sync(priv->dev); - - while (max >= sizeof(u32)) { - if (!mtk_rng_wait_ready(rng, wait)) -@@ -97,8 +98,8 @@ static int mtk_rng_read(struct hwrng *rn - max -= sizeof(u32); - } - -- pm_runtime_mark_last_busy((struct device *)priv->rng.priv); -- pm_runtime_put_sync_autosuspend((struct device *)priv->rng.priv); -+ pm_runtime_mark_last_busy(priv->dev); -+ pm_runtime_put_sync_autosuspend(priv->dev); - - return retval || !wait ? retval : -EIO; - } -@@ -112,13 +113,13 @@ static int mtk_rng_probe(struct platform - if (!priv) - return -ENOMEM; - -+ priv->dev = &pdev->dev; - priv->rng.name = pdev->name; - #ifndef CONFIG_PM - priv->rng.init = mtk_rng_init; - priv->rng.cleanup = mtk_rng_cleanup; - #endif - priv->rng.read = mtk_rng_read; -- priv->rng.priv = (unsigned long)&pdev->dev; - priv->rng.quality = 900; - - priv->clk = devm_clk_get(&pdev->dev, "rng"); diff --git a/target/linux/mediatek/patches-6.18/060-v6.13-mmc-mtk-sd-add-support-for-mt7988.patch b/target/linux/mediatek/patches-6.18/060-v6.13-mmc-mtk-sd-add-support-for-mt7988.patch deleted file mode 100644 index 126ae5f2a3..0000000000 --- a/target/linux/mediatek/patches-6.18/060-v6.13-mmc-mtk-sd-add-support-for-mt7988.patch +++ /dev/null @@ -1,28 +0,0 @@ -From de6840095f8ed542308279c4f24fa42ba27c2dd3 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sat, 12 Oct 2024 16:38:23 +0200 -Subject: [PATCH] mmc: mtk-sd: add support for mt7988 - -Add support for mmc on MT7988 SoC. - -We can use mt7986 platform data in driver, but mt7988 needs different -clocks so for binding we need own compatible. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Message-ID: <20241012143826.7690-3-linux@fw-web.de> -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -631,6 +631,7 @@ static const struct of_device_id msdc_of - { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, - { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, - { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, -+ { .compatible = "mediatek,mt7988-mmc", .data = &mt7986_compat}, - { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, - { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, - { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, diff --git a/target/linux/mediatek/patches-6.18/062-v6.18-arm64-dts-mediatek-add-thermal-sensor-support-on-mt7.patch b/target/linux/mediatek/patches-6.18/062-v6.18-arm64-dts-mediatek-add-thermal-sensor-support-on-mt7.patch deleted file mode 100644 index 444c64dd7c..0000000000 --- a/target/linux/mediatek/patches-6.18/062-v6.18-arm64-dts-mediatek-add-thermal-sensor-support-on-mt7.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 0da6f7a0ab5322eb6d091a9c89d799adfeae078d Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Sun, 7 Sep 2025 13:15:09 +0200 -Subject: [PATCH] arm64: dts: mediatek: add thermal sensor support on mt7981 - -The temperature sensor in the MT7981 is same as in the MT7986. - -Signed-off-by: Aleksander Jan Bajkowski -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20250907111742.23195-2-olek2@wp.pl -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 31 ++++++++++++++++++++++- - 1 file changed, 30 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi -@@ -76,7 +76,7 @@ - #reset-cells = <1>; - }; - -- clock-controller@1001e000 { -+ apmixedsys: clock-controller@1001e000 { - compatible = "mediatek,mt7981-apmixedsys"; - reg = <0 0x1001e000 0 0x1000>; - #clock-cells = <1>; -@@ -184,6 +184,31 @@ - status = "disabled"; - }; - -+ thermal@1100c800 { -+ compatible = "mediatek,mt7981-thermal", -+ "mediatek,mt7986-thermal"; -+ reg = <0 0x1100c800 0 0x800>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_THERM_CK>, -+ <&infracfg CLK_INFRA_ADC_26M_CK>; -+ clock-names = "therm", "auxadc"; -+ nvmem-cells = <&thermal_calibration>; -+ nvmem-cell-names = "calibration-data"; -+ #thermal-sensor-cells = <1>; -+ mediatek,auxadc = <&auxadc>; -+ mediatek,apmixedsys = <&apmixedsys>; -+ }; -+ -+ auxadc: adc@1100d000 { -+ compatible = "mediatek,mt7981-auxadc", -+ "mediatek,mt7986-auxadc"; -+ reg = <0 0x1100d000 0 0x1000>; -+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; -+ clock-names = "main"; -+ #io-channel-cells = <1>; -+ status = "disabled"; -+ }; -+ - pio: pinctrl@11d00000 { - compatible = "mediatek,mt7981-pinctrl"; - reg = <0 0x11d00000 0 0x1000>, -@@ -211,6 +236,10 @@ - reg = <0 0x11f20000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; -+ -+ thermal_calibration: thermal-calib@274 { -+ reg = <0x274 0xc>; -+ }; - }; - - clock-controller@15000000 { diff --git a/target/linux/mediatek/patches-6.18/070-v7.0-pinctrl-mediatek-enable-ies_present-flag-for-MT798x.patch b/target/linux/mediatek/patches-6.18/070-v7.0-pinctrl-mediatek-enable-ies_present-flag-for-MT798x.patch index 47263733ac..295d1bb159 100644 --- a/target/linux/mediatek/patches-6.18/070-v7.0-pinctrl-mediatek-enable-ies_present-flag-for-MT798x.patch +++ b/target/linux/mediatek/patches-6.18/070-v7.0-pinctrl-mediatek-enable-ies_present-flag-for-MT798x.patch @@ -48,7 +48,7 @@ Signed-off-by: Linus Walleij .bias_disable_set = mtk_pinconf_bias_disable_set, --- a/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c -@@ -1515,7 +1515,7 @@ static const struct mtk_pin_soc mt7988_d +@@ -1505,7 +1505,7 @@ static const struct mtk_pin_soc mt7988_d .nfuncs = ARRAY_SIZE(mt7988_functions), .eint_hw = &mt7988_eint_hw, .gpio_m = 0, diff --git a/target/linux/mediatek/patches-6.18/080-v6.19-drm-mediatek-mtk_hdmi_common-Defer-probe-when-ddc-i2.patch b/target/linux/mediatek/patches-6.18/080-v6.19-drm-mediatek-mtk_hdmi_common-Defer-probe-when-ddc-i2.patch new file mode 100644 index 0000000000..60b85119ac --- /dev/null +++ b/target/linux/mediatek/patches-6.18/080-v6.19-drm-mediatek-mtk_hdmi_common-Defer-probe-when-ddc-i2.patch @@ -0,0 +1,29 @@ +From 022afb0106bb5dba0f1f4ed58e88bb119081e191 Mon Sep 17 00:00:00 2001 +From: Sjoerd Simons +Date: Thu, 23 Oct 2025 12:32:37 +0200 +Subject: [PATCH] drm/mediatek: mtk_hdmi_common: Defer probe when ddc i2c bus + isn't available yet + +The i2c adapter for ddc might not be available yet due to e.g. its +module not yet being loaded. To handle that defer probing rather then +returning a fatal error when probing. + +Signed-off-by: Sjoerd Simons +Signed-off-by: Louis-Alexis Eyraud +Signed-off-by: Chun-Kuang Hu +[cherry-pick to 6.18] +--- + drivers/gpu/drm/mediatek/mtk_hdmi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c ++++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c +@@ -1432,7 +1432,7 @@ static int mtk_hdmi_dt_parse_pdata(struc + hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np); + of_node_put(i2c_np); + if (!hdmi->ddc_adpt) +- return dev_err_probe(dev, -EINVAL, "Failed to get ddc i2c adapter by node\n"); ++ return dev_err_probe(dev, -EPROBE_DEFER, "Failed to get ddc i2c adapter by node\n"); + + ret = devm_add_action_or_reset(dev, mtk_hdmi_put_device, &hdmi->ddc_adpt->dev); + if (ret) diff --git a/target/linux/mediatek/patches-6.18/090-v7.1-drm-prime-Limit-scatter-list-size-with-dedicated-DMA.patch b/target/linux/mediatek/patches-6.18/090-v7.1-drm-prime-Limit-scatter-list-size-with-dedicated-DMA.patch new file mode 100644 index 0000000000..2e825de0a6 --- /dev/null +++ b/target/linux/mediatek/patches-6.18/090-v7.1-drm-prime-Limit-scatter-list-size-with-dedicated-DMA.patch @@ -0,0 +1,35 @@ +From 709c19cccb5bb3d10be47687cbbc968d2b19c851 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Wed, 11 Mar 2026 17:49:25 +0800 +Subject: [PATCH 1/4] drm/prime: Limit scatter list size with dedicated DMA + device + +If a dedicated DMA device is specified for the DRM device, then the +scatter list size limit should pertain to the DMA device. + +Use the dedicated DMA device, if given, to limit the scatter list size. +This only applies to drivers that have called drm_dev_set_dma_dev() and +are using drm_prime_pages_to_sg() either directly or through the SHMEM +helpers. At the time of this writing, the former case only includes the +Rockchip DRM driver, while the latter case includes the gud, udl, and +the tiny appletbdrm and gm12u320 drivers. + +Reviewed-by: Thomas Zimmermann +Reviewed-by: AngeloGioacchino Del Regno +Link: https://patch.msgid.link/20260311094929.3393338-2-wenst@chromium.org +Signed-off-by: Chen-Yu Tsai +--- + drivers/gpu/drm/drm_prime.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/drm_prime.c ++++ b/drivers/gpu/drm/drm_prime.c +@@ -858,7 +858,7 @@ struct sg_table *drm_prime_pages_to_sg(s + return ERR_PTR(-ENOMEM); + + if (dev) +- max_segment = dma_max_mapping_size(dev->dev); ++ max_segment = dma_max_mapping_size(drm_dev_dma_dev(dev)); + if (max_segment == 0) + max_segment = UINT_MAX; + err = sg_alloc_table_from_pages_segment(sg, pages, nr_pages, 0, diff --git a/target/linux/mediatek/patches-6.18/091-v7.1-drm-gem-dma-Support-dedicated-DMA-device-for-allocat.patch b/target/linux/mediatek/patches-6.18/091-v7.1-drm-gem-dma-Support-dedicated-DMA-device-for-allocat.patch new file mode 100644 index 0000000000..3425536f25 --- /dev/null +++ b/target/linux/mediatek/patches-6.18/091-v7.1-drm-gem-dma-Support-dedicated-DMA-device-for-allocat.patch @@ -0,0 +1,94 @@ +From 0f8bd61dd09d7b24640193d2b12b42c0bb5fe09d Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Wed, 11 Mar 2026 17:49:26 +0800 +Subject: [PATCH 2/4] drm/gem-dma: Support dedicated DMA device for allocation + and mapping + +Support for a dedicated DMA device for prime imports was added in commit +143ec8d3f939 ("drm/prime: Support dedicated DMA device for dma-buf imports"). +This allowed the DRM driver to provide a dedicated DMA device when its +own underlying device was not capable of DMA, for example when it is a +USB device (the original target) or a virtual device. The latter case is +common on embedded SoCs, on which the display pipeline is composed of +various fixed function blocks, and the DRM device is simply a made-up +device, an address space managing the routing between the blocks, or +whichever block the implementor thought made sense at the time. The +point is that the chosen device is often not the actual device doing +the DMA. Various drivers have used workarounds or reimplemented the +GEM DMA helpers to get the DMA addresses and IOMMUs to work correctly. + +Add support for the dedicated DMA device to the GEM DMA helpers. + +No existing driver currently uses the GEM DMA helpers and calls +drm_dev_set_dma_dev() to set a dedicated DMA device, so no existing +users should be affected. + +Reviewed-by: Thomas Zimmermann +Reviewed-by: AngeloGioacchino Del Regno +Link: https://patch.msgid.link/20260311094929.3393338-3-wenst@chromium.org +Signed-off-by: Chen-Yu Tsai +--- + drivers/gpu/drm/drm_gem_dma_helper.c | 21 ++++++++++++--------- + 1 file changed, 12 insertions(+), 9 deletions(-) + +--- a/drivers/gpu/drm/drm_gem_dma_helper.c ++++ b/drivers/gpu/drm/drm_gem_dma_helper.c +@@ -144,12 +144,13 @@ struct drm_gem_dma_object *drm_gem_dma_c + return dma_obj; + + if (dma_obj->map_noncoherent) { +- dma_obj->vaddr = dma_alloc_noncoherent(drm->dev, size, ++ dma_obj->vaddr = dma_alloc_noncoherent(drm_dev_dma_dev(drm), ++ size, + &dma_obj->dma_addr, + DMA_TO_DEVICE, + GFP_KERNEL | __GFP_NOWARN); + } else { +- dma_obj->vaddr = dma_alloc_wc(drm->dev, size, ++ dma_obj->vaddr = dma_alloc_wc(drm_dev_dma_dev(drm), size, + &dma_obj->dma_addr, + GFP_KERNEL | __GFP_NOWARN); + } +@@ -234,12 +235,14 @@ void drm_gem_dma_free(struct drm_gem_dma + drm_prime_gem_destroy(gem_obj, dma_obj->sgt); + } else if (dma_obj->vaddr) { + if (dma_obj->map_noncoherent) +- dma_free_noncoherent(gem_obj->dev->dev, dma_obj->base.size, ++ dma_free_noncoherent(drm_dev_dma_dev(gem_obj->dev), ++ dma_obj->base.size, + dma_obj->vaddr, dma_obj->dma_addr, + DMA_TO_DEVICE); + else +- dma_free_wc(gem_obj->dev->dev, dma_obj->base.size, +- dma_obj->vaddr, dma_obj->dma_addr); ++ dma_free_wc(drm_dev_dma_dev(gem_obj->dev), ++ dma_obj->base.size, dma_obj->vaddr, ++ dma_obj->dma_addr); + } + + drm_gem_object_release(gem_obj); +@@ -428,7 +431,7 @@ struct sg_table *drm_gem_dma_get_sg_tabl + if (!sgt) + return ERR_PTR(-ENOMEM); + +- ret = dma_get_sgtable(obj->dev->dev, sgt, dma_obj->vaddr, ++ ret = dma_get_sgtable(drm_dev_dma_dev(obj->dev), sgt, dma_obj->vaddr, + dma_obj->dma_addr, obj->size); + if (ret < 0) + goto out; +@@ -535,12 +538,12 @@ int drm_gem_dma_mmap(struct drm_gem_dma_ + if (dma_obj->map_noncoherent) { + vma->vm_page_prot = vm_get_page_prot(vma->vm_flags); + +- ret = dma_mmap_pages(dma_obj->base.dev->dev, ++ ret = dma_mmap_pages(drm_dev_dma_dev(dma_obj->base.dev), + vma, vma->vm_end - vma->vm_start, + virt_to_page(dma_obj->vaddr)); + } else { +- ret = dma_mmap_wc(dma_obj->base.dev->dev, vma, dma_obj->vaddr, +- dma_obj->dma_addr, ++ ret = dma_mmap_wc(drm_dev_dma_dev(dma_obj->base.dev), vma, ++ dma_obj->vaddr, dma_obj->dma_addr, + vma->vm_end - vma->vm_start); + } + if (ret) diff --git a/target/linux/mediatek/patches-6.18/092-v7.1-drm-mediatek-mtk_gem-Partial-refactor-and-use-drm_ge.patch b/target/linux/mediatek/patches-6.18/092-v7.1-drm-mediatek-mtk_gem-Partial-refactor-and-use-drm_ge.patch new file mode 100644 index 0000000000..1881f8349a --- /dev/null +++ b/target/linux/mediatek/patches-6.18/092-v7.1-drm-mediatek-mtk_gem-Partial-refactor-and-use-drm_ge.patch @@ -0,0 +1,519 @@ +From 76537a68686190bff0ea24e09cdfea05aed0a3c0 Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Tue, 11 Nov 2025 09:51:14 +0100 +Subject: [PATCH 3/4] drm/mediatek: mtk_gem: Partial refactor and use + drm_gem_dma_object + +Partially refactor mtk_gem to stop using (and remove) the unneeded +custom mtk_gem_obj structure and migrate drivers to use the API +defined drm_gem_dma_object structure instead, and to align all of +the functions to be similar to the logic from drm_gem_dma_helper. + +Unfortunately, for this driver it wasn't possible to directly use +the drm_gem_dma_helper callbacks (apart from .print_info), as the +DMA mapping here is done on specific dma devices instead of the +main DRM device. + +Also, since the mtk_gem_obj structure is no more, also migrate the +mtk_plane.c code to grab the DMA address from a drm_gem_dma_object +and replace the inclusion of the custom mtk_gem.h header (as it is +now unneeded) with the DRM API provided drm_gem_dma_helper. + +While at it, also set DRM_GEM_DMA_HELPER as an unconditional +dependency (remove the `if DRM_FBDEV_EMULATION` from the select +DRM_GEM_DMA_HELPER statement in Kconfig). + +This resolves an issue pointed by UBSAN, as when using drm_fbdev_dma +the drm_gem_object is supposed to be child of a drm_gem_dma_object +instead of a custom mtk_gem_obj (or the mtk_gem_obj should have been +reordered to have the same fields as drm_gem_dma_object, but that +would have been too fragile and generally a bad idea anyway). + +Fixes: 0992284b4fe4 ("drm/mediatek: Use fbdev-dma") +Signed-off-by: AngeloGioacchino Del Regno +Link: https://patchwork.kernel.org/project/dri-devel/patch/20251111085114.9752-1-angelogioacchino.delregno@collabora.com/ +Signed-off-by: Chun-Kuang Hu +--- + drivers/gpu/drm/mediatek/Kconfig | 2 +- + drivers/gpu/drm/mediatek/mtk_gem.c | 264 +++++++++++---------------- + drivers/gpu/drm/mediatek/mtk_gem.h | 33 +--- + drivers/gpu/drm/mediatek/mtk_plane.c | 9 +- + 4 files changed, 110 insertions(+), 198 deletions(-) + +--- a/drivers/gpu/drm/mediatek/Kconfig ++++ b/drivers/gpu/drm/mediatek/Kconfig +@@ -8,7 +8,7 @@ config DRM_MEDIATEK + depends on OF + depends on MTK_MMSYS + select DRM_CLIENT_SELECTION +- select DRM_GEM_DMA_HELPER if DRM_FBDEV_EMULATION ++ select DRM_GEM_DMA_HELPER + select DRM_KMS_HELPER + select DRM_DISPLAY_HELPER + select DRM_BRIDGE_CONNECTOR +--- a/drivers/gpu/drm/mediatek/mtk_gem.c ++++ b/drivers/gpu/drm/mediatek/mtk_gem.c +@@ -1,6 +1,8 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* + * Copyright (c) 2015 MediaTek Inc. ++ * Copyright (c) 2025 Collabora Ltd. ++ * AngeloGioacchino Del Regno + */ + + #include +@@ -17,24 +19,64 @@ + + static int mtk_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); + +-static const struct vm_operations_struct vm_ops = { +- .open = drm_gem_vm_open, +- .close = drm_gem_vm_close, +-}; ++static void mtk_gem_free_object(struct drm_gem_object *obj) ++{ ++ struct drm_gem_dma_object *dma_obj = to_drm_gem_dma_obj(obj); ++ struct mtk_drm_private *priv = obj->dev->dev_private; ++ ++ if (dma_obj->sgt) ++ drm_prime_gem_destroy(obj, dma_obj->sgt); ++ else ++ dma_free_wc(priv->dma_dev, dma_obj->base.size, ++ dma_obj->vaddr, dma_obj->dma_addr); ++ ++ /* release file pointer to gem object. */ ++ drm_gem_object_release(obj); ++ ++ kfree(dma_obj); ++} ++ ++/* ++ * Allocate a sg_table for this GEM object. ++ * Note: Both the table's contents, and the sg_table itself must be freed by ++ * the caller. ++ * Returns a pointer to the newly allocated sg_table, or an ERR_PTR() error. ++ */ ++static struct sg_table *mtk_gem_prime_get_sg_table(struct drm_gem_object *obj) ++{ ++ struct drm_gem_dma_object *dma_obj = to_drm_gem_dma_obj(obj); ++ struct mtk_drm_private *priv = obj->dev->dev_private; ++ struct sg_table *sgt; ++ int ret; ++ ++ sgt = kzalloc(sizeof(*sgt), GFP_KERNEL); ++ if (!sgt) ++ return ERR_PTR(-ENOMEM); ++ ++ ret = dma_get_sgtable(priv->dma_dev, sgt, dma_obj->vaddr, ++ dma_obj->dma_addr, obj->size); ++ if (ret) { ++ DRM_ERROR("failed to allocate sgt, %d\n", ret); ++ kfree(sgt); ++ return ERR_PTR(ret); ++ } ++ ++ return sgt; ++} + + static const struct drm_gem_object_funcs mtk_gem_object_funcs = { + .free = mtk_gem_free_object, ++ .print_info = drm_gem_dma_object_print_info, + .get_sg_table = mtk_gem_prime_get_sg_table, +- .vmap = mtk_gem_prime_vmap, +- .vunmap = mtk_gem_prime_vunmap, ++ .vmap = drm_gem_dma_object_vmap, + .mmap = mtk_gem_object_mmap, +- .vm_ops = &vm_ops, ++ .vm_ops = &drm_gem_dma_vm_ops, + }; + +-static struct mtk_gem_obj *mtk_gem_init(struct drm_device *dev, +- unsigned long size) ++static struct drm_gem_dma_object *mtk_gem_init(struct drm_device *dev, ++ unsigned long size, bool private) + { +- struct mtk_gem_obj *mtk_gem_obj; ++ struct drm_gem_dma_object *dma_obj; + int ret; + + size = round_up(size, PAGE_SIZE); +@@ -42,86 +84,65 @@ static struct mtk_gem_obj *mtk_gem_init( + if (size == 0) + return ERR_PTR(-EINVAL); + +- mtk_gem_obj = kzalloc(sizeof(*mtk_gem_obj), GFP_KERNEL); +- if (!mtk_gem_obj) ++ dma_obj = kzalloc(sizeof(*dma_obj), GFP_KERNEL); ++ if (!dma_obj) + return ERR_PTR(-ENOMEM); + +- mtk_gem_obj->base.funcs = &mtk_gem_object_funcs; ++ dma_obj->base.funcs = &mtk_gem_object_funcs; + +- ret = drm_gem_object_init(dev, &mtk_gem_obj->base, size); +- if (ret < 0) { ++ if (private) { ++ ret = 0; ++ drm_gem_private_object_init(dev, &dma_obj->base, size); ++ } else { ++ ret = drm_gem_object_init(dev, &dma_obj->base, size); ++ } ++ if (ret) { + DRM_ERROR("failed to initialize gem object\n"); +- kfree(mtk_gem_obj); ++ kfree(dma_obj); + return ERR_PTR(ret); + } + +- return mtk_gem_obj; ++ return dma_obj; + } + +-struct mtk_gem_obj *mtk_gem_create(struct drm_device *dev, +- size_t size, bool alloc_kmap) ++static struct drm_gem_dma_object *mtk_gem_create(struct drm_device *dev, size_t size) + { + struct mtk_drm_private *priv = dev->dev_private; +- struct mtk_gem_obj *mtk_gem; ++ struct drm_gem_dma_object *dma_obj; + struct drm_gem_object *obj; + int ret; + +- mtk_gem = mtk_gem_init(dev, size); +- if (IS_ERR(mtk_gem)) +- return ERR_CAST(mtk_gem); +- +- obj = &mtk_gem->base; +- +- mtk_gem->dma_attrs = DMA_ATTR_WRITE_COMBINE; +- +- if (!alloc_kmap) +- mtk_gem->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING; +- +- mtk_gem->cookie = dma_alloc_attrs(priv->dma_dev, obj->size, +- &mtk_gem->dma_addr, GFP_KERNEL, +- mtk_gem->dma_attrs); +- if (!mtk_gem->cookie) { ++ dma_obj = mtk_gem_init(dev, size, false); ++ if (IS_ERR(dma_obj)) ++ return ERR_CAST(dma_obj); ++ ++ obj = &dma_obj->base; ++ ++ dma_obj->vaddr = dma_alloc_wc(priv->dma_dev, obj->size, ++ &dma_obj->dma_addr, ++ GFP_KERNEL | __GFP_NOWARN); ++ if (!dma_obj->vaddr) { + DRM_ERROR("failed to allocate %zx byte dma buffer", obj->size); + ret = -ENOMEM; + goto err_gem_free; + } + +- if (alloc_kmap) +- mtk_gem->kvaddr = mtk_gem->cookie; +- +- DRM_DEBUG_DRIVER("cookie = %p dma_addr = %pad size = %zu\n", +- mtk_gem->cookie, &mtk_gem->dma_addr, ++ DRM_DEBUG_DRIVER("vaddr = %p dma_addr = %pad size = %zu\n", ++ dma_obj->vaddr, &dma_obj->dma_addr, + size); + +- return mtk_gem; ++ return dma_obj; + + err_gem_free: + drm_gem_object_release(obj); +- kfree(mtk_gem); ++ kfree(dma_obj); + return ERR_PTR(ret); + } + +-void mtk_gem_free_object(struct drm_gem_object *obj) +-{ +- struct mtk_gem_obj *mtk_gem = to_mtk_gem_obj(obj); +- struct mtk_drm_private *priv = obj->dev->dev_private; +- +- if (mtk_gem->sg) +- drm_prime_gem_destroy(obj, mtk_gem->sg); +- else +- dma_free_attrs(priv->dma_dev, obj->size, mtk_gem->cookie, +- mtk_gem->dma_addr, mtk_gem->dma_attrs); +- +- /* release file pointer to gem object. */ +- drm_gem_object_release(obj); +- +- kfree(mtk_gem); +-} +- + int mtk_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, + struct drm_mode_create_dumb *args) + { +- struct mtk_gem_obj *mtk_gem; ++ struct drm_gem_dma_object *dma_obj; + int ret; + + args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8); +@@ -134,25 +155,25 @@ int mtk_gem_dumb_create(struct drm_file + args->size = args->pitch; + args->size *= args->height; + +- mtk_gem = mtk_gem_create(dev, args->size, false); +- if (IS_ERR(mtk_gem)) +- return PTR_ERR(mtk_gem); ++ dma_obj = mtk_gem_create(dev, args->size); ++ if (IS_ERR(dma_obj)) ++ return PTR_ERR(dma_obj); + + /* + * allocate a id of idr table where the obj is registered + * and handle has the id what user can see. + */ +- ret = drm_gem_handle_create(file_priv, &mtk_gem->base, &args->handle); ++ ret = drm_gem_handle_create(file_priv, &dma_obj->base, &args->handle); + if (ret) + goto err_handle_create; + + /* drop reference from allocate - handle holds it now. */ +- drm_gem_object_put(&mtk_gem->base); ++ drm_gem_object_put(&dma_obj->base); + + return 0; + + err_handle_create: +- mtk_gem_free_object(&mtk_gem->base); ++ mtk_gem_free_object(&dma_obj->base); + return ret; + } + +@@ -160,129 +181,50 @@ static int mtk_gem_object_mmap(struct dr + struct vm_area_struct *vma) + + { +- int ret; +- struct mtk_gem_obj *mtk_gem = to_mtk_gem_obj(obj); ++ struct drm_gem_dma_object *dma_obj = to_drm_gem_dma_obj(obj); + struct mtk_drm_private *priv = obj->dev->dev_private; ++ int ret; + + /* + * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the + * whole buffer from the start. + */ +- vma->vm_pgoff = 0; ++ vma->vm_pgoff -= drm_vma_node_start(&obj->vma_node); + + /* + * dma_alloc_attrs() allocated a struct page table for mtk_gem, so clear + * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap(). + */ +- vm_flags_set(vma, VM_IO | VM_DONTEXPAND | VM_DONTDUMP); ++ vm_flags_mod(vma, VM_IO | VM_DONTEXPAND | VM_DONTDUMP, VM_PFNMAP); ++ + vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); + vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); + +- ret = dma_mmap_attrs(priv->dma_dev, vma, mtk_gem->cookie, +- mtk_gem->dma_addr, obj->size, mtk_gem->dma_attrs); ++ ret = dma_mmap_wc(priv->dma_dev, vma, dma_obj->vaddr, ++ dma_obj->dma_addr, obj->size); ++ if (ret) ++ drm_gem_vm_close(vma); + + return ret; + } + +-/* +- * Allocate a sg_table for this GEM object. +- * Note: Both the table's contents, and the sg_table itself must be freed by +- * the caller. +- * Returns a pointer to the newly allocated sg_table, or an ERR_PTR() error. +- */ +-struct sg_table *mtk_gem_prime_get_sg_table(struct drm_gem_object *obj) +-{ +- struct mtk_gem_obj *mtk_gem = to_mtk_gem_obj(obj); +- struct mtk_drm_private *priv = obj->dev->dev_private; +- struct sg_table *sgt; +- int ret; +- +- sgt = kzalloc(sizeof(*sgt), GFP_KERNEL); +- if (!sgt) +- return ERR_PTR(-ENOMEM); +- +- ret = dma_get_sgtable_attrs(priv->dma_dev, sgt, mtk_gem->cookie, +- mtk_gem->dma_addr, obj->size, +- mtk_gem->dma_attrs); +- if (ret) { +- DRM_ERROR("failed to allocate sgt, %d\n", ret); +- kfree(sgt); +- return ERR_PTR(ret); +- } +- +- return sgt; +-} +- + struct drm_gem_object *mtk_gem_prime_import_sg_table(struct drm_device *dev, +- struct dma_buf_attachment *attach, struct sg_table *sg) ++ struct dma_buf_attachment *attach, struct sg_table *sgt) + { +- struct mtk_gem_obj *mtk_gem; ++ struct drm_gem_dma_object *dma_obj; + + /* check if the entries in the sg_table are contiguous */ +- if (drm_prime_get_contiguous_size(sg) < attach->dmabuf->size) { ++ if (drm_prime_get_contiguous_size(sgt) < attach->dmabuf->size) { + DRM_ERROR("sg_table is not contiguous"); + return ERR_PTR(-EINVAL); + } + +- mtk_gem = mtk_gem_init(dev, attach->dmabuf->size); +- if (IS_ERR(mtk_gem)) +- return ERR_CAST(mtk_gem); +- +- mtk_gem->dma_addr = sg_dma_address(sg->sgl); +- mtk_gem->sg = sg; +- +- return &mtk_gem->base; +-} +- +-int mtk_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map) +-{ +- struct mtk_gem_obj *mtk_gem = to_mtk_gem_obj(obj); +- struct sg_table *sgt = NULL; +- unsigned int npages; +- +- if (mtk_gem->kvaddr) +- goto out; +- +- sgt = mtk_gem_prime_get_sg_table(obj); +- if (IS_ERR(sgt)) +- return PTR_ERR(sgt); +- +- npages = obj->size >> PAGE_SHIFT; +- mtk_gem->pages = kcalloc(npages, sizeof(*mtk_gem->pages), GFP_KERNEL); +- if (!mtk_gem->pages) { +- sg_free_table(sgt); +- kfree(sgt); +- return -ENOMEM; +- } +- +- drm_prime_sg_to_page_array(sgt, mtk_gem->pages, npages); +- +- mtk_gem->kvaddr = vmap(mtk_gem->pages, npages, VM_MAP, +- pgprot_writecombine(PAGE_KERNEL)); +- if (!mtk_gem->kvaddr) { +- sg_free_table(sgt); +- kfree(sgt); +- kfree(mtk_gem->pages); +- return -ENOMEM; +- } +- sg_free_table(sgt); +- kfree(sgt); +- +-out: +- iosys_map_set_vaddr(map, mtk_gem->kvaddr); +- +- return 0; +-} +- +-void mtk_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map) +-{ +- struct mtk_gem_obj *mtk_gem = to_mtk_gem_obj(obj); +- void *vaddr = map->vaddr; ++ dma_obj = mtk_gem_init(dev, attach->dmabuf->size, true); ++ if (IS_ERR(dma_obj)) ++ return ERR_CAST(dma_obj); + +- if (!mtk_gem->pages) +- return; ++ dma_obj->dma_addr = sg_dma_address(sgt->sgl); ++ dma_obj->sgt = sgt; + +- vunmap(vaddr); +- mtk_gem->kvaddr = NULL; +- kfree(mtk_gem->pages); ++ return &dma_obj->base; + } +--- a/drivers/gpu/drm/mediatek/mtk_gem.h ++++ b/drivers/gpu/drm/mediatek/mtk_gem.h +@@ -7,42 +7,11 @@ + #define _MTK_GEM_H_ + + #include ++#include + +-/* +- * mtk drm buffer structure. +- * +- * @base: a gem object. +- * - a new handle to this gem object would be created +- * by drm_gem_handle_create(). +- * @cookie: the return value of dma_alloc_attrs(), keep it for dma_free_attrs() +- * @kvaddr: kernel virtual address of gem buffer. +- * @dma_addr: dma address of gem buffer. +- * @dma_attrs: dma attributes of gem buffer. +- * +- * P.S. this object would be transferred to user as kms_bo.handle so +- * user can access the buffer through kms_bo.handle. +- */ +-struct mtk_gem_obj { +- struct drm_gem_object base; +- void *cookie; +- void *kvaddr; +- dma_addr_t dma_addr; +- unsigned long dma_attrs; +- struct sg_table *sg; +- struct page **pages; +-}; +- +-#define to_mtk_gem_obj(x) container_of(x, struct mtk_gem_obj, base) +- +-void mtk_gem_free_object(struct drm_gem_object *gem); +-struct mtk_gem_obj *mtk_gem_create(struct drm_device *dev, size_t size, +- bool alloc_kmap); + int mtk_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, + struct drm_mode_create_dumb *args); +-struct sg_table *mtk_gem_prime_get_sg_table(struct drm_gem_object *obj); + struct drm_gem_object *mtk_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, struct sg_table *sg); +-int mtk_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); +-void mtk_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); + + #endif +--- a/drivers/gpu/drm/mediatek/mtk_plane.c ++++ b/drivers/gpu/drm/mediatek/mtk_plane.c +@@ -11,12 +11,13 @@ + #include + #include + #include ++#include ++#include + #include + + #include "mtk_crtc.h" + #include "mtk_ddp_comp.h" + #include "mtk_drm_drv.h" +-#include "mtk_gem.h" + #include "mtk_plane.h" + + static const u64 modifiers[] = { +@@ -112,8 +113,8 @@ static void mtk_plane_update_new_state(s + struct mtk_plane_state *mtk_plane_state) + { + struct drm_framebuffer *fb = new_state->fb; ++ struct drm_gem_dma_object *dma_obj; + struct drm_gem_object *gem; +- struct mtk_gem_obj *mtk_gem; + unsigned int pitch, format; + u64 modifier; + dma_addr_t addr; +@@ -122,8 +123,8 @@ static void mtk_plane_update_new_state(s + int offset; + + gem = fb->obj[0]; +- mtk_gem = to_mtk_gem_obj(gem); +- addr = mtk_gem->dma_addr; ++ dma_obj = to_drm_gem_dma_obj(gem); ++ addr = dma_obj->dma_addr; + pitch = fb->pitches[0]; + format = fb->format->format; + modifier = fb->modifier; diff --git a/target/linux/mediatek/patches-6.18/093-v7.1-drm-mediatek-Set-dedicated-DMA-device-and-drop-custo.patch b/target/linux/mediatek/patches-6.18/093-v7.1-drm-mediatek-Set-dedicated-DMA-device-and-drop-custo.patch new file mode 100644 index 0000000000..9e79da6611 --- /dev/null +++ b/target/linux/mediatek/patches-6.18/093-v7.1-drm-mediatek-Set-dedicated-DMA-device-and-drop-custo.patch @@ -0,0 +1,388 @@ +From 80f543ceef4c9983c1cf37850000f0fa7782b471 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Wed, 11 Mar 2026 17:49:27 +0800 +Subject: [PATCH 4/4] drm/mediatek: Set dedicated DMA device and drop custom + GEM callbacks + +In commit 9b54a32c7c6a ("drm/mediatek: mtk_gem: Partial refactor and +use drm_gem_dma_object") the MediaTek DRM driver was refactored to use +drm_gem_dma_object, but custom callbacks were still needed to deal with +using the first device of the pipeline as the DMA device, instead of +the MMSYS device that the DRM driver binds to. + +Turns out there is already partial support for dedicated DMA devices in +the DRM subsystem for PRIME imports. The preceding patches add support +for dedicated DMA devices to the GEM DMA helpers. + +This allows us to just set the dedicated DMA device for the DRM device, +and drop all the custom GEM callbacks. Also drop the .dma_dev field +from the driver private data as it is no longer needed. + +There are slight differences in the mmap helper: the VM_DONTDUMP and +VM_IO flags are no longer set. Both were lifted from drm_gem_mmap_obj(). +VM_IO probably doesn't make sense since the buffer is allocated using +dma_alloc_attrs(). + +Reviewed-by: Thomas Zimmermann +Acked-by: Chun-Kuang Hu +Reviewed-by: AngeloGioacchino Del Regno +Link: https://patch.msgid.link/20260311094929.3393338-4-wenst@chromium.org +Signed-off-by: Chen-Yu Tsai +--- + drivers/gpu/drm/mediatek/Makefile | 1 - + drivers/gpu/drm/mediatek/mtk_crtc.c | 2 +- + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 21 +-- + drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 - + drivers/gpu/drm/mediatek/mtk_gem.c | 230 ------------------------- + drivers/gpu/drm/mediatek/mtk_gem.h | 17 -- + 6 files changed, 4 insertions(+), 268 deletions(-) + delete mode 100644 drivers/gpu/drm/mediatek/mtk_gem.c + delete mode 100644 drivers/gpu/drm/mediatek/mtk_gem.h + +--- a/drivers/gpu/drm/mediatek/Makefile ++++ b/drivers/gpu/drm/mediatek/Makefile +@@ -14,7 +14,6 @@ mediatek-drm-y := mtk_crtc.o \ + mtk_dsi.o \ + mtk_dpi.o \ + mtk_ethdr.o \ +- mtk_gem.o \ + mtk_mdp_rdma.o \ + mtk_padding.o \ + mtk_plane.o +--- a/drivers/gpu/drm/mediatek/mtk_crtc.c ++++ b/drivers/gpu/drm/mediatek/mtk_crtc.c +@@ -14,6 +14,7 @@ + + #include + ++#include + #include + #include + #include +@@ -22,7 +23,6 @@ + #include "mtk_crtc.h" + #include "mtk_ddp_comp.h" + #include "mtk_drm_drv.h" +-#include "mtk_gem.h" + #include "mtk_plane.h" + + /* +--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c ++++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -29,7 +30,6 @@ + #include "mtk_ddp_comp.h" + #include "mtk_disp_drv.h" + #include "mtk_drm_drv.h" +-#include "mtk_gem.h" + + #define DRIVER_NAME "mediatek" + #define DRIVER_DESC "Mediatek SoC DRM" +@@ -565,8 +565,7 @@ static int mtk_drm_kms_init(struct drm_d + goto err_component_unbind; + } + +- for (i = 0; i < private->data->mmsys_dev_num; i++) +- private->all_drm_private[i]->dma_dev = dma_dev; ++ drm_dev_set_dma_dev(drm, dma_dev); + + /* + * Configure the DMA segment size to make sure we get contiguous IOVA +@@ -600,26 +599,12 @@ static void mtk_drm_kms_deinit(struct dr + + DEFINE_DRM_GEM_FOPS(mtk_drm_fops); + +-/* +- * We need to override this because the device used to import the memory is +- * not dev->dev, as drm_gem_prime_import() expects. +- */ +-static struct drm_gem_object *mtk_gem_prime_import(struct drm_device *dev, +- struct dma_buf *dma_buf) +-{ +- struct mtk_drm_private *private = dev->dev_private; +- +- return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); +-} +- + static const struct drm_driver mtk_drm_driver = { + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, + +- .dumb_create = mtk_gem_dumb_create, ++ DRM_GEM_DMA_DRIVER_OPS, + DRM_FBDEV_DMA_DRIVER_OPS, + +- .gem_prime_import = mtk_gem_prime_import, +- .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, + .fops = &mtk_drm_fops, + + .name = DRIVER_NAME, +--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h ++++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h +@@ -54,7 +54,6 @@ struct mtk_mmsys_driver_data { + + struct mtk_drm_private { + struct drm_device *drm; +- struct device *dma_dev; + bool mtk_drm_bound; + bool drm_master; + struct device *dev; +--- a/drivers/gpu/drm/mediatek/mtk_gem.c ++++ /dev/null +@@ -1,230 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2015 MediaTek Inc. +- * Copyright (c) 2025 Collabora Ltd. +- * AngeloGioacchino Del Regno +- */ +- +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +- +-#include "mtk_drm_drv.h" +-#include "mtk_gem.h" +- +-static int mtk_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); +- +-static void mtk_gem_free_object(struct drm_gem_object *obj) +-{ +- struct drm_gem_dma_object *dma_obj = to_drm_gem_dma_obj(obj); +- struct mtk_drm_private *priv = obj->dev->dev_private; +- +- if (dma_obj->sgt) +- drm_prime_gem_destroy(obj, dma_obj->sgt); +- else +- dma_free_wc(priv->dma_dev, dma_obj->base.size, +- dma_obj->vaddr, dma_obj->dma_addr); +- +- /* release file pointer to gem object. */ +- drm_gem_object_release(obj); +- +- kfree(dma_obj); +-} +- +-/* +- * Allocate a sg_table for this GEM object. +- * Note: Both the table's contents, and the sg_table itself must be freed by +- * the caller. +- * Returns a pointer to the newly allocated sg_table, or an ERR_PTR() error. +- */ +-static struct sg_table *mtk_gem_prime_get_sg_table(struct drm_gem_object *obj) +-{ +- struct drm_gem_dma_object *dma_obj = to_drm_gem_dma_obj(obj); +- struct mtk_drm_private *priv = obj->dev->dev_private; +- struct sg_table *sgt; +- int ret; +- +- sgt = kzalloc(sizeof(*sgt), GFP_KERNEL); +- if (!sgt) +- return ERR_PTR(-ENOMEM); +- +- ret = dma_get_sgtable(priv->dma_dev, sgt, dma_obj->vaddr, +- dma_obj->dma_addr, obj->size); +- if (ret) { +- DRM_ERROR("failed to allocate sgt, %d\n", ret); +- kfree(sgt); +- return ERR_PTR(ret); +- } +- +- return sgt; +-} +- +-static const struct drm_gem_object_funcs mtk_gem_object_funcs = { +- .free = mtk_gem_free_object, +- .print_info = drm_gem_dma_object_print_info, +- .get_sg_table = mtk_gem_prime_get_sg_table, +- .vmap = drm_gem_dma_object_vmap, +- .mmap = mtk_gem_object_mmap, +- .vm_ops = &drm_gem_dma_vm_ops, +-}; +- +-static struct drm_gem_dma_object *mtk_gem_init(struct drm_device *dev, +- unsigned long size, bool private) +-{ +- struct drm_gem_dma_object *dma_obj; +- int ret; +- +- size = round_up(size, PAGE_SIZE); +- +- if (size == 0) +- return ERR_PTR(-EINVAL); +- +- dma_obj = kzalloc(sizeof(*dma_obj), GFP_KERNEL); +- if (!dma_obj) +- return ERR_PTR(-ENOMEM); +- +- dma_obj->base.funcs = &mtk_gem_object_funcs; +- +- if (private) { +- ret = 0; +- drm_gem_private_object_init(dev, &dma_obj->base, size); +- } else { +- ret = drm_gem_object_init(dev, &dma_obj->base, size); +- } +- if (ret) { +- DRM_ERROR("failed to initialize gem object\n"); +- kfree(dma_obj); +- return ERR_PTR(ret); +- } +- +- return dma_obj; +-} +- +-static struct drm_gem_dma_object *mtk_gem_create(struct drm_device *dev, size_t size) +-{ +- struct mtk_drm_private *priv = dev->dev_private; +- struct drm_gem_dma_object *dma_obj; +- struct drm_gem_object *obj; +- int ret; +- +- dma_obj = mtk_gem_init(dev, size, false); +- if (IS_ERR(dma_obj)) +- return ERR_CAST(dma_obj); +- +- obj = &dma_obj->base; +- +- dma_obj->vaddr = dma_alloc_wc(priv->dma_dev, obj->size, +- &dma_obj->dma_addr, +- GFP_KERNEL | __GFP_NOWARN); +- if (!dma_obj->vaddr) { +- DRM_ERROR("failed to allocate %zx byte dma buffer", obj->size); +- ret = -ENOMEM; +- goto err_gem_free; +- } +- +- DRM_DEBUG_DRIVER("vaddr = %p dma_addr = %pad size = %zu\n", +- dma_obj->vaddr, &dma_obj->dma_addr, +- size); +- +- return dma_obj; +- +-err_gem_free: +- drm_gem_object_release(obj); +- kfree(dma_obj); +- return ERR_PTR(ret); +-} +- +-int mtk_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, +- struct drm_mode_create_dumb *args) +-{ +- struct drm_gem_dma_object *dma_obj; +- int ret; +- +- args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8); +- +- /* +- * Multiply 2 variables of different types, +- * for example: args->size = args->spacing * args->height; +- * may cause coverity issue with unintentional overflow. +- */ +- args->size = args->pitch; +- args->size *= args->height; +- +- dma_obj = mtk_gem_create(dev, args->size); +- if (IS_ERR(dma_obj)) +- return PTR_ERR(dma_obj); +- +- /* +- * allocate a id of idr table where the obj is registered +- * and handle has the id what user can see. +- */ +- ret = drm_gem_handle_create(file_priv, &dma_obj->base, &args->handle); +- if (ret) +- goto err_handle_create; +- +- /* drop reference from allocate - handle holds it now. */ +- drm_gem_object_put(&dma_obj->base); +- +- return 0; +- +-err_handle_create: +- mtk_gem_free_object(&dma_obj->base); +- return ret; +-} +- +-static int mtk_gem_object_mmap(struct drm_gem_object *obj, +- struct vm_area_struct *vma) +- +-{ +- struct drm_gem_dma_object *dma_obj = to_drm_gem_dma_obj(obj); +- struct mtk_drm_private *priv = obj->dev->dev_private; +- int ret; +- +- /* +- * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the +- * whole buffer from the start. +- */ +- vma->vm_pgoff -= drm_vma_node_start(&obj->vma_node); +- +- /* +- * dma_alloc_attrs() allocated a struct page table for mtk_gem, so clear +- * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap(). +- */ +- vm_flags_mod(vma, VM_IO | VM_DONTEXPAND | VM_DONTDUMP, VM_PFNMAP); +- +- vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); +- vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); +- +- ret = dma_mmap_wc(priv->dma_dev, vma, dma_obj->vaddr, +- dma_obj->dma_addr, obj->size); +- if (ret) +- drm_gem_vm_close(vma); +- +- return ret; +-} +- +-struct drm_gem_object *mtk_gem_prime_import_sg_table(struct drm_device *dev, +- struct dma_buf_attachment *attach, struct sg_table *sgt) +-{ +- struct drm_gem_dma_object *dma_obj; +- +- /* check if the entries in the sg_table are contiguous */ +- if (drm_prime_get_contiguous_size(sgt) < attach->dmabuf->size) { +- DRM_ERROR("sg_table is not contiguous"); +- return ERR_PTR(-EINVAL); +- } +- +- dma_obj = mtk_gem_init(dev, attach->dmabuf->size, true); +- if (IS_ERR(dma_obj)) +- return ERR_CAST(dma_obj); +- +- dma_obj->dma_addr = sg_dma_address(sgt->sgl); +- dma_obj->sgt = sgt; +- +- return &dma_obj->base; +-} +--- a/drivers/gpu/drm/mediatek/mtk_gem.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * Copyright (c) 2015 MediaTek Inc. +- */ +- +-#ifndef _MTK_GEM_H_ +-#define _MTK_GEM_H_ +- +-#include +-#include +- +-int mtk_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, +- struct drm_mode_create_dumb *args); +-struct drm_gem_object *mtk_gem_prime_import_sg_table(struct drm_device *dev, +- struct dma_buf_attachment *attach, struct sg_table *sg); +- +-#endif diff --git a/target/linux/mediatek/patches-6.18/103-mt7623-enable-arch-timer.patch b/target/linux/mediatek/patches-6.18/103-mt7623-enable-arch-timer.patch index 04df7b927b..0c3359c37d 100644 --- a/target/linux/mediatek/patches-6.18/103-mt7623-enable-arch-timer.patch +++ b/target/linux/mediatek/patches-6.18/103-mt7623-enable-arch-timer.patch @@ -10,7 +10,7 @@ Signed-off-by: Chuanhong Guo --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -26,6 +26,7 @@ config MACH_MT6592 +@@ -30,6 +30,7 @@ config MACH_MT6592 config MACH_MT7623 bool "MediaTek MT7623 SoCs support" default ARCH_MEDIATEK diff --git a/target/linux/mediatek/patches-6.18/107-ARM-dts-mediatek-mt7623n-remove-mali-reset.patch b/target/linux/mediatek/patches-6.18/107-ARM-dts-mediatek-mt7623n-remove-mali-reset.patch new file mode 100644 index 0000000000..a0e65ee670 --- /dev/null +++ b/target/linux/mediatek/patches-6.18/107-ARM-dts-mediatek-mt7623n-remove-mali-reset.patch @@ -0,0 +1,25 @@ +From 28a23b2437f9d6ef4ebe4c8da6e420004beca938 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 14 Apr 2026 00:47:00 +0100 +Subject: [PATCH] ARM: dts: mediatek: mt7623n: remove mali reset + +The mali reset on the MT7623N is very destructive and prevents +subsequent resumes after the GPU has been suspended. +Turns out the easiest fix is to just not use it. + +Signed-off-by: Daniel Golle +--- + arch/arm/boot/dts/mediatek/mt7623n.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/mediatek/mt7623n.dtsi ++++ b/arch/arm/boot/dts/mediatek/mt7623n.dtsi +@@ -45,7 +45,7 @@ + <&g3dsys CLK_G3DSYS_CORE>; + clock-names = "bus", "core"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; +- resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; ++ /* resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; */ + }; + + mmsys: syscon@14000000 { diff --git a/target/linux/mediatek/patches-6.18/108-ARM-dts-mediatek-mt7623-fix-UART-clock-parents.patch b/target/linux/mediatek/patches-6.18/108-ARM-dts-mediatek-mt7623-fix-UART-clock-parents.patch new file mode 100644 index 0000000000..a794362ca8 --- /dev/null +++ b/target/linux/mediatek/patches-6.18/108-ARM-dts-mediatek-mt7623-fix-UART-clock-parents.patch @@ -0,0 +1,57 @@ +From fdf44e096c5a99e36120f7b3cc06eb9a1eb94ee5 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 11 Apr 2026 13:13:10 +0100 +Subject: [PATCH] ARM: dts: mediatek: mt7623: fix UART clock parents + +The per-UART baud rate muxes default to clk26m, bypassing uart_sel. +Since commit e581cf5d2162 ("clk: Get runtime PM before walking tree +during disable_unused") the unclaimed uart_sel MUX_GATE gets disabled +by clk_disable_unused, breaking UART RX which needs this clock for +input sampling. Set uart_sel as the baud clock parent so enabling a +UART port keeps uart_sel alive through clock parent propagation. + +Fixes: e581cf5d2162 ("clk: Get runtime PM before walking tree during disable_unused") +Cc: stable@vger.kernel.org +Signed-off-by: Daniel Golle +--- + arch/arm/boot/dts/mediatek/mt7623.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm/boot/dts/mediatek/mt7623.dtsi ++++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi +@@ -380,6 +380,8 @@ + clocks = <&pericfg CLK_PERI_UART0_SEL>, + <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; ++ assigned-clocks = <&pericfg CLK_PERI_UART0_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + +@@ -391,6 +393,8 @@ + clocks = <&pericfg CLK_PERI_UART1_SEL>, + <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; ++ assigned-clocks = <&pericfg CLK_PERI_UART1_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + +@@ -402,6 +406,8 @@ + clocks = <&pericfg CLK_PERI_UART2_SEL>, + <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; ++ assigned-clocks = <&pericfg CLK_PERI_UART2_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + +@@ -413,6 +419,8 @@ + clocks = <&pericfg CLK_PERI_UART3_SEL>, + <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; ++ assigned-clocks = <&pericfg CLK_PERI_UART3_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + diff --git a/target/linux/mediatek/patches-6.18/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch b/target/linux/mediatek/patches-6.18/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch index 1d53cefd7f..3057b99f9b 100644 --- a/target/linux/mediatek/patches-6.18/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch +++ b/target/linux/mediatek/patches-6.18/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch @@ -20,14 +20,3 @@ This reverts commit 963c3b0c47ec29b4c49c9f45965cd066f419d17f. compatible = "mediatek,mt7622-tphy", "mediatek,generic-tphy-v1"; #address-cells = <2>; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -428,7 +428,7 @@ - }; - }; - -- pcie_phy: t-phy { -+ pcie_phy: t-phy@11c00000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; - ranges; diff --git a/target/linux/mediatek/patches-6.18/121-hack-spi-nand-1b-bbm.patch b/target/linux/mediatek/patches-6.18/121-hack-spi-nand-1b-bbm.patch index 21459e1c17..27d0db4341 100644 --- a/target/linux/mediatek/patches-6.18/121-hack-spi-nand-1b-bbm.patch +++ b/target/linux/mediatek/patches-6.18/121-hack-spi-nand-1b-bbm.patch @@ -11,7 +11,7 @@ Signed-off-by: Chuanhong Guo --- --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -924,7 +924,7 @@ static int spinand_mtd_write(struct mtd_ +@@ -979,7 +979,7 @@ static int spinand_mtd_write(struct mtd_ static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) { struct spinand_device *spinand = nand_to_spinand(nand); @@ -20,7 +20,7 @@ Signed-off-by: Chuanhong Guo struct nand_page_io_req req = { .pos = *pos, .ooblen = sizeof(marker), -@@ -943,7 +943,7 @@ static bool spinand_isbad(struct nand_de +@@ -998,7 +998,7 @@ static bool spinand_isbad(struct nand_de spinand_read_page(spinand, &req); } diff --git a/target/linux/mediatek/patches-6.18/150-dts-mt7623-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.18/150-dts-mt7623-eip97-inside-secure-support.patch index 9e96a5a09b..4a9f51056f 100644 --- a/target/linux/mediatek/patches-6.18/150-dts-mt7623-eip97-inside-secure-support.patch +++ b/target/linux/mediatek/patches-6.18/150-dts-mt7623-eip97-inside-secure-support.patch @@ -13,7 +13,7 @@ Signed-off-by: John Crispin --- --- a/arch/arm/boot/dts/mediatek/mt7623.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi -@@ -995,17 +995,15 @@ +@@ -1003,17 +1003,15 @@ }; crypto: crypto@1b240000 { diff --git a/target/linux/mediatek/patches-6.18/170-arm64-dts-mediatek-mt7988a-bpi-r4-allow-hw-variants-.patch b/target/linux/mediatek/patches-6.18/170-arm64-dts-mediatek-mt7988a-bpi-r4-allow-hw-variants-.patch deleted file mode 100644 index 6216f59cfd..0000000000 --- a/target/linux/mediatek/patches-6.18/170-arm64-dts-mediatek-mt7988a-bpi-r4-allow-hw-variants-.patch +++ /dev/null @@ -1,876 +0,0 @@ -From df3c7a5128f88e658bd4519154d5e896519e740a Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 22 Apr 2025 15:24:25 +0200 -Subject: [PATCH 27/32] arm64: dts: mediatek: mt7988a-bpi-r4: allow hw variants - of bpi-r4 - -Sinovoip has released other variants of Bananapi-R4 board. -The known changes affecting only the LAN SFP+ slot which is replaced -by a 2.5G phy with optional PoE. - -Just move the common parts to a new dtsi and keep differences (only -i2c for lan-sfp) in dts. - -Signed-off-by: Frank Wunderlich -Acked-by: Krzysztof Kozlowski -Reviewed-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/Makefile | 6 + - .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts | 11 + - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 400 +----------------- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 399 +++++++++++++++++ - 4 files changed, 421 insertions(+), 395 deletions(-) - create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts - create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi - ---- a/arch/arm64/boot/dts/mediatek/Makefile -+++ b/arch/arm64/boot/dts/mediatek/Makefile -@@ -21,6 +21,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-b - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo - dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb -@@ -90,3 +93,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pu - # Device tree overlays support - DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@ - DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini := -@ -+DTC_FLAGS_mt7988a-bananapi-bpi-r4 := -@ -+DTC_FLAGS_mt7988a-bananapi-bpi-r4-2g5 := -@ -+DTC_FLAGS_mt8395-radxa-nio-12l := -@ ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts -@@ -0,0 +1,11 @@ -+// SPDX-License-Identifier: GPL-2.0-only OR MIT -+ -+/dts-v1/; -+ -+#include "mt7988a-bananapi-bpi-r4.dtsi" -+ -+/ { -+ compatible = "bananapi,bpi-r4-2g5", "bananapi,bpi-r4", "mediatek,mt7988a"; -+ model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)"; -+ chassis-type = "embedded"; -+}; ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -2,408 +2,18 @@ - - /dts-v1/; - --#include --#include -- --#include "mt7988a.dtsi" -+#include "mt7988a-bananapi-bpi-r4.dtsi" - - / { - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; -- model = "Banana Pi BPI-R4"; -+ model = "Banana Pi BPI-R4 (2x SFP+)"; - chassis-type = "embedded"; -- -- chosen { -- stdout-path = "serial0:115200n8"; -- }; -- -- reg_1p8v: regulator-1p8v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-1.8V"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-boot-on; -- regulator-always-on; -- }; -- -- reg_3p3v: regulator-3p3v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-3.3V"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-boot-on; -- regulator-always-on; -- }; - }; - --&cpu0 { -- proc-supply = <&rt5190_buck3>; --}; -- --&cpu1 { -- proc-supply = <&rt5190_buck3>; --}; -- --&cpu2 { -- proc-supply = <&rt5190_buck3>; --}; -- --&cpu3 { -- proc-supply = <&rt5190_buck3>; --}; -- --&cpu_thermal { -- trips { -- cpu_trip_hot: hot { -- temperature = <120000>; -- hysteresis = <2000>; -- type = "hot"; -- }; -- -- cpu_trip_active_high: active-high { -- temperature = <115000>; -- hysteresis = <2000>; -- type = "active"; -- }; -- -- cpu_trip_active_med: active-med { -- temperature = <85000>; -- hysteresis = <2000>; -- type = "active"; -- }; -- -- cpu_trip_active_low: active-low { -- temperature = <40000>; -- hysteresis = <2000>; -- type = "active"; -- }; -- }; --}; -- --&i2c0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c0_pins>; -- status = "okay"; -- -- rt5190a_64: rt5190a@64 { -- compatible = "richtek,rt5190a"; -- reg = <0x64>; -- vin2-supply = <&rt5190_buck1>; -- vin3-supply = <&rt5190_buck1>; -- vin4-supply = <&rt5190_buck1>; -- -- regulators { -- rt5190_buck1: buck1 { -- regulator-name = "rt5190a-buck1"; -- regulator-min-microvolt = <5090000>; -- regulator-max-microvolt = <5090000>; -- regulator-allowed-modes = -- , ; -- regulator-boot-on; -- regulator-always-on; -- }; -- buck2 { -- regulator-name = "vcore"; -- regulator-min-microvolt = <600000>; -- regulator-max-microvolt = <1400000>; -- regulator-boot-on; -- regulator-always-on; -- }; -- rt5190_buck3: buck3 { -- regulator-name = "vproc"; -- regulator-min-microvolt = <600000>; -- regulator-max-microvolt = <1400000>; -- regulator-boot-on; -- }; -- buck4 { -- regulator-name = "rt5190a-buck4"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-allowed-modes = -- , ; -- regulator-boot-on; -- regulator-always-on; -- }; -- ldo { -- regulator-name = "rt5190a-ldo"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-boot-on; -- regulator-always-on; -- }; -- }; -- }; --}; -- --&i2c2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c2_1_pins>; -- status = "okay"; -- -- pca9545: i2c-mux@70 { -- compatible = "nxp,pca9545"; -- reg = <0x70>; -- reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; -+&pca9545 { -+ i2c_sfp2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; -- -- i2c@0 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0>; -- -- pcf8563: rtc@51 { -- compatible = "nxp,pcf8563"; -- reg = <0x51>; -- #clock-cells = <0>; -- }; -- -- eeprom@57 { -- compatible = "atmel,24c02"; -- reg = <0x57>; -- size = <256>; -- }; -- -- }; -- -- i2c_sfp1: i2c@1 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <1>; -- }; -- -- i2c_sfp2: i2c@2 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <2>; -- }; -- }; --}; -- --/* mPCIe SIM2 */ --&pcie0 { -- status = "okay"; --}; -- --/* mPCIe SIM3 */ --&pcie1 { -- status = "okay"; --}; -- --/* M.2 key-B SIM1 */ --&pcie2 { -- status = "okay"; --}; -- --/* M.2 key-M SSD */ --&pcie3 { -- status = "okay"; --}; -- --&pio { -- mdio0_pins: mdio0-pins { -- mux { -- function = "eth"; -- groups = "mdc_mdio0"; -- }; -- -- conf { -- pins = "SMI_0_MDC", "SMI_0_MDIO"; -- drive-strength = <8>; -- }; -- }; -- -- i2c0_pins: i2c0-g0-pins { -- mux { -- function = "i2c"; -- groups = "i2c0_1"; -- }; -- }; -- -- i2c1_pins: i2c1-g0-pins { -- mux { -- function = "i2c"; -- groups = "i2c1_0"; -- }; -- }; -- -- i2c1_sfp_pins: i2c1-sfp-g0-pins { -- mux { -- function = "i2c"; -- groups = "i2c1_sfp"; -- }; -- }; -- -- i2c2_0_pins: i2c2-g0-pins { -- mux { -- function = "i2c"; -- groups = "i2c2_0"; -- }; -+ reg = <2>; - }; -- -- i2c2_1_pins: i2c2-g1-pins { -- mux { -- function = "i2c"; -- groups = "i2c2_1"; -- }; -- }; -- -- gbe0_led0_pins: gbe0-led0-pins { -- mux { -- function = "led"; -- groups = "gbe0_led0"; -- }; -- }; -- -- gbe1_led0_pins: gbe1-led0-pins { -- mux { -- function = "led"; -- groups = "gbe1_led0"; -- }; -- }; -- -- gbe2_led0_pins: gbe2-led0-pins { -- mux { -- function = "led"; -- groups = "gbe2_led0"; -- }; -- }; -- -- gbe3_led0_pins: gbe3-led0-pins { -- mux { -- function = "led"; -- groups = "gbe3_led0"; -- }; -- }; -- -- gbe0_led1_pins: gbe0-led1-pins { -- mux { -- function = "led"; -- groups = "gbe0_led1"; -- }; -- }; -- -- gbe1_led1_pins: gbe1-led1-pins { -- mux { -- function = "led"; -- groups = "gbe1_led1"; -- }; -- }; -- -- gbe2_led1_pins: gbe2-led1-pins { -- mux { -- function = "led"; -- groups = "gbe2_led1"; -- }; -- }; -- -- gbe3_led1_pins: gbe3-led1-pins { -- mux { -- function = "led"; -- groups = "gbe3_led1"; -- }; -- }; -- -- i2p5gbe_led0_pins: 2p5gbe-led0-pins { -- mux { -- function = "led"; -- groups = "2p5gbe_led0"; -- }; -- }; -- -- i2p5gbe_led1_pins: 2p5gbe-led1-pins { -- mux { -- function = "led"; -- groups = "2p5gbe_led1"; -- }; -- }; -- -- mmc0_pins_emmc_45: mmc0-emmc-45-pins { -- mux { -- function = "flash"; -- groups = "emmc_45"; -- }; -- }; -- -- mmc0_pins_emmc_51: mmc0-emmc-51-pins { -- mux { -- function = "flash"; -- groups = "emmc_51"; -- }; -- }; -- -- mmc0_pins_sdcard: mmc0-sdcard-pins { -- mux { -- function = "flash"; -- groups = "sdcard"; -- }; -- }; -- -- uart0_pins: uart0-pins { -- mux { -- function = "uart"; -- groups = "uart0"; -- }; -- }; -- -- snfi_pins: snfi-pins { -- mux { -- function = "flash"; -- groups = "snfi"; -- }; -- }; -- -- spi0_pins: spi0-pins { -- mux { -- function = "spi"; -- groups = "spi0"; -- }; -- }; -- -- spi0_flash_pins: spi0-flash-pins { -- mux { -- function = "spi"; -- groups = "spi0", "spi0_wp_hold"; -- }; -- }; -- -- spi1_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1"; -- }; -- }; -- -- spi2_pins: spi2-pins { -- mux { -- function = "spi"; -- groups = "spi2"; -- }; -- }; -- -- spi2_flash_pins: spi2-flash-pins { -- mux { -- function = "spi"; -- groups = "spi2", "spi2_wp_hold"; -- }; -- }; --}; -- --&pwm { -- status = "okay"; --}; -- --&serial0 { -- status = "okay"; --}; -- --&ssusb1 { -- status = "okay"; --}; -- --&tphy { -- status = "okay"; --}; -- --&watchdog { -- status = "okay"; - }; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -0,0 +1,399 @@ -+// SPDX-License-Identifier: GPL-2.0-only OR MIT -+ -+/dts-v1/; -+ -+#include -+#include -+ -+#include "mt7988a.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-1.8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+&cpu0 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu1 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu2 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu3 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu_thermal { -+ trips { -+ cpu_trip_hot: hot { -+ temperature = <120000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ -+ cpu_trip_active_high: active-high { -+ temperature = <115000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_active_med: active-med { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_active_low: active-low { -+ temperature = <40000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ status = "okay"; -+ -+ rt5190a_64: rt5190a@64 { -+ compatible = "richtek,rt5190a"; -+ reg = <0x64>; -+ vin2-supply = <&rt5190_buck1>; -+ vin3-supply = <&rt5190_buck1>; -+ vin4-supply = <&rt5190_buck1>; -+ -+ regulators { -+ rt5190_buck1: buck1 { -+ regulator-name = "rt5190a-buck1"; -+ regulator-min-microvolt = <5090000>; -+ regulator-max-microvolt = <5090000>; -+ regulator-allowed-modes = -+ , ; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ buck2 { -+ regulator-name = "vcore"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ rt5190_buck3: buck3 { -+ regulator-name = "vproc"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ }; -+ buck4 { -+ regulator-name = "rt5190a-buck4"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-allowed-modes = -+ , ; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ ldo { -+ regulator-name = "rt5190a-ldo"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_1_pins>; -+ status = "okay"; -+ -+ pca9545: i2c-mux@70 { -+ compatible = "nxp,pca9545"; -+ reg = <0x70>; -+ reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ -+ pcf8563: rtc@51 { -+ compatible = "nxp,pcf8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ }; -+ -+ eeprom@57 { -+ compatible = "atmel,24c02"; -+ reg = <0x57>; -+ size = <256>; -+ }; -+ -+ }; -+ -+ i2c_sfp1: i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ }; -+ }; -+}; -+ -+/* mPCIe SIM2 */ -+&pcie0 { -+ status = "okay"; -+}; -+ -+/* mPCIe SIM3 */ -+&pcie1 { -+ status = "okay"; -+}; -+ -+/* M.2 key-B SIM1 */ -+&pcie2 { -+ status = "okay"; -+}; -+ -+/* M.2 key-M SSD */ -+&pcie3 { -+ status = "okay"; -+}; -+ -+&pio { -+ mdio0_pins: mdio0-pins { -+ mux { -+ function = "eth"; -+ groups = "mdc_mdio0"; -+ }; -+ -+ conf { -+ pins = "SMI_0_MDC", "SMI_0_MDIO"; -+ drive-strength = <8>; -+ }; -+ }; -+ -+ i2c0_pins: i2c0-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c0_1"; -+ }; -+ }; -+ -+ i2c1_pins: i2c1-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c1_0"; -+ }; -+ }; -+ -+ i2c1_sfp_pins: i2c1-sfp-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c1_sfp"; -+ }; -+ }; -+ -+ i2c2_0_pins: i2c2-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c2_0"; -+ }; -+ }; -+ -+ i2c2_1_pins: i2c2-g1-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c2_1"; -+ }; -+ }; -+ -+ gbe0_led0_pins: gbe0-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe0_led0"; -+ }; -+ }; -+ -+ gbe1_led0_pins: gbe1-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe1_led0"; -+ }; -+ }; -+ -+ gbe2_led0_pins: gbe2-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe2_led0"; -+ }; -+ }; -+ -+ gbe3_led0_pins: gbe3-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe3_led0"; -+ }; -+ }; -+ -+ gbe0_led1_pins: gbe0-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe0_led1"; -+ }; -+ }; -+ -+ gbe1_led1_pins: gbe1-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe1_led1"; -+ }; -+ }; -+ -+ gbe2_led1_pins: gbe2-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe2_led1"; -+ }; -+ }; -+ -+ gbe3_led1_pins: gbe3-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe3_led1"; -+ }; -+ }; -+ -+ i2p5gbe_led0_pins: 2p5gbe-led0-pins { -+ mux { -+ function = "led"; -+ groups = "2p5gbe_led0"; -+ }; -+ }; -+ -+ i2p5gbe_led1_pins: 2p5gbe-led1-pins { -+ mux { -+ function = "led"; -+ groups = "2p5gbe_led1"; -+ }; -+ }; -+ -+ mmc0_pins_emmc_45: mmc0-emmc-45-pins { -+ mux { -+ function = "flash"; -+ groups = "emmc_45"; -+ }; -+ }; -+ -+ mmc0_pins_emmc_51: mmc0-emmc-51-pins { -+ mux { -+ function = "flash"; -+ groups = "emmc_51"; -+ }; -+ }; -+ -+ mmc0_pins_sdcard: mmc0-sdcard-pins { -+ mux { -+ function = "flash"; -+ groups = "sdcard"; -+ }; -+ }; -+ -+ uart0_pins: uart0-pins { -+ mux { -+ function = "uart"; -+ groups = "uart0"; -+ }; -+ }; -+ -+ snfi_pins: snfi-pins { -+ mux { -+ function = "flash"; -+ groups = "snfi"; -+ }; -+ }; -+ -+ spi0_pins: spi0-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0"; -+ }; -+ }; -+ -+ spi0_flash_pins: spi0-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spi1_pins: spi1-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1"; -+ }; -+ }; -+ -+ spi2_pins: spi2-pins { -+ mux { -+ function = "spi"; -+ groups = "spi2"; -+ }; -+ }; -+ -+ spi2_flash_pins: spi2-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi2", "spi2_wp_hold"; -+ }; -+ }; -+}; -+ -+&pwm { -+ status = "okay"; -+}; -+ -+&serial0 { -+ status = "okay"; -+}; -+ -+&ssusb1 { -+ status = "okay"; -+}; -+ -+&tphy { -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "okay"; -+}; diff --git a/target/linux/mediatek/patches-6.18/171-v6.16-arm64-dts-mediatek-mt7988-Add-xsphy-for-ssusb0-pcie2.patch b/target/linux/mediatek/patches-6.18/171-v6.16-arm64-dts-mediatek-mt7988-Add-xsphy-for-ssusb0-pcie2.patch deleted file mode 100644 index 18f1ddc5bf..0000000000 --- a/target/linux/mediatek/patches-6.18/171-v6.16-arm64-dts-mediatek-mt7988-Add-xsphy-for-ssusb0-pcie2.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 2400b24dfecea9a628f63089bf7eeb9a43b91021 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 22 Apr 2025 15:24:30 +0200 -Subject: [PATCH 28/32] arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2 - -First usb and third pcie controller on mt7988 need a xs-phy to work -properly. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20250422132438.15735-8-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 36 +++++++++++++++++++++++ - 1 file changed, 36 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -334,6 +334,8 @@ - <&infracfg CLK_INFRA_133M_USB_HCK>, - <&infracfg CLK_INFRA_USB_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; -+ phys = <&xphyu2port0 PHY_TYPE_USB2>, -+ <&xphyu3port0 PHY_TYPE_USB3>; - status = "disabled"; - }; - -@@ -398,6 +400,9 @@ - pinctrl-0 = <&pcie2_pins>; - status = "disabled"; - -+ phys = <&xphyu3port0 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc2 0>, -@@ -548,6 +553,37 @@ - }; - }; - -+ -+ topmisc: system-controller@11d10084 { -+ compatible = "mediatek,mt7988-topmisc", -+ "syscon"; -+ reg = <0 0x11d10084 0 0xff80>; -+ }; -+ -+ xs-phy@11e10000 { -+ compatible = "mediatek,mt7988-xsphy", -+ "mediatek,xsphy"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ xphyu2port0: usb-phy@11e10000 { -+ reg = <0 0x11e10000 0 0x400>; -+ clocks = <&infracfg CLK_INFRA_USB_UTMI>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ }; -+ -+ xphyu3port0: usb-phy@11e13000 { -+ reg = <0 0x11e13400 0 0x500>; -+ clocks = <&infracfg CLK_INFRA_USB_PIPE>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ mediatek,syscon-type = <&topmisc 0x194 0>; -+ }; -+ }; -+ - clock-controller@11f40000 { - compatible = "mediatek,mt7988-xfi-pll"; - reg = <0 0x11f40000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.18/172-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch b/target/linux/mediatek/patches-6.18/172-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch deleted file mode 100644 index d02bca2b4e..0000000000 --- a/target/linux/mediatek/patches-6.18/172-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch +++ /dev/null @@ -1,37 +0,0 @@ -From bb5872c4b6cb0a8687b424b9970b2c3cca2ededd Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 22 Apr 2025 15:24:31 +0200 -Subject: [PATCH 29/32] arm64: dts: mediatek: mt7988a-bpi-r4: enable xsphy - -Enable XS-Phy on Bananapi R4 for pcie2. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20250422132438.15735-9-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -397,3 +397,7 @@ - &watchdog { - status = "okay"; - }; -+ -+&xsphy { -+ status = "okay"; -+}; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -560,7 +560,7 @@ - reg = <0 0x11d10084 0 0xff80>; - }; - -- xs-phy@11e10000 { -+ xsphy: xs-phy@11e10000 { - compatible = "mediatek,mt7988-xsphy", - "mediatek,xsphy"; - #address-cells = <2>; diff --git a/target/linux/mediatek/patches-6.18/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch b/target/linux/mediatek/patches-6.18/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch index 698f821314..bbc18bb123 100644 --- a/target/linux/mediatek/patches-6.18/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch +++ b/target/linux/mediatek/patches-6.18/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch @@ -12,7 +12,7 @@ Signed-off-by: Sky Huang --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -322,6 +322,12 @@ +@@ -418,6 +418,12 @@ nvmem-cell-names = "lvts-calib-data-1"; }; diff --git a/target/linux/mediatek/patches-6.18/174-v6.16-arm64-dts-mediatek-mt7988-add-spi-controllers.patch b/target/linux/mediatek/patches-6.18/174-v6.16-arm64-dts-mediatek-mt7988-add-spi-controllers.patch deleted file mode 100644 index d634671ab5..0000000000 --- a/target/linux/mediatek/patches-6.18/174-v6.16-arm64-dts-mediatek-mt7988-add-spi-controllers.patch +++ /dev/null @@ -1,69 +0,0 @@ -From bf7c2ce439ca811dc1697b4bc19ab57bd8f13be3 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 16 May 2025 20:01:35 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988: add spi controllers - -Add SPI controllers for mt7988. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20250516180147.10416-6-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 45 +++++++++++++++++++++++ - 1 file changed, 45 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -311,6 +311,51 @@ - status = "disabled"; - }; - -+ spi0: spi@11007000 { -+ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; -+ reg = <0 0x11007000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPI_SEL>, -+ <&infracfg CLK_INFRA_104M_SPI0>, -+ <&infracfg CLK_INFRA_66M_SPI0_HCK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", -+ "hclk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@11008000 { -+ compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm"; -+ reg = <0 0x11008000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPIM_MST_SEL>, -+ <&infracfg CLK_INFRA_104M_SPI1>, -+ <&infracfg CLK_INFRA_66M_SPI1_HCK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", -+ "hclk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi2: spi@11009000 { -+ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; -+ reg = <0 0x11009000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPI_SEL>, -+ <&infracfg CLK_INFRA_104M_SPI2_BCK>, -+ <&infracfg CLK_INFRA_66M_SPI2_HCK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", -+ "hclk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - lvts: lvts@1100a000 { - compatible = "mediatek,mt7988-lvts-ap"; - #thermal-sensor-cells = <1>; diff --git a/target/linux/mediatek/patches-6.18/175-v6.16-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-t.patch b/target/linux/mediatek/patches-6.18/175-v6.16-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-t.patch deleted file mode 100644 index 54d829c7d9..0000000000 --- a/target/linux/mediatek/patches-6.18/175-v6.16-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-t.patch +++ /dev/null @@ -1,90 +0,0 @@ -From b9ebd166b006f77cef4530b4bf4a291a112da4f2 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 16 May 2025 20:01:36 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988: move uart0 and spi1 pins to soc - dtsi - -In order to use uart0 or spi1 there is only 1 possible pin definition -so move them to soc dtsi to reuse them in other boards and avoiding -conflict if defined twice. - -Suggested-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20250516180147.10416-7-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 14 -------------- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 18 ++++++++++++++++++ - 2 files changed, 18 insertions(+), 14 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -328,13 +328,6 @@ - }; - }; - -- uart0_pins: uart0-pins { -- mux { -- function = "uart"; -- groups = "uart0"; -- }; -- }; -- - snfi_pins: snfi-pins { - mux { - function = "flash"; -@@ -356,13 +349,6 @@ - }; - }; - -- spi1_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1"; -- }; -- }; -- - spi2_pins: spi2-pins { - mux { - function = "spi"; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -209,6 +209,20 @@ - "pcie_wake_n3_0"; - }; - }; -+ -+ spi1_pins: spi1-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1"; -+ }; -+ }; -+ -+ uart0_pins: uart0-pins { -+ mux { -+ function = "uart"; -+ groups = "uart0"; -+ }; -+ }; - }; - - pwm: pwm@10048000 { -@@ -244,6 +258,8 @@ - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_52M_UART0_CK>; - clock-names = "baud", "bus"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; - status = "disabled"; - }; - -@@ -338,6 +354,8 @@ - "hclk"; - #address-cells = <1>; - #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; - status = "disabled"; - }; - diff --git a/target/linux/mediatek/patches-6.18/176-v6.17-arm64-dts-mediatek-mt7988-add-cci-node.patch b/target/linux/mediatek/patches-6.18/176-v6.17-arm64-dts-mediatek-mt7988-add-cci-node.patch deleted file mode 100644 index 42a4aed2e2..0000000000 --- a/target/linux/mediatek/patches-6.18/176-v6.17-arm64-dts-mediatek-mt7988-add-cci-node.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 0cbdb6d04689f8c05074e348c8e0a42b229ef9a3 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 6 Jul 2025 15:22:03 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988: add cci node - -Add cci devicetree node for cpu frequency scaling. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20250706132213.20412-9-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++ - 1 file changed, 33 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -12,6 +12,35 @@ - #address-cells = <2>; - #size-cells = <2>; - -+ cci: cci { -+ compatible = "mediatek,mt7988-cci", "mediatek,mt8183-cci"; -+ clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, -+ <&topckgen CLK_TOP_XTAL>; -+ clock-names = "cci", "intermediate"; -+ operating-points-v2 = <&cci_opp>; -+ }; -+ -+ cci_opp: opp-table-cci { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ opp-480000000 { -+ opp-hz = /bits/ 64 <480000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-660000000 { -+ opp-hz = /bits/ 64 <660000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-900000000 { -+ opp-hz = /bits/ 64 <900000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-1080000000 { -+ opp-hz = /bits/ 64 <1080000000>; -+ opp-microvolt = <900000>; -+ }; -+ }; -+ - cpus { - #address-cells = <1>; - #size-cells = <0>; -@@ -25,6 +54,7 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ mediatek,cci = <&cci>; - }; - - cpu1: cpu@1 { -@@ -36,6 +66,7 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ mediatek,cci = <&cci>; - }; - - cpu2: cpu@2 { -@@ -47,6 +78,7 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ mediatek,cci = <&cci>; - }; - - cpu3: cpu@3 { -@@ -58,6 +90,7 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ mediatek,cci = <&cci>; - }; - - cluster0_opp: opp-table-0 { diff --git a/target/linux/mediatek/patches-6.18/177-v6.16-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-.patch b/target/linux/mediatek/patches-6.18/177-v6.16-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-.patch deleted file mode 100644 index b657e221f6..0000000000 --- a/target/linux/mediatek/patches-6.18/177-v6.16-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-.patch +++ /dev/null @@ -1,42 +0,0 @@ -From e4950b016c727feb0c39ad12cfcb6182c9ef3814 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 16 May 2025 20:01:38 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988: add phy calibration efuse - subnodes - -MT7988 contains buildin mt753x switch which needs calibration data from -efuse. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20250516180147.10416-9-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -702,6 +702,22 @@ - lvts_calibration: calib@918 { - reg = <0x918 0x28>; - }; -+ -+ phy_calibration_p0: calib@940 { -+ reg = <0x940 0x10>; -+ }; -+ -+ phy_calibration_p1: calib@954 { -+ reg = <0x954 0x10>; -+ }; -+ -+ phy_calibration_p2: calib@968 { -+ reg = <0x968 0x10>; -+ }; -+ -+ phy_calibration_p3: calib@97c { -+ reg = <0x97c 0x10>; -+ }; - }; - - clock-controller@15000000 { diff --git a/target/linux/mediatek/patches-6.18/178-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch b/target/linux/mediatek/patches-6.18/178-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch deleted file mode 100644 index 15c8ad7ea0..0000000000 --- a/target/linux/mediatek/patches-6.18/178-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch +++ /dev/null @@ -1,213 +0,0 @@ -From patchwork Sun May 11 14:19:24 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084161 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 08/14] arm64: dts: mediatek: mt7988: add basic - ethernet-nodes -Date: Sun, 11 May 2025 16:19:24 +0200 -Message-ID: <20250511141942.10284-9-linux@fw-web.de> -X-Mailer: git-send-email 2.43.0 -In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> -References: <20250511141942.10284-1-linux@fw-web.de> -MIME-Version: 1.0 -X-Mail-ID: 5c8e73b6-e2d6-4898-90c0-375604707c20 -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -From: Frank Wunderlich - -Add basic ethernet related nodes. - -Mac1+2 needs pcs (sgmii+usxgmii) to work correctly which will be linked -later when driver is merged. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 124 +++++++++++++++++++++- - 1 file changed, 121 insertions(+), 3 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -686,7 +686,28 @@ - }; - }; - -- clock-controller@11f40000 { -+ xfi_tphy0: phy@11f20000 { -+ compatible = "mediatek,mt7988-xfi-tphy"; -+ reg = <0 0x11f20000 0 0x10000>; -+ resets = <&watchdog 14>; -+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, -+ <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; -+ clock-names = "xfipll", "topxtal"; -+ mediatek,usxgmii-performance-errata; -+ #phy-cells = <0>; -+ }; -+ -+ xfi_tphy1: phy@11f30000 { -+ compatible = "mediatek,mt7988-xfi-tphy"; -+ reg = <0 0x11f30000 0 0x10000>; -+ resets = <&watchdog 15>; -+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, -+ <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>; -+ clock-names = "xfipll", "topxtal"; -+ #phy-cells = <0>; -+ }; -+ -+ xfi_pll: clock-controller@11f40000 { - compatible = "mediatek,mt7988-xfi-pll"; - reg = <0 0x11f40000 0 0x1000>; - resets = <&watchdog 16>; -@@ -720,19 +741,116 @@ - }; - }; - -- clock-controller@15000000 { -+ ethsys: clock-controller@15000000 { - compatible = "mediatek,mt7988-ethsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -- clock-controller@15031000 { -+ ethwarp: clock-controller@15031000 { - compatible = "mediatek,mt7988-ethwarp"; - reg = <0 0x15031000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; -+ -+ eth: ethernet@15100000 { -+ compatible = "mediatek,mt7988-eth"; -+ reg = <0 0x15100000 0 0x80000>, -+ <0 0x15400000 0 0x200000>; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <ðsys CLK_ETHDMA_CRYPT0_EN>, -+ <ðsys CLK_ETHDMA_FE_EN>, -+ <ðsys CLK_ETHDMA_GP2_EN>, -+ <ðsys CLK_ETHDMA_GP1_EN>, -+ <ðsys CLK_ETHDMA_GP3_EN>, -+ <ðwarp CLK_ETHWARP_WOCPU2_EN>, -+ <ðwarp CLK_ETHWARP_WOCPU1_EN>, -+ <ðwarp CLK_ETHWARP_WOCPU0_EN>, -+ <ðsys CLK_ETHDMA_ESW_EN>, -+ <&topckgen CLK_TOP_ETH_GMII_SEL>, -+ <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, -+ <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, -+ <&topckgen CLK_TOP_ETH_SYS_SEL>, -+ <&topckgen CLK_TOP_ETH_XGMII_SEL>, -+ <&topckgen CLK_TOP_ETH_MII_SEL>, -+ <&topckgen CLK_TOP_NETSYS_SEL>, -+ <&topckgen CLK_TOP_NETSYS_500M_SEL>, -+ <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, -+ <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, -+ <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, -+ <&topckgen CLK_TOP_NETSYS_WARP_SEL>, -+ <ðsys CLK_ETHDMA_XGP1_EN>, -+ <ðsys CLK_ETHDMA_XGP2_EN>, -+ <ðsys CLK_ETHDMA_XGP3_EN>; -+ clock-names = "crypto", "fe", "gp2", "gp1", -+ "gp3", -+ "ethwarp_wocpu2", "ethwarp_wocpu1", -+ "ethwarp_wocpu0", "esw", "top_eth_gmii_sel", -+ "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", -+ "top_eth_sys_sel", "top_eth_xgmii_sel", -+ "top_eth_mii_sel", "top_netsys_sel", -+ "top_netsys_500m_sel", "top_netsys_pao_2x_sel", -+ "top_netsys_sync_250m_sel", -+ "top_netsys_ppefb_250m_sel", -+ "top_netsys_warp_sel","xgp1", "xgp2", "xgp3"; -+ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, -+ <&topckgen CLK_TOP_NETSYS_GSW_SEL>, -+ <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, -+ <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, -+ <&topckgen CLK_TOP_SGM_0_SEL>, -+ <&topckgen CLK_TOP_SGM_1_SEL>; -+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, -+ <&topckgen CLK_TOP_NET1PLL_D4>, -+ <&topckgen CLK_TOP_NET1PLL_D8_D4>, -+ <&topckgen CLK_TOP_NET1PLL_D8_D4>, -+ <&apmixedsys CLK_APMIXED_SGMPLL>, -+ <&apmixedsys CLK_APMIXED_SGMPLL>; -+ mediatek,ethsys = <ðsys>; -+ mediatek,infracfg = <&topmisc>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gmac0: mac@0 { -+ compatible = "mediatek,eth-mac"; -+ reg = <0>; -+ phy-mode = "internal"; -+ -+ fixed-link { -+ speed = <10000>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ -+ gmac1: mac@1 { -+ compatible = "mediatek,eth-mac"; -+ reg = <1>; -+ status = "disabled"; -+ }; -+ -+ gmac2: mac@2 { -+ compatible = "mediatek,eth-mac"; -+ reg = <2>; -+ status = "disabled"; -+ }; -+ -+ mdio_bus: mdio-bus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* internal 2.5G PHY */ -+ int_2p5g_phy: ethernet-phy@f { -+ reg = <15>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ phy-mode = "internal"; -+ }; -+ }; -+ }; - }; - - thermal-zones { diff --git a/target/linux/mediatek/patches-6.18/179-arm64-dts-mediatek-mt7988-add-switch-node.patch b/target/linux/mediatek/patches-6.18/179-arm64-dts-mediatek-mt7988-add-switch-node.patch deleted file mode 100644 index de43734c26..0000000000 --- a/target/linux/mediatek/patches-6.18/179-arm64-dts-mediatek-mt7988-add-switch-node.patch +++ /dev/null @@ -1,228 +0,0 @@ -From patchwork Sun May 11 14:19:25 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084123 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 09/14] arm64: dts: mediatek: mt7988: add switch node -Date: Sun, 11 May 2025 16:19:25 +0200 -Message-ID: <20250511141942.10284-10-linux@fw-web.de> -X-Mailer: git-send-email 2.43.0 -In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> -References: <20250511141942.10284-1-linux@fw-web.de> -MIME-Version: 1.0 -X-Mail-ID: a24ecea1-b7fd-4cb4-a93d-b29036e2e6ac -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -From: Frank Wunderlich - -Add mt7988 builtin mt753x switch nodes. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 166 ++++++++++++++++++++++ - 1 file changed, 166 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -5,6 +5,7 @@ - #include - #include - #include -+#include - - / { - compatible = "mediatek,mt7988a"; -@@ -748,6 +749,159 @@ - #reset-cells = <1>; - }; - -+ switch: switch@15020000 { -+ compatible = "mediatek,mt7988-switch"; -+ reg = <0 0x15020000 0 0x8000>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gsw_port0: port@0 { -+ reg = <0>; -+ phy-mode = "internal"; -+ phy-handle = <&gsw_phy0>; -+ }; -+ -+ gsw_port1: port@1 { -+ reg = <1>; -+ phy-mode = "internal"; -+ phy-handle = <&gsw_phy1>; -+ }; -+ -+ gsw_port2: port@2 { -+ reg = <2>; -+ phy-mode = "internal"; -+ phy-handle = <&gsw_phy2>; -+ }; -+ -+ gsw_port3: port@3 { -+ reg = <3>; -+ phy-mode = "internal"; -+ phy-handle = <&gsw_phy3>; -+ }; -+ -+ port@6 { -+ reg = <6>; -+ ethernet = <&gmac0>; -+ phy-mode = "internal"; -+ -+ fixed-link { -+ speed = <10000>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ }; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ mediatek,pio = <&pio>; -+ -+ gsw_phy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ interrupts = <0>; -+ phy-mode = "internal"; -+ nvmem-cells = <&phy_calibration_p0>; -+ nvmem-cell-names = "phy-cal-data"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gsw_phy0_led0: led@0 { -+ reg = <0>; -+ status = "disabled"; -+ }; -+ -+ gsw_phy0_led1: led@1 { -+ reg = <1>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ gsw_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ interrupts = <1>; -+ phy-mode = "internal"; -+ nvmem-cells = <&phy_calibration_p1>; -+ nvmem-cell-names = "phy-cal-data"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gsw_phy1_led0: led@0 { -+ reg = <0>; -+ status = "disabled"; -+ }; -+ -+ gsw_phy1_led1: led@1 { -+ reg = <1>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ gsw_phy2: ethernet-phy@2 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <2>; -+ interrupts = <2>; -+ phy-mode = "internal"; -+ nvmem-cells = <&phy_calibration_p2>; -+ nvmem-cell-names = "phy-cal-data"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gsw_phy2_led0: led@0 { -+ reg = <0>; -+ status = "disabled"; -+ }; -+ -+ gsw_phy2_led1: led@1 { -+ reg = <1>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ gsw_phy3: ethernet-phy@3 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <3>; -+ interrupts = <3>; -+ phy-mode = "internal"; -+ nvmem-cells = <&phy_calibration_p3>; -+ nvmem-cell-names = "phy-cal-data"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gsw_phy3_led0: led@0 { -+ reg = <0>; -+ status = "disabled"; -+ }; -+ -+ gsw_phy3_led1: led@1 { -+ reg = <1>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ }; -+ }; -+ - ethwarp: clock-controller@15031000 { - compatible = "mediatek,mt7988-ethwarp"; - reg = <0 0x15031000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.18/180-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolin.patch b/target/linux/mediatek/patches-6.18/180-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolin.patch deleted file mode 100644 index 9b616cebd1..0000000000 --- a/target/linux/mediatek/patches-6.18/180-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolin.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 0f63e96e2ab422d1d35def1da75d3df299bf503e Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 16 May 2025 20:01:41 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and coolingmaps - -Add Fan and cooling maps for Bananapi-R4 board. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20250516180147.10416-12-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 29 +++++++++++++++++++ - 1 file changed, 29 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -12,6 +12,15 @@ - stdout-path = "serial0:115200n8"; - }; - -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */ -+ cooling-levels = <0 80 128 255>; -+ #cooling-cells = <2>; -+ pwms = <&pwm 0 50000>; -+ status = "okay"; -+ }; -+ - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; -@@ -73,6 +82,26 @@ - type = "active"; - }; - }; -+ -+ cooling-maps { -+ map-cpu-active-high { -+ /* active: set fan to cooling level 2 */ -+ cooling-device = <&fan 3 3>; -+ trip = <&cpu_trip_active_high>; -+ }; -+ -+ map-cpu-active-med { -+ /* active: set fan to cooling level 1 */ -+ cooling-device = <&fan 2 2>; -+ trip = <&cpu_trip_active_med>; -+ }; -+ -+ map-cpu-active-low { -+ /* active: set fan to cooling level 0 */ -+ cooling-device = <&fan 1 1>; -+ trip = <&cpu_trip_active_low>; -+ }; -+ }; - }; - - &i2c0 { diff --git a/target/linux/mediatek/patches-6.18/181-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-node.patch b/target/linux/mediatek/patches-6.18/181-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-node.patch deleted file mode 100644 index cffc02226b..0000000000 --- a/target/linux/mediatek/patches-6.18/181-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-node.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 6b7642e9d095d33d8034b8b396a2de9e5ecb25a7 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 16 May 2025 20:01:42 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988a-bpi-r4: configure spi-nodes - -Configure and enable SPI nodes on Bananapi R4 board. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20250516180147.10416-13-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 32 +++++++++++++++++++ - 1 file changed, 32 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -401,6 +401,38 @@ - status = "okay"; - }; - -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_flash_pins>; -+ status = "okay"; -+ -+ spi_nand: flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ }; -+}; -+ -+&spi1 { -+ status = "okay"; -+}; -+ -+&spi_nand { -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x200000>; -+ read-only; -+ }; -+ }; -+}; -+ - &ssusb1 { - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.18/182-v6.17-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-fo.patch b/target/linux/mediatek/patches-6.18/182-v6.17-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-fo.patch deleted file mode 100644 index 68858e76b0..0000000000 --- a/target/linux/mediatek/patches-6.18/182-v6.17-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-fo.patch +++ /dev/null @@ -1,28 +0,0 @@ -From b5a4ad957114b59a74b3e3f598ae0785dd86cd32 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 6 Jul 2025 15:22:06 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci - -CCI requires proc-supply. Add it on board level. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20250706132213.20412-12-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -40,6 +40,10 @@ - }; - }; - -+&cci { -+ proc-supply = <&rt5190_buck3>; -+}; -+ - &cpu0 { - proc-supply = <&rt5190_buck3>; - }; diff --git a/target/linux/mediatek/patches-6.18/183-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-link-to-gmac.patch b/target/linux/mediatek/patches-6.18/183-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-link-to-gmac.patch deleted file mode 100644 index 9861dc0f5b..0000000000 --- a/target/linux/mediatek/patches-6.18/183-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-link-to-gmac.patch +++ /dev/null @@ -1,138 +0,0 @@ -From patchwork Sun May 11 14:26:53 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084128 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 13/14] arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages - and link to gmac -Date: Sun, 11 May 2025 16:26:53 +0200 -Message-ID: <20250511142655.11007-4-frank-w@public-files.de> -X-Mailer: git-send-email 2.43.0 -In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de> -References: <20250511142655.11007-1-frank-w@public-files.de> -MIME-Version: 1.0 -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -Add SFP cages to Bananapi-R4 board. The 2.5g phy variant only contains the -wan-SFP, so add this to common dtsi and the lan-sfp only to the dual-SFP -variant. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts | 11 +++++++++++ - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 18 ++++++++++++++++++ - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 18 ++++++++++++++++++ - 3 files changed, 47 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts -@@ -9,3 +9,14 @@ - model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)"; - chassis-type = "embedded"; - }; -+ -+&gmac1 { -+ phy-mode = "internal"; -+ phy-connection-type = "internal"; -+ phy = <&int_2p5g_phy>; -+}; -+ -+&int_2p5g_phy { -+ pinctrl-names = "i2p5gbe-led"; -+ pinctrl-0 = <&i2p5gbe_led0_pins>; -+}; ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -8,6 +8,24 @@ - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; - model = "Banana Pi BPI-R4 (2x SFP+)"; - chassis-type = "embedded"; -+ -+ /* SFP2 cage (LAN) */ -+ sfp2: sfp2 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp2>; -+ los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>; -+ tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>; -+ tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>; -+ rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>; -+ maximum-power-milliwatt = <3000>; -+ }; -+}; -+ -+&gmac1 { -+ sfp = <&sfp2>; -+ managed = "in-band-status"; -+ phy-mode = "usxgmii"; - }; - - &pca9545 { ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -38,6 +38,18 @@ - regulator-boot-on; - regulator-always-on; - }; -+ -+ /* SFP1 cage (WAN) */ -+ sfp1: sfp1 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp1>; -+ los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; -+ tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; -+ tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; -+ rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; -+ maximum-power-milliwatt = <3000>; -+ }; - }; - - &cci { -@@ -108,6 +120,12 @@ - }; - }; - -+&gmac2 { -+ sfp = <&sfp1>; -+ managed = "in-band-status"; -+ phy-mode = "usxgmii"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; diff --git a/target/linux/mediatek/patches-6.18/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch b/target/linux/mediatek/patches-6.18/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch index 0bdc6c9a15..e253ceb7eb 100644 --- a/target/linux/mediatek/patches-6.18/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch +++ b/target/linux/mediatek/patches-6.18/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch @@ -56,8 +56,8 @@ Signed-off-by: Frank Wunderlich --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -126,6 +126,54 @@ - phy-mode = "usxgmii"; +@@ -214,6 +214,54 @@ + label = "lan3"; }; +&gsw_phy0 { diff --git a/target/linux/mediatek/patches-6.18/185-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch b/target/linux/mediatek/patches-6.18/185-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch index efa2121812..4a9437ff5d 100644 --- a/target/linux/mediatek/patches-6.18/185-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch +++ b/target/linux/mediatek/patches-6.18/185-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch @@ -13,7 +13,7 @@ Signed-off-by: Daniel Golle --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -297,7 +297,7 @@ +@@ -296,7 +296,7 @@ status = "disabled"; }; @@ -22,7 +22,7 @@ Signed-off-by: Daniel Golle compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; reg = <0 0x11000100 0 0x100>; interrupts = ; -@@ -308,7 +308,7 @@ +@@ -307,7 +307,7 @@ status = "disabled"; }; diff --git a/target/linux/mediatek/patches-6.18/186-arm64-dts-mt7988a-complete-dtsi.patch b/target/linux/mediatek/patches-6.18/186-arm64-dts-mt7988a-complete-dtsi.patch index b7c609f0f5..ca5402b75c 100644 --- a/target/linux/mediatek/patches-6.18/186-arm64-dts-mt7988a-complete-dtsi.patch +++ b/target/linux/mediatek/patches-6.18/186-arm64-dts-mt7988a-complete-dtsi.patch @@ -5,7 +5,7 @@ Subject: [PATCH] arm64: dts: mt7988a: complete dtsi Work-in-progress patch to complete mt7988a.dtsi --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -193,7 +193,7 @@ +@@ -192,7 +192,7 @@ }; pio: pinctrl@1001f000 { @@ -14,7 +14,7 @@ Work-in-progress patch to complete mt7988a.dtsi reg = <0 0x1001f000 0 0x1000>, <0 0x11c10000 0 0x1000>, <0 0x11d00000 0 0x1000>, -@@ -212,6 +212,13 @@ +@@ -211,6 +211,13 @@ interrupt-parent = <&gic>; #interrupt-cells = <2>; @@ -28,7 +28,7 @@ Work-in-progress patch to complete mt7988a.dtsi pcie0_pins: pcie0-pins { mux { function = "pcie"; -@@ -278,6 +285,60 @@ +@@ -277,6 +284,60 @@ status = "disabled"; }; @@ -89,7 +89,7 @@ Work-in-progress patch to complete mt7988a.dtsi mcusys: mcusys@100e0000 { compatible = "mediatek,mt7988-mcusys", "syscon"; reg = <0 0x100e0000 0 0x1000>; -@@ -319,6 +380,32 @@ +@@ -318,6 +379,32 @@ status = "disabled"; }; @@ -122,7 +122,7 @@ Work-in-progress patch to complete mt7988a.dtsi i2c0: i2c@11003000 { compatible = "mediatek,mt7981-i2c"; reg = <0 0x11003000 0 0x1000>, -@@ -425,7 +512,7 @@ +@@ -424,7 +511,7 @@ <0 0x0f0f0018 0 0x20>; }; @@ -131,7 +131,7 @@ Work-in-progress patch to complete mt7988a.dtsi compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; reg = <0 0x11190000 0 0x2e00>, <0 0x11193e00 0 0x0100>; -@@ -459,6 +546,35 @@ +@@ -458,6 +545,35 @@ status = "disabled"; }; @@ -167,7 +167,7 @@ Work-in-progress patch to complete mt7988a.dtsi mmc0: mmc@11230000 { compatible = "mediatek,mt7988-mmc"; reg = <0 0x11230000 0 0x1000>, -@@ -721,6 +837,10 @@ +@@ -720,6 +836,10 @@ #address-cells = <1>; #size-cells = <1>; @@ -195,10 +195,10 @@ Work-in-progress patch to complete mt7988a.dtsi status = "disabled"; }; -@@ -1002,9 +1126,37 @@ - reg = <15>; +@@ -1001,6 +1125,21 @@ + int_2p5g_phy: ethernet-phy@15 { compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "internal"; + reg = <15>; + + leds { + #address-cells = <1>; @@ -206,19 +206,21 @@ Work-in-progress patch to complete mt7988a.dtsi + + i2p5gbe_led0: i2p5gbe-led0@0 { + reg = <0>; -+ function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + i2p5gbe_led1: i2p5gbe-led1@1 { + reg = <1>; -+ function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; }; }; }; +@@ -1012,6 +1151,17 @@ + #size-cells = <1>; + ranges = <0 0x15400000 0 0x200000>; + }; + + crypto: crypto@15600000 { + compatible = "inside-secure,safexcel-eip197b"; diff --git a/target/linux/mediatek/patches-6.18/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch b/target/linux/mediatek/patches-6.18/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch index 0e0236c5fc..b075a1d0be 100644 --- a/target/linux/mediatek/patches-6.18/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch +++ b/target/linux/mediatek/patches-6.18/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch @@ -34,7 +34,7 @@ Signed-off-by: Sam Shih Signed-off-by: Daniel Golle --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile -@@ -24,6 +24,19 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-b +@@ -25,6 +25,19 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-b dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo diff --git a/target/linux/mediatek/patches-6.18/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch b/target/linux/mediatek/patches-6.18/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch index 8eccb6f8f1..be55d3e9fd 100644 --- a/target/linux/mediatek/patches-6.18/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch +++ b/target/linux/mediatek/patches-6.18/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch @@ -6,8 +6,8 @@ Subject: [PATCH 32/32] WIP: add BPi-R4 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts @@ -20,3 +20,16 @@ - pinctrl-names = "i2p5gbe-led"; pinctrl-0 = <&i2p5gbe_led0_pins>; + pinctrl-names = "i2p5gbe-led"; }; + +&gmac1 { @@ -22,40 +22,12 @@ Subject: [PATCH 32/32] WIP: add BPi-R4 + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; +}; ---- /dev/null +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso -@@ -0,0 +1,56 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2021 MediaTek Inc. -+ * Author: Frank Wunderlich -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; -+}; -+ -+&{/soc/mmc@11230000} { -+ pinctrl-names = "default", "state_uhs"; -+ pinctrl-0 = <&mmc0_pins_emmc_51>; -+ pinctrl-1 = <&mmc0_pins_emmc_51>; -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ hs400-ds-delay = <0x12814>; -+ vqmmc-supply = <®_1p8v>; -+ vmmc-supply = <®_3p3v>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; +@@ -29,5 +29,31 @@ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + card@0 { + compatible = "mmc-card"; @@ -76,11 +48,14 @@ Subject: [PATCH 32/32] WIP: add BPi-R4 + }; + }; + }; -+}; -+ + }; + +&{/chosen} { + rootdisk-emmc = <&emmc_rootfs>; +}; ++ ++ ++ --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso @@ -0,0 +1,19 @@ @@ -103,38 +78,12 @@ Subject: [PATCH 32/32] WIP: add BPi-R4 + }; + }; +}; ---- /dev/null +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso -@@ -0,0 +1,54 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2023 MediaTek Inc. -+ * Author: Frank Wunderlich -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+#include -+ -+/ { -+ compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; -+}; -+ -+&{/soc/mmc@11230000} { -+ pinctrl-names = "default", "state_uhs"; -+ pinctrl-0 = <&mmc0_pins_sdcard>; -+ pinctrl-1 = <&mmc0_pins_sdcard>; -+ cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ max-frequency = <52000000>; -+ cap-sd-highspeed; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_3p3v>; -+ no-mmc; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; +@@ -27,5 +27,30 @@ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + card@0 { + compatible = "mmc-card"; @@ -155,14 +104,16 @@ Subject: [PATCH 32/32] WIP: add BPi-R4 + }; + }; + }; -+}; -+ + }; + +&{/chosen} { + rootdisk-sd = <&sd_rootfs>; +}; ++ ++ --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -35,3 +35,11 @@ +@@ -36,3 +36,11 @@ reg = <2>; }; }; @@ -176,17 +127,16 @@ Subject: [PATCH 32/32] WIP: add BPi-R4 +}; --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -3,6 +3,8 @@ +@@ -3,6 +3,7 @@ /dts-v1/; #include +#include -+#include + #include #include + #include +@@ -18,6 +19,8 @@ - #include "mt7988a.dtsi" -@@ -10,6 +12,8 @@ - / { chosen { stdout-path = "serial0:115200n8"; + bootargs = "console=ttyS0,115200n1 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0"; @@ -194,9 +144,9 @@ Subject: [PATCH 32/32] WIP: add BPi-R4 }; fan: pwm-fan { -@@ -50,6 +54,142 @@ - rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; - maximum-power-milliwatt = <3000>; +@@ -78,6 +81,142 @@ + tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; }; + + aliases { @@ -337,7 +287,7 @@ Subject: [PATCH 32/32] WIP: add BPi-R4 }; &cci { -@@ -174,6 +314,10 @@ +@@ -262,6 +401,10 @@ color = ; }; @@ -348,7 +298,7 @@ Subject: [PATCH 32/32] WIP: add BPi-R4 &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; -@@ -265,6 +409,14 @@ +@@ -353,6 +496,14 @@ #size-cells = <0>; reg = <1>; }; @@ -363,97 +313,7 @@ Subject: [PATCH 32/32] WIP: add BPi-R4 }; }; -@@ -364,34 +516,6 @@ - }; - }; - -- gbe0_led1_pins: gbe0-led1-pins { -- mux { -- function = "led"; -- groups = "gbe0_led1"; -- }; -- }; -- -- gbe1_led1_pins: gbe1-led1-pins { -- mux { -- function = "led"; -- groups = "gbe1_led1"; -- }; -- }; -- -- gbe2_led1_pins: gbe2-led1-pins { -- mux { -- function = "led"; -- groups = "gbe2_led1"; -- }; -- }; -- -- gbe3_led1_pins: gbe3-led1-pins { -- mux { -- function = "led"; -- groups = "gbe3_led1"; -- }; -- }; -- - i2p5gbe_led0_pins: 2p5gbe-led0-pins { - mux { - function = "led"; -@@ -399,13 +523,6 @@ - }; - }; - -- i2p5gbe_led1_pins: 2p5gbe-led1-pins { -- mux { -- function = "led"; -- groups = "2p5gbe_led1"; -- }; -- }; -- - mmc0_pins_emmc_45: mmc0-emmc-45-pins { - mux { - function = "flash"; -@@ -427,40 +544,12 @@ - }; - }; - -- snfi_pins: snfi-pins { -- mux { -- function = "flash"; -- groups = "snfi"; -- }; -- }; -- -- spi0_pins: spi0-pins { -- mux { -- function = "spi"; -- groups = "spi0"; -- }; -- }; -- - spi0_flash_pins: spi0-flash-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - }; -- -- spi2_pins: spi2-pins { -- mux { -- function = "spi"; -- groups = "spi2"; -- }; -- }; -- -- spi2_flash_pins: spi2-flash-pins { -- mux { -- function = "spi"; -- groups = "spi2", "spi2_wp_hold"; -- }; -- }; - }; - - &pwm { -@@ -500,6 +589,32 @@ +@@ -499,6 +650,32 @@ reg = <0x0 0x200000>; read-only; }; diff --git a/target/linux/mediatek/patches-6.18/194-dts-mt7968a-add-ramoops.patch b/target/linux/mediatek/patches-6.18/194-dts-mt7986a-add-ramoops.patch similarity index 100% rename from target/linux/mediatek/patches-6.18/194-dts-mt7968a-add-ramoops.patch rename to target/linux/mediatek/patches-6.18/194-dts-mt7986a-add-ramoops.patch diff --git a/target/linux/mediatek/patches-6.18/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch b/target/linux/mediatek/patches-6.18/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch index 2554f88317..5a41ff6a6d 100644 --- a/target/linux/mediatek/patches-6.18/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch +++ b/target/linux/mediatek/patches-6.18/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch @@ -23,7 +23,7 @@ Signed-off-by: Daniel Golle }; chosen { -@@ -418,27 +422,27 @@ +@@ -415,27 +419,27 @@ port@1 { reg = <1>; @@ -56,7 +56,7 @@ Signed-off-by: Daniel Golle phy-mode = "2500base-x"; sfp = <&sfp2>; managed = "in-band-status"; -@@ -489,9 +493,137 @@ +@@ -486,9 +490,137 @@ &wifi { status = "okay"; diff --git a/target/linux/mediatek/patches-6.18/198-dts-mt7988a-enable-wed.patch b/target/linux/mediatek/patches-6.18/198-dts-mt7988a-enable-wed.patch index 45ae596256..8468adbb43 100644 --- a/target/linux/mediatek/patches-6.18/198-dts-mt7988a-enable-wed.patch +++ b/target/linux/mediatek/patches-6.18/198-dts-mt7988a-enable-wed.patch @@ -10,7 +10,7 @@ Signed-off-by: Daniel Golle --- --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -145,6 +145,32 @@ +@@ -144,6 +144,32 @@ reg = <0 0x43000000 0 0x50000>; no-map; }; @@ -43,7 +43,7 @@ Signed-off-by: Daniel Golle }; soc { -@@ -867,6 +893,50 @@ +@@ -866,6 +892,50 @@ reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; @@ -94,16 +94,16 @@ Signed-off-by: Daniel Golle }; switch: switch@15020000 { -@@ -1086,6 +1156,7 @@ - <&apmixedsys CLK_APMIXED_SGMPLL>; +@@ -1087,6 +1157,7 @@ + #size-cells = <0>; mediatek,ethsys = <ðsys>; mediatek,infracfg = <&topmisc>; + mediatek,wed = <&wed0>, <&wed1>, <&wed2>; - #address-cells = <1>; - #size-cells = <0>; -@@ -1147,6 +1218,72 @@ - }; + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; +@@ -1152,6 +1223,72 @@ + ranges = <0 0x15400000 0 0x200000>; }; + wo_ccif0: syscon@151a5000 { diff --git a/target/linux/mediatek/patches-6.18/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-6.18/200-phy-phy-mtk-tphy-Add-hifsys-support.patch index 5c482f6358..a4cd1895cb 100644 --- a/target/linux/mediatek/patches-6.18/200-phy-phy-mtk-tphy-Add-hifsys-support.patch +++ b/target/linux/mediatek/patches-6.18/200-phy-phy-mtk-tphy-Add-hifsys-support.patch @@ -18,7 +18,7 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support #include "phy-mtk-io.h" -@@ -271,6 +273,9 @@ +@@ -269,6 +271,9 @@ #define USER_BUF_LEN(count) min_t(size_t, 8, (count)) @@ -28,7 +28,7 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support enum mtk_phy_version { MTK_PHY_V1 = 1, MTK_PHY_V2, -@@ -339,6 +344,7 @@ struct mtk_tphy { +@@ -341,6 +346,7 @@ struct mtk_tphy { void __iomem *sif_base; /* only shared sif */ const struct mtk_phy_pdata *pdata; struct mtk_phy_instance **phys; @@ -36,7 +36,7 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support int nphys; int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ int src_coef; /* coefficient for slew rate calibrate */ -@@ -973,6 +979,10 @@ static void pcie_phy_instance_init(struc +@@ -957,6 +963,10 @@ static void pcie_phy_instance_init(struc if (tphy->pdata->version != MTK_PHY_V1) return; @@ -47,9 +47,9 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) | -@@ -1621,6 +1631,16 @@ static int mtk_tphy_probe(struct platfor - &tphy->src_coef); - } +@@ -1610,6 +1620,16 @@ static int mtk_tphy_probe(struct platfor + if (ret) + tphy->src_coef = tphy->pdata->slew_rate_coefficient; + if (of_property_present(np, "mediatek,phy-switch")) { + tphy->hif = syscon_regmap_lookup_by_phandle(np, diff --git a/target/linux/mediatek/patches-6.18/255-clk-mediatek-mt7988-infracfg-SPI0-clocks-are-not-critical.patch b/target/linux/mediatek/patches-6.18/255-clk-mediatek-mt7988-infracfg-SPI0-clocks-are-not-critical.patch index ed3471933c..413b157ef2 100644 --- a/target/linux/mediatek/patches-6.18/255-clk-mediatek-mt7988-infracfg-SPI0-clocks-are-not-critical.patch +++ b/target/linux/mediatek/patches-6.18/255-clk-mediatek-mt7988-infracfg-SPI0-clocks-are-not-critical.patch @@ -48,7 +48,7 @@ Signed-off-by: Daniel Golle --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c -@@ -196,12 +196,10 @@ static const struct mtk_gate infra_clks[ +@@ -192,12 +192,10 @@ static const struct mtk_gate infra_clks[ GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11, CLK_IS_CRITICAL), diff --git a/target/linux/mediatek/patches-6.18/320-hwrng-mtk-add-support-for-hw-access-via-SMCC.patch b/target/linux/mediatek/patches-6.18/320-hwrng-mtk-add-support-for-hw-access-via-SMCC.patch index 9bd9d0ab31..4a7f8438d4 100644 --- a/target/linux/mediatek/patches-6.18/320-hwrng-mtk-add-support-for-hw-access-via-SMCC.patch +++ b/target/linux/mediatek/patches-6.18/320-hwrng-mtk-add-support-for-hw-access-via-SMCC.patch @@ -55,7 +55,7 @@ Signed-off-by: Daniel Golle }; static int mtk_rng_init(struct hwrng *rng) -@@ -104,6 +113,56 @@ static int mtk_rng_read(struct hwrng *rn +@@ -103,6 +112,56 @@ static int mtk_rng_read(struct hwrng *rn return retval || !wait ? retval : -EIO; } @@ -112,7 +112,7 @@ Signed-off-by: Daniel Golle static int mtk_rng_probe(struct platform_device *pdev) { int ret; -@@ -115,23 +174,42 @@ static int mtk_rng_probe(struct platform +@@ -114,23 +173,42 @@ static int mtk_rng_probe(struct platform priv->dev = &pdev->dev; priv->rng.name = pdev->name; @@ -168,7 +168,7 @@ Signed-off-by: Daniel Golle ret = devm_hwrng_register(&pdev->dev, &priv->rng); if (ret) { -@@ -140,12 +218,15 @@ static int mtk_rng_probe(struct platform +@@ -139,12 +217,15 @@ static int mtk_rng_probe(struct platform return ret; } @@ -190,7 +190,7 @@ Signed-off-by: Daniel Golle dev_info(&pdev->dev, "registered RNG driver\n"); -@@ -182,8 +263,12 @@ static const struct dev_pm_ops mtk_rng_p +@@ -181,8 +262,12 @@ static const struct dev_pm_ops mtk_rng_p #endif /* CONFIG_PM */ static const struct of_device_id mtk_rng_match[] = { @@ -204,7 +204,7 @@ Signed-off-by: Daniel Golle {}, }; MODULE_DEVICE_TABLE(of, mtk_rng_match); -@@ -201,4 +286,5 @@ module_platform_driver(mtk_rng_driver); +@@ -200,4 +285,5 @@ module_platform_driver(mtk_rng_driver); MODULE_DESCRIPTION("Mediatek Random Number Generator Driver"); MODULE_AUTHOR("Sean Wang "); diff --git a/target/linux/mediatek/patches-6.18/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-6.18/330-snand-mtk-bmt-support.patch index 28e63ebeee..df58fa0821 100644 --- a/target/linux/mediatek/patches-6.18/330-snand-mtk-bmt-support.patch +++ b/target/linux/mediatek/patches-6.18/330-snand-mtk-bmt-support.patch @@ -18,9 +18,9 @@ Signed-off-by: Chuanhong Guo #include +#include - static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) + int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) { -@@ -1604,6 +1605,7 @@ static int spinand_probe(struct spi_mem +@@ -1685,6 +1686,7 @@ static int spinand_probe(struct spi_mem if (ret) return ret; @@ -28,7 +28,7 @@ Signed-off-by: Chuanhong Guo ret = mtd_device_register(mtd, NULL, 0); if (ret) goto err_spinand_cleanup; -@@ -1611,6 +1613,7 @@ static int spinand_probe(struct spi_mem +@@ -1692,6 +1694,7 @@ static int spinand_probe(struct spi_mem return 0; err_spinand_cleanup: @@ -36,7 +36,7 @@ Signed-off-by: Chuanhong Guo spinand_cleanup(spinand); return ret; -@@ -1629,6 +1632,7 @@ static int spinand_remove(struct spi_mem +@@ -1710,6 +1713,7 @@ static int spinand_remove(struct spi_mem if (ret) return ret; diff --git a/target/linux/mediatek/patches-6.18/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-6.18/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch deleted file mode 100644 index 05a02bde22..0000000000 --- a/target/linux/mediatek/patches-6.18/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch +++ /dev/null @@ -1,123 +0,0 @@ -From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001 -From: Davide Fioravanti -Date: Fri, 8 Jan 2021 15:35:24 +0100 -Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA - -Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf - -Signed-off-by: Davide Fioravanti ---- - drivers/mtd/nand/spi/Makefile | 2 +- - drivers/mtd/nand/spi/core.c | 1 + - drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++ - include/linux/mtd/spinand.h | 1 + - 4 files changed, 79 insertions(+), 1 deletion(-) - create mode 100644 drivers/mtd/nand/spi/fidelix.c - ---- a/drivers/mtd/nand/spi/Makefile -+++ b/drivers/mtd/nand/spi/Makefile -@@ -1,4 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 --spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fmsh.o foresee.o gigadevice.o -+spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fidelix.o fmsh.o foresee.o gigadevice.o - spinand-objs += macronix.o micron.o paragon.o skyhigh.o toshiba.o winbond.o xtx.o - obj-$(CONFIG_MTD_SPI_NAND) += spinand.o ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -1189,6 +1189,7 @@ static const struct spinand_manufacturer - &esmt_c8_spinand_manufacturer, - &etron_spinand_manufacturer, - &fmsh_spinand_manufacturer, -+ &fidelix_spinand_manufacturer, - &foresee_spinand_manufacturer, - &gigadevice_spinand_manufacturer, - ¯onix_spinand_manufacturer, ---- /dev/null -+++ b/drivers/mtd/nand/spi/fidelix.c -@@ -0,0 +1,76 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2020 Davide Fioravanti -+ */ -+ -+#include -+#include -+#include -+ -+#define SPINAND_MFR_FIDELIX 0xE5 -+#define FIDELIX_ECCSR_MASK 0x0F -+ -+static SPINAND_OP_VARIANTS(read_cache_variants, -+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(write_cache_variants, -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(update_cache_variants, -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); -+ -+static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ region->offset = (16 * section) + 8; -+ region->length = 8; -+ -+ return 0; -+} -+ -+static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ region->offset = (16 * section) + 2; -+ region->length = 6; -+ -+ return 0; -+} -+ -+static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = { -+ .ecc = fm35x1ga_ooblayout_ecc, -+ .free = fm35x1ga_ooblayout_free, -+}; -+ -+static const struct spinand_info fidelix_spinand_table[] = { -+ SPINAND_INFO("FM35X1GA", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)), -+}; -+ -+static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = { -+}; -+ -+const struct spinand_manufacturer fidelix_spinand_manufacturer = { -+ .id = SPINAND_MFR_FIDELIX, -+ .name = "Fidelix", -+ .chips = fidelix_spinand_table, -+ .nchips = ARRAY_SIZE(fidelix_spinand_table), -+ .ops = &fidelix_spinand_manuf_ops, -+}; ---- a/include/linux/mtd/spinand.h -+++ b/include/linux/mtd/spinand.h -@@ -266,6 +266,7 @@ extern const struct spinand_manufacturer - extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; - extern const struct spinand_manufacturer etron_spinand_manufacturer; - extern const struct spinand_manufacturer fmsh_spinand_manufacturer; -+extern const struct spinand_manufacturer fidelix_spinand_manufacturer; - extern const struct spinand_manufacturer foresee_spinand_manufacturer; - extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; - extern const struct spinand_manufacturer macronix_spinand_manufacturer; diff --git a/target/linux/mediatek/patches-6.18/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch b/target/linux/mediatek/patches-6.18/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch index c52ed76e92..7cb49eead4 100644 --- a/target/linux/mediatek/patches-6.18/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch +++ b/target/linux/mediatek/patches-6.18/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch @@ -35,7 +35,7 @@ Signed-off-by: Sam Shih --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -744,6 +744,7 @@ static const struct of_device_id mtk_cpu +@@ -750,6 +750,7 @@ static const struct of_device_id mtk_cpu { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data }, diff --git a/target/linux/mediatek/patches-6.18/360-pinctrl-mediatek-add-mt7987-pinctrl-support.patch b/target/linux/mediatek/patches-6.18/360-pinctrl-add-pinctrl-driver-for-mt7987-from-sdk.patch similarity index 94% rename from target/linux/mediatek/patches-6.18/360-pinctrl-mediatek-add-mt7987-pinctrl-support.patch rename to target/linux/mediatek/patches-6.18/360-pinctrl-add-pinctrl-driver-for-mt7987-from-sdk.patch index 061a14c5f6..1cb43bfc6c 100644 --- a/target/linux/mediatek/patches-6.18/360-pinctrl-mediatek-add-mt7987-pinctrl-support.patch +++ b/target/linux/mediatek/patches-6.18/360-pinctrl-add-pinctrl-driver-for-mt7987-from-sdk.patch @@ -1,24 +1,23 @@ -From e37d53fb387eb788dff33cdc4c1009543e2ccd5f Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Mon, 20 Jan 2025 19:49:34 +0800 -Subject: [PATCH 1/2] pinctrl: mediatek: add mt7987 pinctrl support +From b93d8bb7ac7fbb86e16eb3f3d3300d3eb9bf28bf Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Wed, 3 Sep 2025 08:53:19 +0200 +Subject: [PATCH] pinctrl: add pinctrl driver for mt7987 from sdk -Signed-off-by: Daniel Golle --- - drivers/pinctrl/mediatek/Kconfig | 6 + + drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/Makefile | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7987.c | 752 ++++++++++++++++++++++ - 3 files changed, 759 insertions(+) + drivers/pinctrl/mediatek/pinctrl-mt7987.c | 675 ++++++++++++++++++++++ + 3 files changed, 683 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7987.c --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig -@@ -187,6 +187,13 @@ config PINCTRL_MT7986 +@@ -212,6 +212,13 @@ config PINCTRL_MT7986 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE +config PINCTRL_MT7987 -+ bool "Mediatek MT7987 pin control" ++ bool "MediaTek MT7987 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK @@ -29,7 +28,7 @@ Signed-off-by: Daniel Golle depends on OF --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl +@@ -29,6 +29,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o @@ -39,7 +38,7 @@ Signed-off-by: Daniel Golle obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt7987.c -@@ -0,0 +1,751 @@ +@@ -0,0 +1,675 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The MT7987 driver based on Linux generic pinctrl binding. @@ -47,9 +46,7 @@ Signed-off-by: Daniel Golle + * Copyright (C) 2020 MediaTek Inc. + * Author: Tim.Kuo + */ -+ +#include "pinctrl-moore.h" -+ +enum MT7987_PINCTRL_REG_PAGE { + GPIO_BASE, + IOCFG_RB_BASE, @@ -58,41 +55,31 @@ Signed-off-by: Daniel Golle + IOCFG_RT2_BASE, + IOCFG_TL_BASE, +}; -+ +#define MT7987_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) -+ +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) -+ +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) -+ -+ +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) -+ +static const struct mtk_pin_field_calc mt7987_pin_mode_range[] = { + PIN_FIELD(0, 49, 0x300, 0x10, 0, 4), +}; -+ +static const struct mtk_pin_field_calc mt7987_pin_dir_range[] = { + PIN_FIELD(0, 49, 0x0, 0x10, 0, 1), +}; -+ +static const struct mtk_pin_field_calc mt7987_pin_di_range[] = { + PIN_FIELD(0, 49, 0x200, 0x10, 0, 1), +}; -+ +static const struct mtk_pin_field_calc mt7987_pin_do_range[] = { + PIN_FIELD(0, 49, 0x100, 0x10, 0, 1), +}; -+ +static const struct mtk_pin_field_calc mt7987_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x20, 0x10, 2, 1), @@ -145,7 +132,6 @@ Signed-off-by: Daniel Golle + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x20, 0x10, 8, 1), +}; -+ +static const struct mtk_pin_field_calc mt7987_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x90, 0x10, 2, 1), @@ -198,7 +184,6 @@ Signed-off-by: Daniel Golle + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x90, 0x10, 8, 1), +}; -+ +static const struct mtk_pin_field_calc mt7987_pin_pu_range[] = { + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), @@ -207,7 +192,6 @@ Signed-off-by: Daniel Golle + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x40, 0x10, 5, 1), +}; -+ +static const struct mtk_pin_field_calc mt7987_pin_pd_range[] = { + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x30, 0x10, 0, 1), @@ -216,7 +200,6 @@ Signed-off-by: Daniel Golle + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x30, 0x10, 5, 1), +}; -+ +static const struct mtk_pin_field_calc mt7987_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x0, 0x10, 6, 3), @@ -269,7 +252,6 @@ Signed-off-by: Daniel Golle + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x0, 0x10, 21, 3), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x0, 0x10, 24, 3), +}; -+ +static const struct mtk_pin_field_calc mt7987_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x30, 0x10, 2, 1), @@ -304,7 +286,6 @@ Signed-off-by: Daniel Golle + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x30, 0x10, 6, 1), -+ + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x30, 0x10, 0, 1), @@ -317,7 +298,6 @@ Signed-off-by: Daniel Golle + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), +}; -+ +static const struct mtk_pin_field_calc mt7987_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x40, 0x10, 2, 1), @@ -352,7 +332,6 @@ Signed-off-by: Daniel Golle + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x40, 0x10, 6, 1), -+ + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x40, 0x10, 0, 1), @@ -365,7 +344,6 @@ Signed-off-by: Daniel Golle + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x40, 0x10, 8, 1), +}; -+ +static const struct mtk_pin_field_calc mt7987_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x50, 0x10, 2, 1), @@ -400,7 +378,6 @@ Signed-off-by: Daniel Golle + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x50, 0x10, 6, 1), -+ + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x50, 0x10, 0, 1), @@ -413,7 +390,6 @@ Signed-off-by: Daniel Golle + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), +}; -+ +static const unsigned int mt7987_pull_type[] = { + MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ + MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ @@ -441,7 +417,6 @@ Signed-off-by: Daniel Golle + MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ + MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ +}; -+ +static const struct mtk_pin_reg_calc mt7987_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7987_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7987_pin_dir_range), @@ -456,7 +431,6 @@ Signed-off-by: Daniel Golle + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7987_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7987_pin_r1_range), +}; -+ +static const struct mtk_pin_desc mt7987_pins[] = { + MT7987_PIN(0, "GPIO_WPS"), + MT7987_PIN(1, "GPIO_RESET"), @@ -509,149 +483,106 @@ Signed-off-by: Daniel Golle + MT7987_PIN(48, "UART1_CTS"), + MT7987_PIN(49, "UART1_RTS"), +}; -+ +/* watchdog */ +static int mt7987_watchdog_pins[] = {2}; +static int mt7987_watchdog_funcs[] = {1}; -+ +/* jtag */ +static int mt7987_jtag_pins[] = {3, 4, 5, 6, 7}; +static int mt7987_jtag_funcs[] = {1, 1, 1, 1, 1}; -+ -+/* i2s */ -+static int mt7987_i2s_pins[] = { 8, 9, 10, 11, 12 }; -+static int mt7987_i2s_funcs[] = { 1, 1, 1, 1, 1 }; -+ +/* pcm */ -+static int mt7987_pcm_pins[] = { 8, 9, 10, 11 }; -+static int mt7987_pcm_funcs[] = { 1, 1, 1, 1 }; -+ ++static int mt7987_pcm0_0_pins[] = {3, 4, 5, 6, 7}; ++static int mt7987_pcm0_0_funcs[] = {2, 2, 2, 2, 2}; ++static int mt7987_pcm0_1_pins[] = {8, 9, 10, 11, 12}; ++static int mt7987_pcm0_1_funcs[] = {1, 1, 1, 1, 1}; +/* uart */ +static int mt7987_uart0_pins[] = {31, 32}; +static int mt7987_uart0_funcs[] = {1, 1}; -+ +static int mt7987_uart1_0_pins[] = {3, 4, 5, 6}; +static int mt7987_uart1_0_funcs[] = {3, 3, 3, 3}; -+ +static int mt7987_uart1_0_lite_pins[] = {3, 4}; +static int mt7987_uart1_0_lite_funcs[] = {3, 3}; -+ +static int mt7987_uart1_1_pins[] = {21, 22, 23, 24}; +static int mt7987_uart1_1_funcs[] = {3, 3, 3, 3}; -+ +static int mt7987_uart1_2_pins[] = {46, 47, 48, 49}; +static int mt7987_uart1_2_funcs[] = {1, 1, 1, 1}; -+ +static int mt7987_uart2_0_pins[] = {8, 9, 10, 11}; +static int mt7987_uart2_0_funcs[] = {2, 2, 2, 2}; -+ +static int mt7987_uart2_1_pins[] = {25, 26, 27, 28}; +static int mt7987_uart2_1_funcs[] = {2, 2, 2, 2}; -+ +/* pwm */ +static int mt7987_pwm0_pins[] = {13}; +static int mt7987_pwm0_funcs[] = {1}; -+ +static int mt7987_pwm1_0_pins[] = {7}; +static int mt7987_pwm1_0_funcs[] = {3}; -+ +static int mt7987_pwm1_1_pins[] = {43}; +static int mt7987_pwm1_1_funcs[] = {2}; -+ +static int mt7987_pwm2_0_pins[] = {12}; +static int mt7987_pwm2_0_funcs[] = {2}; -+ +static int mt7987_pwm2_1_pins[] = {44}; +static int mt7987_pwm2_1_funcs[] = {2}; -+ +/* vbus */ +static int mt7987_drv_vbus_p1_pins[] = {14}; +static int mt7987_drv_vbus_p1_funcs[] = {1}; -+ +static int mt7987_drv_vbus_pins[] = {48}; +static int mt7987_drv_vbus_funcs[] = {3}; -+ +/* 2p5gbe_led */ +static int mt7987_2p5gbe_led0_pins[] = {45}; +static int mt7987_2p5gbe_led0_funcs[] = {1}; -+ +static int mt7987_2p5gbe_led1_0_pins[] = {13}; +static int mt7987_2p5gbe_led1_0_funcs[] = {2}; -+ +static int mt7987_2p5gbe_led1_1_pins[] = {49}; +static int mt7987_2p5gbe_led1_1_funcs[] = {3}; -+ +/* mdc, mdio */ +static int mt7987_2p5g_ext_mdc_mdio_pins[] = {23, 24}; +static int mt7987_2p5g_ext_mdc_mdio_funcs[] = {4, 4}; -+ +static int mt7987_mdc_mdio_pins[] = {39, 40}; +static int mt7987_mdc_mdio_funcs[] = {1, 1}; -+ +/* spi */ +static int mt7987_spi0_pins[] = {15, 16, 17, 18}; +static int mt7987_spi0_funcs[] = {1, 1, 1, 1}; -+ +static int mt7987_spi0_wp_hold_pins[] = {19, 20}; +static int mt7987_spi0_wp_hold_funcs[] = {1, 1}; -+ +static int mt7987_spi1_pins[] = {21, 22, 23, 24}; +static int mt7987_spi1_funcs[] = {1, 1, 1, 1}; -+ +static int mt7987_spi1_1_pins[] = {46, 47, 48, 49}; +static int mt7987_spi1_1_funcs[] = {2, 2, 2, 2}; -+ +static int mt7987_spi2_pins[] = {25, 26, 27, 28}; +static int mt7987_spi2_funcs[] = {1, 1, 1, 1}; -+ +static int mt7987_spi2_wp_hold_pins[] = {29, 30}; +static int mt7987_spi2_wp_hold_funcs[] = {1, 1}; -+ +/* emmc */ +static int mt7987_emmc_45_pins[] = {14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24}; +static int mt7987_emmc_45_funcs[] = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}; -+ +/* sd */ +static int mt7987_sd_pins[] = {15, 16, 17, 18, 23, 24}; +static int mt7987_sd_funcs[] = {2, 2, 2, 2, 2, 2}; -+ +/* i2c */ +static int mt7987_i2c0_0_pins[] = {29, 30}; +static int mt7987_i2c0_0_funcs[] = {2, 2}; -+ +static int mt7987_i2c0_1_pins[] = {39, 40}; +static int mt7987_i2c0_1_funcs[] = {2, 2}; -+ +static int mt7987_i2c0_2_pins[] = {43, 44}; +static int mt7987_i2c0_2_funcs[] = {1, 1}; -+ +/* pcie */ +static int mt7987_pcie0_pereset_pins[] = {33}; +static int mt7987_pcie0_pereset_funcs[] = {1}; -+ +static int mt7987_pcie0_clkreq_pins[] = {34}; +static int mt7987_pcie0_clkreq_funcs[] = {1}; -+ +static int mt7987_pcie0_wake_pins[] = {35}; +static int mt7987_pcie0_wake_funcs[] = {1}; -+ +static int mt7987_pcie1_pereset_pins[] = {36}; +static int mt7987_pcie1_pereset_funcs[] = {1}; -+ +static int mt7987_pcie1_clkreq_pins[] = {37}; +static int mt7987_pcie1_clkreq_funcs[] = {1}; -+ +static int mt7987_pcie1_wake_pins[] = {38}; +static int mt7987_pcie1_wake_funcs[] = {1}; -+ +static int mt7987_pcie_phy_i2c_pins[] = {43, 44}; +static int mt7987_pcie_phy_i2c_funcs[] = {3, 3}; -+ +static const struct group_desc mt7987_groups[] = { + PINCTRL_PIN_GROUP("watchdog", mt7987_watchdog), + PINCTRL_PIN_GROUP("jtag", mt7987_jtag), -+ PINCTRL_PIN_GROUP("i2s", mt7987_i2s), -+ PINCTRL_PIN_GROUP("pcm", mt7987_pcm), ++ PINCTRL_PIN_GROUP("pcm0_0", mt7987_pcm0_0), ++ PINCTRL_PIN_GROUP("pcm0_1", mt7987_pcm0_1), + PINCTRL_PIN_GROUP("uart0", mt7987_uart0), + PINCTRL_PIN_GROUP("uart1_0", mt7987_uart1_0), + PINCTRL_PIN_GROUP("uart1_0_lite", mt7987_uart1_0_lite), @@ -690,10 +621,9 @@ Signed-off-by: Daniel Golle + PINCTRL_PIN_GROUP("pcie1_wake", mt7987_pcie1_wake), + PINCTRL_PIN_GROUP("pcie1_pcie_phy_i2c", mt7987_pcie_phy_i2c), +}; -+ -+static const char *const mt7987_audio_groups[] = {"i2s", "pcm",}; +static const char *const mt7987_wdt_groups[] = {"watchdog",}; +static const char *const mt7987_jtag_groups[] = {"jtag",}; ++static const char *const mt7987_pcm_groups[] = {"pcm0_0", "pcm0_1"}; +static const char *const mt7987_uart_groups[] = {"uart0", "uart1_0", + "uart1_0_lite", "uart1_1", + "uart1_2", "uart2_0", @@ -706,40 +636,37 @@ Signed-off-by: Daniel Golle +static const char *const mt7987_ethernet_groups[] = {"2p5g_ext_mdc_mdio", "mdc_mdio",}; +static const char *const mt7987_spi_groups[] = {"spi0", "spi0_wp_hold", "spi1", + "spi1_1", "spi2", "spi2_wp_hold",}; -+static const char *const mt7987_flash_groups[] = {"emmc_45", "sd",}; ++static const char *const mt7987_flash_groups[] = {"emmc_45", "sd"}; +static const char *const mt7987_i2c_groups[] = {"i2c0_0", "i2c0_1", "i2c0_2",}; +static const char *const mt7987_pcie_groups[] = {"pcie_phy_i2c", "pcie0_pereset", + "pcie0_clkreq", "pcie0_wake", + "pcie1_pereset", "pcie1_clkreq", + "pcie1_wake",}; -+ -+ -+static const struct function_desc mt7987_functions[] = { -+ { {"audio", mt7987_audio_groups, ARRAY_SIZE(mt7987_audio_groups)}, NULL }, -+ { {"wdt", mt7987_wdt_groups, ARRAY_SIZE(mt7987_wdt_groups)}, NULL }, -+ { {"jtag", mt7987_jtag_groups, ARRAY_SIZE(mt7987_jtag_groups)}, NULL }, -+ { {"uart", mt7987_uart_groups, ARRAY_SIZE(mt7987_uart_groups)}, NULL }, -+ { {"pwm", mt7987_pwm_groups, ARRAY_SIZE(mt7987_pwm_groups)}, NULL }, -+ { {"usb", mt7987_usb_groups, ARRAY_SIZE(mt7987_usb_groups)}, NULL }, -+ { {"led", mt7987_led_groups, ARRAY_SIZE(mt7987_led_groups)}, NULL }, -+ { {"eth", mt7987_ethernet_groups, ARRAY_SIZE(mt7987_ethernet_groups)}, NULL }, -+ { {"spi", mt7987_spi_groups, ARRAY_SIZE(mt7987_spi_groups)}, NULL }, -+ { {"flash", mt7987_flash_groups, ARRAY_SIZE(mt7987_flash_groups)}, NULL }, -+ { {"i2c", mt7987_i2c_groups, ARRAY_SIZE(mt7987_i2c_groups)}, NULL }, -+ { {"pcie", mt7987_pcie_groups, ARRAY_SIZE(mt7987_pcie_groups)}, NULL }, ++static const char *const mt7987_i2s_groups[] = {"pcm0_0", "pcm0_1"}; ++static const struct pinfunction mt7987_functions[] = { ++ PINCTRL_PIN_FUNCTION("wdt", mt7987_wdt), ++ PINCTRL_PIN_FUNCTION("jtag", mt7987_jtag), ++ PINCTRL_PIN_FUNCTION("pcm", mt7987_pcm), ++ PINCTRL_PIN_FUNCTION("uart", mt7987_uart), ++ PINCTRL_PIN_FUNCTION("pwm", mt7987_pwm), ++ PINCTRL_PIN_FUNCTION("usb", mt7987_usb), ++ PINCTRL_PIN_FUNCTION("led", mt7987_led), ++ PINCTRL_PIN_FUNCTION("eth", mt7987_ethernet), ++ PINCTRL_PIN_FUNCTION("spi", mt7987_spi), ++ PINCTRL_PIN_FUNCTION("flash", mt7987_flash), ++ PINCTRL_PIN_FUNCTION("i2c", mt7987_i2c), ++ PINCTRL_PIN_FUNCTION("pcie", mt7987_pcie), ++ PINCTRL_PIN_FUNCTION("i2s", mt7987_i2s), +}; -+ +static const struct mtk_eint_hw mt7987_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = ARRAY_SIZE(mt7987_pins), + .db_cnt = 16, +}; -+ +static const char * const mt7987_pinctrl_register_base_names[] = { + "gpio", "iocfg_rb", "iocfg_lb", "iocfg_rt1", "iocfg_rt2", "iocfg_tl", +}; -+ +static struct mtk_pin_soc mt7987_data = { + .reg_cal = mt7987_reg_cals, + .pins = mt7987_pins, @@ -750,7 +677,7 @@ Signed-off-by: Daniel Golle + .nfuncs = ARRAY_SIZE(mt7987_functions), + .eint_hw = &mt7987_eint_hw, + .gpio_m = 0, -+ .ies_present = true, ++ .ies_present = false, + .base_names = mt7987_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7987_pinctrl_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set, @@ -765,19 +692,16 @@ Signed-off-by: Daniel Golle + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; -+ +static const struct of_device_id mt7987_pinctrl_of_match[] = { + { + .compatible = "mediatek,mt7987-pinctrl", + }, + {} +}; -+ +static int mt7987_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_moore_pinctrl_probe(pdev, &mt7987_data); +} -+ +static struct platform_driver mt7987_pinctrl_driver = { + .driver = { + .name = "mt7987-pinctrl", @@ -785,7 +709,6 @@ Signed-off-by: Daniel Golle + }, + .probe = mt7987_pinctrl_probe, +}; -+ +static int __init mt7987_pinctrl_init(void) +{ + return platform_driver_register(&mt7987_pinctrl_driver); diff --git a/target/linux/mediatek/patches-6.18/361-clk-mediatek-add-mt7987-clock-drivers-support.patch b/target/linux/mediatek/patches-6.18/361-clk-mediatek-add-clock-driver-for-mt7987-from-sdk.patch similarity index 92% rename from target/linux/mediatek/patches-6.18/361-clk-mediatek-add-mt7987-clock-drivers-support.patch rename to target/linux/mediatek/patches-6.18/361-clk-mediatek-add-clock-driver-for-mt7987-from-sdk.patch index 249e239086..44ef8ec30d 100644 --- a/target/linux/mediatek/patches-6.18/361-clk-mediatek-add-mt7987-clock-drivers-support.patch +++ b/target/linux/mediatek/patches-6.18/361-clk-mediatek-add-clock-driver-for-mt7987-from-sdk.patch @@ -1,31 +1,26 @@ -From 08b3847982f4c470ff1ac0761bed0d8d83f1fd49 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Mon, 20 Jan 2025 19:50:03 +0800 -Subject: [PATCH 2/2] clk: mediatek: add mt7987 clock drivers support +From a20f5db46e87c60dac43c67a03e1b48e57d1349a Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Wed, 3 Sep 2025 08:43:14 +0200 +Subject: [PATCH] clk: mediatek: add clock driver for mt7987 from sdk -Signed-off-by: Daniel Golle --- - drivers/clk/mediatek/Kconfig | 9 + - drivers/clk/mediatek/Makefile | 5 + - drivers/clk/mediatek/clk-mt7987-apmixed.c | 116 +++++++ - drivers/clk/mediatek/clk-mt7987-eth.c | 94 +++++ - drivers/clk/mediatek/clk-mt7987-infracfg.c | 328 ++++++++++++++++++ - drivers/clk/mediatek/clk-mt7987-mcusys.c | 47 +++ - drivers/clk/mediatek/clk-mt7987-topckgen.c | 311 +++++++++++++++++ - .../dt-bindings/clock/mediatek,mt7987-clk.h | 206 +++++++++++ - .../reset/mediatek,mt7987-resets.h | 10 + - 9 files changed, 1126 insertions(+) + drivers/clk/mediatek/Kconfig | 17 ++ + drivers/clk/mediatek/Makefile | 5 + + drivers/clk/mediatek/clk-mt7987-apmixed.c | 102 ++++++++ + drivers/clk/mediatek/clk-mt7987-eth.c | 80 ++++++ + drivers/clk/mediatek/clk-mt7987-infracfg.c | 288 +++++++++++++++++++++ + drivers/clk/mediatek/clk-mt7987-mcusys.c | 41 +++ + drivers/clk/mediatek/clk-mt7987-topckgen.c | 273 +++++++++++++++++++ + 7 files changed, 806 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt7987-apmixed.c create mode 100644 drivers/clk/mediatek/clk-mt7987-eth.c create mode 100644 drivers/clk/mediatek/clk-mt7987-infracfg.c create mode 100644 drivers/clk/mediatek/clk-mt7987-mcusys.c create mode 100644 drivers/clk/mediatek/clk-mt7987-topckgen.c - create mode 100644 include/dt-bindings/clock/mediatek,mt7987-clk.h - create mode 100644 include/dt-bindings/reset/mediatek,mt7987-resets.h --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig -@@ -423,6 +423,15 @@ config COMMON_CLK_MT7986_ETHSYS +@@ -460,6 +460,23 @@ config COMMON_CLK_MT7986_ETHSYS This driver adds support for clocks for Ethernet and SGMII required on MediaTek MT7986 SoC. @@ -36,35 +31,42 @@ Signed-off-by: Daniel Golle + default ARCH_MEDIATEK + help + This driver supports MediaTek MT7987 basic clocks and clocks -+ required for various periperals found on this SoC. ++ required for various peripherals found on MediaTek. ++ ++config COMMON_CLK_MT7987_ETHSYS ++ tristate "Clock driver for MediaTek MT7987 ETHSYS" ++ depends on COMMON_CLK_MT7987 ++ default COMMON_CLK_MT7987 ++ help ++ This driver adds support for clocks for Ethernet and SGMII ++ required on MediaTek MT7987 SoC. + config COMMON_CLK_MT7988 tristate "Clock driver for MediaTek MT7988" depends on ARCH_MEDIATEK || COMPILE_TEST --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile -@@ -62,6 +62,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m +@@ -67,6 +67,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o +obj-$(CONFIG_COMMON_CLK_MT7987) += clk-mt7987-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7987) += clk-mt7987-eth.o ++obj-$(CONFIG_COMMON_CLK_MT7987) += clk-mt7987-topckgen.o +obj-$(CONFIG_COMMON_CLK_MT7987) += clk-mt7987-infracfg.o +obj-$(CONFIG_COMMON_CLK_MT7987) += clk-mt7987-mcusys.o -+obj-$(CONFIG_COMMON_CLK_MT7987) += clk-mt7987-topckgen.o ++obj-$(CONFIG_COMMON_CLK_MT7987_ETHSYS) += clk-mt7987-eth.o obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7987-apmixed.c -@@ -0,0 +1,116 @@ +@@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 MediaTek Inc. + * Author: Lu Tang + * Author: Sam Shih + */ -+ +#include +#include +#include @@ -94,7 +96,6 @@ Signed-off-by: Daniel Golle + .pcw_chg_bit = MT7987_PCW_CHG_SHIFT, \ + .div_table = _div_table, .parent_name = _parent_name, \ + } -+ +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ + _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, _parent_name) \ @@ -176,14 +177,13 @@ Signed-off-by: Daniel Golle +MODULE_LICENSE("GPL"); --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7987-eth.c -@@ -0,0 +1,94 @@ +@@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 MediaTek Inc. + * Author: Lu Tang + * Author: Sam Shih + */ -+ +#include +#include +#include @@ -265,22 +265,20 @@ Signed-off-by: Daniel Golle + .of_match_table = of_match_clk_mt7987_eth, + }, + .probe = mtk_clk_simple_probe, -+ .remove_new = mtk_clk_simple_remove, ++ .remove = mtk_clk_simple_remove, +}; +module_platform_driver(clk_mt7987_eth_drv); -+ +MODULE_DESCRIPTION("MediaTek MT7987 Ethernet clocks driver"); +MODULE_LICENSE("GPL"); --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7987-infracfg.c -@@ -0,0 +1,325 @@ +@@ -0,0 +1,318 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 MediaTek Inc. + * Author: Lu Tang + * Author: Sam Shih + */ -+ +#include +#include +#include @@ -324,9 +322,11 @@ Signed-off-by: Daniel Golle + "spi_sel" +}; + -+static const char *const infra_pwm_bck_parents[] = { "cb_rtc_32p7k", -+ "csw_infra_f26m_sel", -+ "sysaxi_sel", "pwm_sel" }; ++static const char *const infra_pwm_bck_parents[] = { ++ "cb_rtc_32p7k", ++ "csw_infra_f26m_sel", ++ "sysaxi_sel", "pwm_sel" ++}; + +static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] = { + "cb_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", @@ -340,37 +340,29 @@ Signed-off-by: Daniel Golle + +static struct mtk_mux infra_muxes[] = { + /* MODULE_CLK_SEL_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", -+ infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, -+ 0, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", -+ infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, -+ 1, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", -+ infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, -+ 2, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", -+ infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4, -+ 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", -+ infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5, -+ 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_BCK_SEL, -+ "infra_mux_spi2_bck_sel", -+ infra_mux_spi2_bck_parents, 0x0018, 0x0010, -+ 0x0014, 6, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BCK_SEL, "infra_pwm_bck_sel", -+ infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14, -+ 2, -1, -1, -1), ++ MUX_CLR_SET(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", ++ infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1), ++ MUX_CLR_SET(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", ++ infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1), ++ MUX_CLR_SET(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", ++ infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1), ++ MUX_CLR_SET(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", ++ infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1), ++ MUX_CLR_SET(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", ++ infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1), ++ MUX_CLR_SET(CLK_INFRA_MUX_SPI2_BCK_SEL, "infra_mux_spi2_bck_sel", ++ infra_mux_spi2_bck_parents, 0x0018, 0x0010, 0x0014, 6, 1), ++ MUX_CLR_SET(CLK_INFRA_PWM_BCK_SEL, "infra_pwm_bck_sel", ++ infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14, 2), + /* MODULE_CLK_SEL_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, -+ "infra_pcie_gfmux_tl_ck_o_p0_sel", -+ infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, -+ 0x0020, 0x0024, 0, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, -+ "infra_pcie_gfmux_tl_ck_o_p1_sel", -+ infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, -+ 0x0020, 0x0024, 2, 2, -1, -1, -1), ++ MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, ++ "infra_pcie_gfmux_tl_ck_o_p0_sel", ++ infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, ++ 0x0024, 0, 2), ++ MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, ++ "infra_pcie_gfmux_tl_ck_o_p1_sel", ++ infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, ++ 0x0024, 2, 2), +}; + +static const struct mtk_gate_regs infra0_cg_regs = { @@ -432,7 +424,7 @@ Signed-off-by: Daniel Golle + .ops = &mtk_clk_gate_ops_setclr, \ + } + -+static const struct mtk_gate infra_clks[] __initconst = { ++static const struct mtk_gate infra_clks[] = { + /* INFRA1 */ + GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", + "sysaxi_sel", 0), @@ -595,7 +587,7 @@ Signed-off-by: Daniel Golle + .of_match_table = of_match_clk_mt7987_infracfg, + }, + .probe = mtk_clk_simple_probe, -+ .remove_new = mtk_clk_simple_remove, ++ .remove = mtk_clk_simple_remove, +}; +module_platform_driver(clk_mt7987_infracfg_drv); +MODULE_LICENSE("GPL"); @@ -608,7 +600,6 @@ Signed-off-by: Daniel Golle + * Author: Lu Tang + * Author: Sam Shih + */ -+ +#include +#include +#include @@ -620,6 +611,7 @@ Signed-off-by: Daniel Golle +#include + +static DEFINE_SPINLOCK(mt7987_clk_lock); ++ +static const char *const mcu_bus_div_parents[] = { "cb_cksq_40m", "arm_ll" }; + +static struct mtk_composite mcu_muxes[] = { @@ -645,20 +637,19 @@ Signed-off-by: Daniel Golle + .of_match_table = of_match_clk_mt7987_mcusys, + }, + .probe = mtk_clk_simple_probe, -+ .remove_new = mtk_clk_simple_remove, ++ .remove = mtk_clk_simple_remove, +}; +module_platform_driver(clk_mt7987_mcusys_drv); +MODULE_LICENSE("GPL"); --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7987-topckgen.c -@@ -0,0 +1,311 @@ +@@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 MediaTek Inc. + * Author: Lu Tang + * Author: Sam Shih + */ -+ +#include +#include +#include @@ -955,7 +946,7 @@ Signed-off-by: Daniel Golle + +static struct platform_driver clk_mt7987_topckgen_drv = { + .probe = mtk_clk_simple_probe, -+ .remove_new = mtk_clk_simple_remove, ++ .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt7987-topckgen", + .of_match_table = of_match_clk_mt7987_topckgen, @@ -965,19 +956,16 @@ Signed-off-by: Daniel Golle +MODULE_LICENSE("GPL"); --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt7987-clk.h -@@ -0,0 +1,206 @@ +@@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 MediaTek Inc. + * Author: Lu Tang + * Author: Sam Shih + */ -+ +#ifndef _DT_BINDINGS_CLK_MT7987_H +#define _DT_BINDINGS_CLK_MT7987_H -+ +/* INFRACFG */ -+ +#define CLK_INFRA_MUX_UART0_SEL 0 +#define CLK_INFRA_MUX_UART1_SEL 1 +#define CLK_INFRA_MUX_UART2_SEL 2 @@ -1050,9 +1038,7 @@ Signed-off-by: Daniel Golle +#define CLK_INFRA_PCIE_PERI_26M_CK_P0 69 +#define CLK_INFRA_PCIE_PERI_26M_CK_P1 70 +#define CLK_INFRA_NR_CLK 71 -+ +/* TOPCKGEN */ -+ +#define CLK_TOP_CB_M_D2 0 +#define CLK_TOP_CB_M_D3 1 +#define CLK_TOP_M_D3_D2 2 @@ -1132,9 +1118,7 @@ Signed-off-by: Daniel Golle +#define CLK_TOP_EMMC_200M_SEL 76 +#define CLK_TOP_AUD_I2S_M 77 +#define CLK_TOP_NR_CLK 78 -+ +/* APMIXEDSYS */ -+ +#define CLK_APMIXED_MPLL 0 +#define CLK_APMIXED_APLL2 1 +#define CLK_APMIXED_NET1PLL 2 @@ -1144,26 +1128,18 @@ Signed-off-by: Daniel Golle +#define CLK_APMIXED_ARM_LL 6 +#define CLK_APMIXED_MSDCPLL 7 +#define CLK_APMIXED_NR_CLK 8 -+ +/* MCUSYS */ -+ +#define CLK_MCU_BUS_DIV_SEL 0 +#define CLK_MCU_NR_CLK 1 -+ +/* SGMIISYS_0 */ -+ +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGMII0_NR_CLK 2 -+ +/* SGMIISYS_1 */ -+ +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGMII1_NR_CLK 2 -+ +/* ETHDMA */ -+ +#define CLK_ETHDMA_FE_EN 0 +#define CLK_ETHDMA_GP2_EN 1 +#define CLK_ETHDMA_GP1_EN 2 @@ -1171,12 +1147,10 @@ Signed-off-by: Daniel Golle +#define CLK_ETHDMA_NR_CLK 4 + +#endif /* _DT_BINDINGS_CLK_MT7987_H */ -+ --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt7987-resets.h -@@ -0,0 +1,10 @@ +@@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+ +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7987 +#define _DT_BINDINGS_RESET_CONTROLLER_MT7987 + diff --git a/target/linux/mediatek/patches-6.18/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-6.18/410-bt-mtk-serial-fix.patch index cce3dcadf8..9550723c78 100644 --- a/target/linux/mediatek/patches-6.18/410-bt-mtk-serial-fix.patch +++ b/target/linux/mediatek/patches-6.18/410-bt-mtk-serial-fix.patch @@ -22,7 +22,7 @@ Signed-off-by: John Crispin #define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */ --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c -@@ -276,7 +276,7 @@ static const struct serial8250_config ua +@@ -268,7 +268,7 @@ static const struct serial8250_config ua .tx_loadsz = 16, .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, @@ -31,15 +31,15 @@ Signed-off-by: John Crispin }, [PORT_NPCM] = { .name = "Nuvoton 16550", -@@ -2735,6 +2735,11 @@ serial8250_do_set_termios(struct uart_po - unsigned long flags; - unsigned int baud, quot, frac = 0; +@@ -2766,6 +2766,11 @@ serial8250_do_set_termios(struct uart_po + baud = serial8250_get_baud_rate(port, termios, old); + quot = serial8250_get_divisor(port, baud, &frac); + if (up->capabilities & UART_CAP_NMOD) { + termios->c_cflag = 0; + return; + } + - if (up->capabilities & UART_CAP_MINI) { - termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR); - if ((termios->c_cflag & CSIZE) == CS5 || + /* + * Ok, we're now changing the port state. Do it with interrupts disabled. + * diff --git a/target/linux/mediatek/patches-6.18/411-mtd-spinand-fix-support-for-FORESEE.patch b/target/linux/mediatek/patches-6.18/411-mtd-spinand-fix-support-for-FORESEE.patch index b88c138082..f5f5dc5569 100644 --- a/target/linux/mediatek/patches-6.18/411-mtd-spinand-fix-support-for-FORESEE.patch +++ b/target/linux/mediatek/patches-6.18/411-mtd-spinand-fix-support-for-FORESEE.patch @@ -20,13 +20,13 @@ Signed-off-by: Dim Fish --- a/drivers/mtd/nand/spi/foresee.c +++ b/drivers/mtd/nand/spi/foresee.c @@ -22,8 +22,8 @@ static SPINAND_OP_VARIANTS(write_cache_v - SPINAND_PROG_LOAD(true, 0, NULL, 0)); + SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0)); static SPINAND_OP_VARIANTS(update_cache_variants, -- SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), -- SPINAND_PROG_LOAD(false, 0, NULL, 0)); -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); +- SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0), +- SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); ++ SPINAND_PROG_LOAD_1S_1S_4S_OP(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0)); static int f35sqa002g_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *region) diff --git a/target/linux/mediatek/patches-6.18/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch b/target/linux/mediatek/patches-6.18/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch index 74e9bd9d7a..b292a4f477 100644 --- a/target/linux/mediatek/patches-6.18/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch +++ b/target/linux/mediatek/patches-6.18/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch @@ -21,7 +21,7 @@ Signed-off-by: SkyLake.Huang #include #include #include -@@ -172,6 +171,8 @@ struct mtk_spi { +@@ -175,6 +174,8 @@ struct mtk_spi { struct device *dev; dma_addr_t tx_dma; dma_addr_t rx_dma; @@ -30,8 +30,8 @@ Signed-off-by: SkyLake.Huang }; static const struct mtk_spi_compatible mtk_common_compat; -@@ -217,15 +218,6 @@ static const struct mtk_spi_compatible m - .no_need_unprepare = true, +@@ -228,15 +229,6 @@ static const struct mtk_spi_compatible m + .ipm_design = true, }; -/* @@ -46,15 +46,15 @@ Signed-off-by: SkyLake.Huang static const struct of_device_id mtk_spi_of_match[] = { { .compatible = "mediatek,spi-ipm", .data = (void *)&mtk_ipm_compat, -@@ -353,7 +345,6 @@ static int mtk_spi_hw_init(struct spi_co +@@ -367,7 +359,6 @@ static int mtk_spi_hw_init(struct spi_co { u16 cpha, cpol; u32 reg_val; - struct mtk_chip_config *chip_config = spi->controller_data; struct mtk_spi *mdata = spi_controller_get_devdata(host); - cpha = spi->mode & SPI_CPHA ? 1 : 0; -@@ -403,7 +394,7 @@ static int mtk_spi_hw_init(struct spi_co + cpu_latency_qos_update_request(&mdata->qos_request, 500); +@@ -418,7 +409,7 @@ static int mtk_spi_hw_init(struct spi_co else reg_val &= ~SPI_CMD_CS_POL; @@ -63,7 +63,7 @@ Signed-off-by: SkyLake.Huang reg_val |= SPI_CMD_SAMPLE_SEL; else reg_val &= ~SPI_CMD_SAMPLE_SEL; -@@ -430,20 +421,20 @@ static int mtk_spi_hw_init(struct spi_co +@@ -445,20 +436,20 @@ static int mtk_spi_hw_init(struct spi_co if (mdata->dev_comp->ipm_design) { reg_val = readl(mdata->base + SPI_CMD_REG); reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; @@ -87,7 +87,7 @@ Signed-off-by: SkyLake.Huang << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); writel(reg_val, mdata->base + SPI_CFG1_REG); } -@@ -733,9 +724,6 @@ static int mtk_spi_setup(struct spi_devi +@@ -779,9 +770,6 @@ static int mtk_spi_setup(struct spi_devi { struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); @@ -97,7 +97,7 @@ Signed-off-by: SkyLake.Huang if (mdata->dev_comp->need_pad_sel && spi_get_csgpiod(spi, 0)) /* CS de-asserted, gpiolib will handle inversion */ gpiod_direction_output(spi_get_csgpiod(spi, 0), 0); -@@ -1146,6 +1134,11 @@ static int mtk_spi_probe(struct platform +@@ -1197,6 +1185,11 @@ static int mtk_spi_probe(struct platform host->use_gpio_descriptors = true; mdata = spi_controller_get_devdata(host); diff --git a/target/linux/mediatek/patches-6.18/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-6.18/432-drivers-spi-Add-support-for-dynamic-calibration.patch index 4e51dc21c6..0ebef7abba 100644 --- a/target/linux/mediatek/patches-6.18/432-drivers-spi-Add-support-for-dynamic-calibration.patch +++ b/target/linux/mediatek/patches-6.18/432-drivers-spi-Add-support-for-dynamic-calibration.patch @@ -11,7 +11,7 @@ Signed-off-by: SkyLake.Huang --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c -@@ -1489,6 +1489,70 @@ static int spi_transfer_wait(struct spi_ +@@ -1476,6 +1476,70 @@ static int spi_transfer_wait(struct spi_ return 0; } @@ -82,7 +82,7 @@ Signed-off-by: SkyLake.Huang static void _spi_transfer_delay_ns(u32 ns) { if (!ns) -@@ -2347,6 +2411,75 @@ void spi_flush_queue(struct spi_controll +@@ -2330,6 +2394,75 @@ void spi_flush_queue(struct spi_controll /*-------------------------------------------------------------------------*/ #if defined(CONFIG_OF) @@ -158,7 +158,7 @@ Signed-off-by: SkyLake.Huang static void of_spi_parse_dt_cs_delay(struct device_node *nc, struct spi_delay *delay, const char *prop) { -@@ -2511,6 +2644,10 @@ of_register_spi_device(struct spi_contro +@@ -2485,6 +2618,10 @@ of_register_spi_device(struct spi_contro if (rc) goto err_out; @@ -171,7 +171,7 @@ Signed-off-by: SkyLake.Huang --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h -@@ -348,6 +348,40 @@ struct spi_driver { +@@ -352,6 +352,40 @@ struct spi_driver { struct device_driver driver; }; @@ -212,7 +212,7 @@ Signed-off-by: SkyLake.Huang #define to_spi_driver(__drv) \ ( __drv ? container_of_const(__drv, struct spi_driver, driver) : NULL ) -@@ -754,6 +788,11 @@ struct spi_controller { +@@ -771,6 +805,11 @@ struct spi_controller { void *dummy_rx; void *dummy_tx; @@ -224,7 +224,7 @@ Signed-off-by: SkyLake.Huang int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); /* -@@ -1657,6 +1696,9 @@ spi_register_board_info(struct spi_board +@@ -1687,6 +1726,9 @@ spi_register_board_info(struct spi_board { return 0; } #endif diff --git a/target/linux/mediatek/patches-6.18/433-drivers-spi-mem-Add-spi-calibration-hook.patch b/target/linux/mediatek/patches-6.18/433-drivers-spi-mem-Add-spi-calibration-hook.patch index 60c8f81925..e7b916e169 100644 --- a/target/linux/mediatek/patches-6.18/433-drivers-spi-mem-Add-spi-calibration-hook.patch +++ b/target/linux/mediatek/patches-6.18/433-drivers-spi-mem-Add-spi-calibration-hook.patch @@ -11,7 +11,7 @@ Signed-off-by: SkyLake.Huang --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c -@@ -497,6 +497,14 @@ int spi_mem_exec_op(struct spi_mem *mem, +@@ -511,6 +511,14 @@ int spi_mem_exec_op(struct spi_mem *mem, } EXPORT_SYMBOL_GPL(spi_mem_exec_op); @@ -28,7 +28,7 @@ Signed-off-by: SkyLake.Huang * upper layer if necessary --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h -@@ -390,6 +390,10 @@ bool spi_mem_supports_op(struct spi_mem +@@ -432,6 +432,10 @@ bool spi_mem_supports_op(struct spi_mem int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op); diff --git a/target/linux/mediatek/patches-6.18/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch b/target/linux/mediatek/patches-6.18/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch index a7815d5ead..cff216ef9d 100644 --- a/target/linux/mediatek/patches-6.18/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch +++ b/target/linux/mediatek/patches-6.18/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch @@ -11,7 +11,7 @@ Signed-off-by: SkyLake.Huang --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c -@@ -842,6 +842,21 @@ static irqreturn_t mtk_spi_interrupt(int +@@ -888,6 +888,21 @@ static irqreturn_t mtk_spi_interrupt(int return IRQ_WAKE_THREAD; } @@ -33,7 +33,7 @@ Signed-off-by: SkyLake.Huang static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { -@@ -1132,6 +1147,7 @@ static int mtk_spi_probe(struct platform +@@ -1183,6 +1198,7 @@ static int mtk_spi_probe(struct platform host->setup = mtk_spi_setup; host->set_cs_timing = mtk_spi_set_hw_cs_timing; host->use_gpio_descriptors = true; diff --git a/target/linux/mediatek/patches-6.18/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch b/target/linux/mediatek/patches-6.18/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch index b33315f164..035986dbbd 100644 --- a/target/linux/mediatek/patches-6.18/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch +++ b/target/linux/mediatek/patches-6.18/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch @@ -11,14 +11,14 @@ Signed-off-by: SkyLake.Huang --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -1228,6 +1228,56 @@ static int spinand_manufacturer_match(st +@@ -1279,6 +1279,56 @@ static int spinand_manufacturer_match(st return -EOPNOTSUPP; } +static int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) { + struct spinand_device *spinand = (struct spinand_device *)priv; + struct device *dev = &spinand->spimem->spi->dev; -+ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen); ++ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, buf, readlen, 0); + struct nand_pos pos; + struct nand_page_io_req req; + u8 status; @@ -68,7 +68,7 @@ Signed-off-by: SkyLake.Huang static int spinand_id_detect(struct spinand_device *spinand) { u8 *id = spinand->id.data; -@@ -1481,6 +1531,10 @@ static int spinand_init(struct spinand_d +@@ -1555,6 +1605,10 @@ static int spinand_init(struct spinand_d if (!spinand->scratchbuf) return -ENOMEM; diff --git a/target/linux/mediatek/patches-6.18/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch b/target/linux/mediatek/patches-6.18/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch index 04fa9eeb04..0a2ee86a61 100644 --- a/target/linux/mediatek/patches-6.18/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch +++ b/target/linux/mediatek/patches-6.18/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch @@ -12,7 +12,7 @@ Signed-off-by: SkyLake.Huang --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -1269,7 +1269,10 @@ static int spinand_cal_read(void *priv, +@@ -1320,7 +1320,10 @@ static int spinand_cal_read(void *priv, if (ret) return ret; @@ -26,7 +26,7 @@ Signed-off-by: SkyLake.Huang --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c -@@ -3441,6 +3441,18 @@ static const struct flash_info *spi_nor_ +@@ -3418,6 +3418,18 @@ static const struct flash_info *spi_nor_ return NULL; } @@ -45,7 +45,7 @@ Signed-off-by: SkyLake.Huang static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, const char *name) { -@@ -3615,6 +3627,9 @@ int spi_nor_scan(struct spi_nor *nor, co +@@ -3592,6 +3604,9 @@ int spi_nor_scan(struct spi_nor *nor, co if (ret) return ret; diff --git a/target/linux/mediatek/patches-6.18/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-6.18/500-gsw-rtl8367s-mt7622-support.patch index c558ce3537..ed560c21c7 100644 --- a/target/linux/mediatek/patches-6.18/500-gsw-rtl8367s-mt7622-support.patch +++ b/target/linux/mediatek/patches-6.18/500-gsw-rtl8367s-mt7622-support.patch @@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau --- --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -443,6 +443,12 @@ config ROCKCHIP_PHY +@@ -470,6 +470,12 @@ config ROCKCHIP_PHY help Currently supports the integrated Ethernet PHY. @@ -26,7 +26,7 @@ Signed-off-by: Felix Fietkau select CRC16 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -113,6 +113,7 @@ obj-$(CONFIG_REALTEK_PHY) += realtek/ +@@ -109,6 +109,7 @@ obj-$(CONFIG_REALTEK_PHY) += realtek/ obj-y += rtl8261n/ obj-$(CONFIG_RENESAS_PHY) += uPD60620.o obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o diff --git a/target/linux/mediatek/patches-6.18/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/target/linux/mediatek/patches-6.18/610-pcie-mediatek-fix-clearing-interrupt-status.patch index e31e02d2c2..ab4ce2dc92 100644 --- a/target/linux/mediatek/patches-6.18/610-pcie-mediatek-fix-clearing-interrupt-status.patch +++ b/target/linux/mediatek/patches-6.18/610-pcie-mediatek-fix-clearing-interrupt-status.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c -@@ -601,9 +601,9 @@ static void mtk_pcie_intr_handler(struct +@@ -597,9 +597,9 @@ static void mtk_pcie_intr_handler(struct if (status & INTX_MASK) { for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { /* Clear the INTx */ diff --git a/target/linux/mediatek/patches-6.18/611-pcie-mediatek-gen3-PERST-for-100ms.patch b/target/linux/mediatek/patches-6.18/611-pcie-mediatek-gen3-PERST-for-100ms.patch deleted file mode 100644 index f3d308a294..0000000000 --- a/target/linux/mediatek/patches-6.18/611-pcie-mediatek-gen3-PERST-for-100ms.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 6a2e17d5c1451025396ba523e9f2d112212c7261 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 3 Oct 2023 02:32:35 +0100 -Subject: [PATCH] mediatek: fix PCIe #PERST being de-asserted too early - -The driver for MediaTek gen3 PCIe hosts de-asserts all reset -signals at the same time using a single register write operation. -Delay the de-assertion of the #PERST signal by 100ms as some PCIe -devices fail to come up otherwise. - -Signed-off-by: Daniel Golle ---- ---- a/drivers/pci/controller/pcie-mediatek-gen3.c -+++ b/drivers/pci/controller/pcie-mediatek-gen3.c -@@ -416,7 +416,13 @@ static int mtk_pcie_startup_port(struct - msleep(100); - - /* De-assert reset signals */ -- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); -+ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB); -+ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); -+ -+ msleep(100); -+ -+ /* De-assert PERST# signals */ -+ val &= ~(PCIE_PE_RSTB); - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); - - /* Check if the link is up or not */ diff --git a/target/linux/mediatek/patches-6.18/700-net-phy-mediatek-Add-2.5Gphy-firmware-dt-bindings-an.patch b/target/linux/mediatek/patches-6.18/700-net-phy-mediatek-Add-2.5Gphy-firmware-dt-bindings-an.patch deleted file mode 100644 index 9996501427..0000000000 --- a/target/linux/mediatek/patches-6.18/700-net-phy-mediatek-Add-2.5Gphy-firmware-dt-bindings-an.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 955a80b20fad77dd73ec17ab64d7eb8014cb59c7 Mon Sep 17 00:00:00 2001 -From: Sky Huang -Date: Wed, 19 Feb 2025 16:39:08 +0800 -Subject: [PATCH 19/20] net: phy: mediatek: Add 2.5Gphy firmware dt-bindings - and dts node - -Add 2.5Gphy firmware dt-bindings and dts node since mtk-2p5ge -driver requires firmware to run. Also, update MAINTAINERS for -MediaTek's built-in 2.5Gphy dt-bindings and change MAINTAINER's name. - -Signed-off-by: Sky Huang ---- - .../bindings/net/mediatek,2p5gphy-fw.yaml | 37 +++++++++++++++++++ - MAINTAINERS | 3 +- - 2 files changed, 39 insertions(+), 1 deletion(-) - create mode 100644 Documentation/devicetree/bindings/net/mediatek,2p5gphy-fw.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/mediatek,2p5gphy-fw.yaml -@@ -0,0 +1,37 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/mediatek,2p5gphy-fw.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek Built-in 2.5G Ethernet PHY -+ -+maintainers: -+ - Sky Huang -+ -+description: | -+ MediaTek Built-in 2.5G Ethernet PHY needs to load firmware so it can -+ run correctly. -+ -+properties: -+ compatible: -+ const: "mediatek,2p5gphy-fw" -+ -+ reg: -+ items: -+ - description: pmb firmware load address -+ - description: firmware trigger register -+ -+required: -+ - compatible -+ - reg -+ -+additionalProperties: false -+ -+examples: -+ - | -+ phyfw: phy-firmware@f000000 { -+ compatible = "mediatek,2p5gphy-fw"; -+ reg = <0 0x0f100000 0 0x20000>, -+ <0 0x0f0f0018 0 0x20>; -+ }; ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -14439,9 +14439,10 @@ F: include/linux/pcs/pcs-mtk-usxgmii.h - MEDIATEK ETHERNET PHY DRIVERS - M: Daniel Golle - M: Qingfang Deng --M: SkyLake Huang -+M: Sky Huang - L: netdev@vger.kernel.org - S: Maintained -+F: Documentation/devicetree/bindings/net/mediatek,2p5gphy-fw.yaml - F: drivers/net/phy/mediatek/mtk-ge-soc.c - F: drivers/net/phy/mediatek/mtk-phy-lib.c - F: drivers/net/phy/mediatek/mtk-ge.c diff --git a/target/linux/mediatek/patches-6.18/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch b/target/linux/mediatek/patches-6.18/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch deleted file mode 100644 index ff7aa40f53..0000000000 --- a/target/linux/mediatek/patches-6.18/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch +++ /dev/null @@ -1,399 +0,0 @@ -From 4eb44972db02c2b704f0ef5c891f29f25440a063 Mon Sep 17 00:00:00 2001 -From: Sky Huang -Date: Wed, 19 Feb 2025 16:39:10 +0800 -Subject: [PATCH 20/20] net: phy: mediatek: add driver for built-in 2.5G - ethernet PHY on MT7988 - -Add support for internal 2.5Gphy on MT7988. This driver will load -necessary firmware and add appropriate time delay to make sure -that firmware works stably. Also, certain control registers will -be set to fix link-up issues. - -Signed-off-by: Sky Huang ---- - MAINTAINERS | 1 + - drivers/net/phy/mediatek/Kconfig | 11 + - drivers/net/phy/mediatek/Makefile | 1 + - drivers/net/phy/mediatek/mtk-2p5ge.c | 342 +++++++++++++++++++++++++++ - 4 files changed, 355 insertions(+) - create mode 100644 drivers/net/phy/mediatek/mtk-2p5ge.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -14443,6 +14443,7 @@ M: Sky Huang -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "mtk.h" -+ -+#define MTK_2P5GPHY_ID_MT7988 (0x00339c11) -+ -+#define MT7988_2P5GE_PMB_FW "mediatek/mt7988/i2p5ge-phy-pmb.bin" -+#define MT7988_2P5GE_PMB_FW_SIZE (0x20000) -+#define MD32_EN_CFG (0x18) -+#define MD32_EN BIT(0) -+ -+#define BASE100T_STATUS_EXTEND (0x10) -+#define BASE1000T_STATUS_EXTEND (0x11) -+#define EXTEND_CTRL_AND_STATUS (0x16) -+ -+#define PHY_AUX_CTRL_STATUS (0x1d) -+#define PHY_AUX_DPX_MASK GENMASK(5, 5) -+#define PHY_AUX_SPEED_MASK GENMASK(4, 2) -+ -+/* Registers on MDIO_MMD_VEND1 */ -+#define MTK_PHY_LPI_PCS_DSP_CTRL (0x121) -+#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8) -+ -+#define MTK_PHY_HOST_CMD1 0x800e -+#define MTK_PHY_HOST_CMD2 0x800f -+/* Registers on Token Ring debug nodes */ -+/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */ -+#define AUTO_NP_10XEN BIT(6) -+ -+struct mtk_i2p5ge_phy_priv { -+ bool fw_loaded; -+}; -+ -+enum { -+ PHY_AUX_SPD_10 = 0, -+ PHY_AUX_SPD_100, -+ PHY_AUX_SPD_1000, -+ PHY_AUX_SPD_2500, -+}; -+ -+static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev) -+{ -+ struct mtk_i2p5ge_phy_priv *priv = phydev->priv; -+ void __iomem *mcu_csr_base, *pmb_addr; -+ struct device *dev = &phydev->mdio.dev; -+ const struct firmware *fw; -+ struct device_node *np; -+ int ret, i; -+ u32 reg; -+ -+ np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw"); -+ if (!np) -+ return -ENOENT; -+ -+ pmb_addr = of_iomap(np, 0); -+ if (!pmb_addr) -+ return -ENOMEM; -+ mcu_csr_base = of_iomap(np, 1); -+ if (!mcu_csr_base) { -+ ret = -ENOMEM; -+ goto free_pmb; -+ } -+ -+ ret = request_firmware(&fw, MT7988_2P5GE_PMB_FW, dev); -+ if (ret) { -+ dev_err(dev, "failed to load firmware: %s, ret: %d\n", -+ MT7988_2P5GE_PMB_FW, ret); -+ goto free; -+ } -+ -+ if (fw->size != MT7988_2P5GE_PMB_FW_SIZE) { -+ dev_err(dev, "Firmware size 0x%zx != 0x%x\n", -+ fw->size, MT7988_2P5GE_PMB_FW_SIZE); -+ ret = -EINVAL; -+ goto release_fw; -+ } -+ -+ reg = readw(mcu_csr_base + MD32_EN_CFG); -+ if (reg & MD32_EN) { -+ phy_set_bits(phydev, MII_BMCR, BMCR_RESET); -+ usleep_range(10000, 11000); -+ } -+ phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); -+ -+ /* Write magic number to safely stall MCU */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD1, 0x1100); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD2, 0x00df); -+ -+ for (i = 0; i < MT7988_2P5GE_PMB_FW_SIZE - 1; i += 4) -+ writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); -+ -+ if (!priv->fw_loaded) -+ dev_info(dev, "Firmware date code: %x/%x/%x, version: %x.%x\n", -+ be16_to_cpu(*((__be16 *)(fw->data + -+ MT7988_2P5GE_PMB_FW_SIZE - 8))), -+ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 6), -+ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 5), -+ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 2), -+ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 1)); -+ -+ writew(reg & ~MD32_EN, mcu_csr_base + MD32_EN_CFG); -+ writew(reg | MD32_EN, mcu_csr_base + MD32_EN_CFG); -+ phy_set_bits(phydev, MII_BMCR, BMCR_RESET); -+ /* We need a delay here to stabilize initialization of MCU */ -+ usleep_range(7000, 8000); -+ -+ priv->fw_loaded = true; -+ -+release_fw: -+ release_firmware(fw); -+free: -+ iounmap(mcu_csr_base); -+free_pmb: -+ iounmap(pmb_addr); -+ -+ return ret; -+} -+ -+static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev) -+{ -+ struct pinctrl *pinctrl; -+ int ret; -+ -+ /* Check if PHY interface type is compatible */ -+ if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL) -+ return -ENODEV; -+ -+ ret = mt798x_2p5ge_phy_load_fw(phydev); -+ if (ret < 0) -+ return ret; -+ -+ /* Setup LED */ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, -+ MTK_PHY_LED_ON_POLARITY | MTK_PHY_LED_ON_LINK10 | -+ MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK1000 | -+ MTK_PHY_LED_ON_LINK2500); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, -+ MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX); -+ -+ /* Switch pinctrl after setting polarity to avoid bogus blinking */ -+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led"); -+ if (IS_ERR(pinctrl) && PTR_ERR(pinctrl) != -ENODEV) -+ dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n"); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL, -+ MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0); -+ -+ /* Enable 16-bit next page exchange bit if 1000-BT isn't advertising */ -+ mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, AUTO_NP_10XEN, -+ FIELD_PREP(AUTO_NP_10XEN, 0x1)); -+ -+ /* Enable HW auto downshift */ -+ phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1, -+ MTK_PHY_AUX_CTRL_AND_STATUS, -+ 0, MTK_PHY_ENABLE_DOWNSHIFT); -+ -+ return 0; -+} -+ -+static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev) -+{ -+ bool changed = false; -+ u32 adv; -+ int ret; -+ -+ ret = genphy_c45_an_config_aneg(phydev); -+ if (ret < 0) -+ return ret; -+ if (ret > 0) -+ changed = true; -+ -+ /* Clause 45 doesn't define 1000BaseT support. Use Clause 22 instead in -+ * our design. -+ */ -+ adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); -+ ret = phy_modify_changed(phydev, MII_CTRL1000, ADVERTISE_1000FULL, adv); -+ if (ret < 0) -+ return ret; -+ if (ret > 0) -+ changed = true; -+ -+ return __genphy_config_aneg(phydev, changed); -+} -+ -+static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) -+{ -+ int ret; -+ -+ ret = genphy_c45_pma_read_abilities(phydev); -+ if (ret) -+ return ret; -+ -+ /* This phy can't handle collision, and neither can (XFI)MAC it's -+ * connected to. Although it can do HDX handshake, it doesn't support -+ * CSMA/CD that HDX requires. -+ */ -+ linkmode_clear_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, -+ phydev->supported); -+ -+ return 0; -+} -+ -+static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) -+{ -+ int ret; -+ -+ /* When MDIO_STAT1_LSTATUS is raised genphy_c45_read_link(), this phy -+ * actually hasn't finished AN. So use CL22's link update function -+ * instead. -+ */ -+ ret = genphy_update_link(phydev); -+ if (ret) -+ return ret; -+ -+ phydev->speed = SPEED_UNKNOWN; -+ phydev->duplex = DUPLEX_UNKNOWN; -+ phydev->pause = 0; -+ phydev->asym_pause = 0; -+ -+ /* We'll read link speed through vendor specific registers down below. -+ * So remove phy_resolve_aneg_linkmode (AN on) & genphy_c45_read_pma -+ * (AN off). -+ */ -+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { -+ ret = genphy_c45_read_lpa(phydev); -+ if (ret < 0) -+ return ret; -+ -+ /* Clause 45 doesn't define 1000BaseT support. Read the link -+ * partner's 1G advertisement via Clause 22. -+ */ -+ ret = phy_read(phydev, MII_STAT1000); -+ if (ret < 0) -+ return ret; -+ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); -+ } else if (phydev->autoneg == AUTONEG_DISABLE) { -+ linkmode_zero(phydev->lp_advertising); -+ } -+ -+ if (phydev->link) { -+ ret = phy_read(phydev, PHY_AUX_CTRL_STATUS); -+ if (ret < 0) -+ return ret; -+ -+ switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) { -+ case PHY_AUX_SPD_10: -+ phydev->speed = SPEED_10; -+ break; -+ case PHY_AUX_SPD_100: -+ phydev->speed = SPEED_100; -+ break; -+ case PHY_AUX_SPD_1000: -+ phydev->speed = SPEED_1000; -+ break; -+ case PHY_AUX_SPD_2500: -+ phydev->speed = SPEED_2500; -+ break; -+ } -+ -+ phydev->duplex = DUPLEX_FULL; -+ /* FIXME: -+ * The current firmware always enables rate adaptation mode. -+ */ -+ phydev->rate_matching = RATE_MATCH_PAUSE; -+ } -+ -+ return 0; -+} -+ -+static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device *phydev, -+ phy_interface_t iface) -+{ -+ return RATE_MATCH_PAUSE; -+} -+ -+static int mt798x_2p5ge_phy_probe(struct phy_device *phydev) -+{ -+ struct mtk_i2p5ge_phy_priv *priv; -+ -+ priv = devm_kzalloc(&phydev->mdio.dev, -+ sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ switch (phydev->drv->phy_id) { -+ case MTK_2P5GPHY_ID_MT7988: -+ /* The original hardware only sets MDIO_DEVS_PMAPMD */ -+ phydev->c45_ids.mmds_present |= MDIO_DEVS_PCS | -+ MDIO_DEVS_AN | -+ MDIO_DEVS_VEND1 | -+ MDIO_DEVS_VEND2; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ priv->fw_loaded = false; -+ phydev->priv = priv; -+ -+ return 0; -+} -+ -+static struct phy_driver mtk_2p5gephy_driver[] = { -+ { -+ PHY_ID_MATCH_MODEL(MTK_2P5GPHY_ID_MT7988), -+ .name = "MediaTek MT7988 2.5GbE PHY", -+ .probe = mt798x_2p5ge_phy_probe, -+ .config_init = mt798x_2p5ge_phy_config_init, -+ .config_aneg = mt798x_2p5ge_phy_config_aneg, -+ .get_features = mt798x_2p5ge_phy_get_features, -+ .read_status = mt798x_2p5ge_phy_read_status, -+ .get_rate_matching = mt798x_2p5ge_phy_get_rate_matching, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_page = mtk_phy_read_page, -+ .write_page = mtk_phy_write_page, -+ }, -+}; -+ -+module_phy_driver(mtk_2p5gephy_driver); -+ -+static const struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = { -+ { PHY_ID_MATCH_VENDOR(0x00339c00) }, -+ { } -+}; -+ -+MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver"); -+MODULE_AUTHOR("SkyLake Huang "); -+MODULE_LICENSE("GPL"); -+ -+MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl); -+MODULE_FIRMWARE(MT7988_2P5GE_PMB_FW); diff --git a/target/linux/mediatek/patches-6.18/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-6.18/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch index 1642cfe22a..fa3d2ffe2a 100644 --- a/target/linux/mediatek/patches-6.18/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ b/target/linux/mediatek/patches-6.18/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch @@ -41,7 +41,7 @@ Signed-off-by: Felix Fietkau }; --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c -@@ -20,6 +20,7 @@ +@@ -21,6 +21,7 @@ #include #include #include @@ -49,7 +49,7 @@ Signed-off-by: Felix Fietkau #include #include #include -@@ -139,6 +140,11 @@ +@@ -140,6 +141,11 @@ #define PCIE_LINK_STATUS_V2 0x804 #define PCIE_PORT_LINKUP_V2 BIT(10) @@ -61,7 +61,7 @@ Signed-off-by: Felix Fietkau struct mtk_pcie_port; /** -@@ -1047,6 +1053,27 @@ static int mtk_pcie_setup(struct mtk_pci +@@ -1043,6 +1049,27 @@ static int mtk_pcie_setup(struct mtk_pci struct mtk_pcie_port *port, *tmp; int err, slot; @@ -88,4 +88,4 @@ Signed-off-by: Felix Fietkau + slot = of_get_pci_domain_nr(dev->of_node); if (slot < 0) { - for_each_available_child_of_node(node, child) { + for_each_available_child_of_node_scoped(node, child) { diff --git a/target/linux/mediatek/patches-6.18/722-remove-300Hz-to-prevent-freeze.patch b/target/linux/mediatek/patches-6.18/722-remove-300MHz-to-prevent-freeze.patch similarity index 100% rename from target/linux/mediatek/patches-6.18/722-remove-300Hz-to-prevent-freeze.patch rename to target/linux/mediatek/patches-6.18/722-remove-300MHz-to-prevent-freeze.patch diff --git a/target/linux/mediatek/patches-6.18/734-net-phy-add-Airoha-EN8801SC-PHY.patch b/target/linux/mediatek/patches-6.18/734-net-phy-add-Airoha-EN8801SC-PHY.patch index 4ebaffd1dd..aba9c8926f 100644 --- a/target/linux/mediatek/patches-6.18/734-net-phy-add-Airoha-EN8801SC-PHY.patch +++ b/target/linux/mediatek/patches-6.18/734-net-phy-add-Airoha-EN8801SC-PHY.patch @@ -14,7 +14,7 @@ Signed-off-by: Robert Marko --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -165,6 +165,11 @@ config AS21XXX_PHY +@@ -170,6 +170,11 @@ config AS21XXX_PHY AS21210PB1 that all register with the PHY ID 0x7500 0x7500 before the firmware is loaded. @@ -28,7 +28,7 @@ Signed-off-by: Robert Marko help --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -50,6 +50,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m) +@@ -44,6 +44,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m) obj-$(CONFIG_ADIN_PHY) += adin.o obj-$(CONFIG_ADIN1100_PHY) += adin1100.o diff --git a/target/linux/mediatek/patches-6.18/737-net-dsa-add-Airoha-AN8855.patch b/target/linux/mediatek/patches-6.18/737-net-dsa-add-Airoha-AN8855.patch index 188540591e..325ea35223 100644 --- a/target/linux/mediatek/patches-6.18/737-net-dsa-add-Airoha-AN8855.patch +++ b/target/linux/mediatek/patches-6.18/737-net-dsa-add-Airoha-AN8855.patch @@ -213,20 +213,18 @@ Christian Marangi (9): + source "drivers/net/dsa/hirschmann/Kconfig" - config NET_DSA_LANTIQ_GSWIP + source "drivers/net/dsa/lantiq/Kconfig" --- a/drivers/net/dsa/Makefile +++ b/drivers/net/dsa/Makefile -@@ -6,6 +6,7 @@ ifdef CONFIG_NET_DSA_LOOP - obj-$(CONFIG_FIXED_PHY) += dsa_loop_bdinfo.o - endif - obj-$(CONFIG_NET_DSA_KS8995) += ks8995.o +@@ -1,4 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_NET_DSA_AN8855) += an8855.o - obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o - obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o - obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o + obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm-sf2.o + bcm-sf2-objs := bcm_sf2.o bcm_sf2_cfp.o + obj-$(CONFIG_NET_DSA_LOOP) += dsa_loop.o --- a/drivers/net/mdio/Kconfig +++ b/drivers/net/mdio/Kconfig -@@ -61,6 +61,15 @@ config MDIO_XGENE +@@ -44,6 +44,15 @@ config MDIO_XGENE This module provides a driver for the MDIO busses found in the APM X-Gene SoC's. @@ -244,17 +242,17 @@ Christian Marangi (9): depends on ARCH_ASPEED || COMPILE_TEST --- a/drivers/net/mdio/Makefile +++ b/drivers/net/mdio/Makefile -@@ -5,6 +5,7 @@ obj-$(CONFIG_ACPI_MDIO) += acpi_mdio.o - obj-$(CONFIG_FWNODE_MDIO) += fwnode_mdio.o +@@ -6,6 +6,7 @@ obj-$(CONFIG_FWNODE_MDIO) += fwnode_mdio obj-$(CONFIG_OF_MDIO) += of_mdio.o + obj-$(CONFIG_MDIO_AIROHA) += mdio-airoha.o +obj-$(CONFIG_MDIO_AN8855) += mdio-an8855.o obj-$(CONFIG_MDIO_ASPEED) += mdio-aspeed.o obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -170,6 +170,11 @@ config AIROHA_EN8801SC_PHY +@@ -175,6 +175,11 @@ config AIROHA_EN8801SC_PHY help Currently supports the Airoha EN8801SC PHY. @@ -268,7 +266,7 @@ Christian Marangi (9): help --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -51,6 +51,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m) +@@ -45,6 +45,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m) obj-$(CONFIG_ADIN_PHY) += adin.o obj-$(CONFIG_ADIN1100_PHY) += adin1100.o obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o @@ -276,34 +274,3 @@ Christian Marangi (9): obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o obj-$(CONFIG_AMD_PHY) += amd.o obj-$(CONFIG_AMCC_QT2025_PHY) += qt2025.o ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -29,6 +29,17 @@ source "drivers/nvmem/layouts/Kconfig" - - # Devices - -+config NVMEM_AN8855_EFUSE -+ tristate "Airoha AN8855 eFuse support" -+ depends on MFD_AIROHA_AN8855 || COMPILE_TEST -+ help -+ Say y here to enable support for reading eFuses on Airoha AN8855 -+ Switch. These are e.g. used to store factory programmed -+ calibration data required for the PHY. -+ -+ This driver can also be built as a module. If so, the module will -+ be called nvmem-an8855-efuse. -+ - config NVMEM_APPLE_EFUSES - tristate "Apple eFuse support" - depends on ARCH_APPLE || COMPILE_TEST ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -10,6 +10,8 @@ nvmem_layouts-y := layouts.o - obj-y += layouts/ - - # Devices -+obj-$(CONFIG_NVMEM_AN8855_EFUSE) += nvmem-an8855-efuse.o -+nvmem-an8855-efuse-y := an8855-efuse.o - obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o - nvmem-apple-efuses-y := apple-efuses.o - obj-$(CONFIG_NVMEM_BCM_OCOTP) += nvmem-bcm-ocotp.o diff --git a/target/linux/mediatek/patches-6.18/740-net-pcs-mtk_lynxi-add-mt7987-support.patch b/target/linux/mediatek/patches-6.18/740-net-pcs-mtk_lynxi-add-mt7987-support.patch index d4d09b64fd..dffa05c00d 100644 --- a/target/linux/mediatek/patches-6.18/740-net-pcs-mtk_lynxi-add-mt7987-support.patch +++ b/target/linux/mediatek/patches-6.18/740-net-pcs-mtk_lynxi-add-mt7987-support.patch @@ -10,7 +10,7 @@ Signed-off-by: Bo-Cun Chen --- a/drivers/net/pcs/pcs-mtk-lynxi.c +++ b/drivers/net/pcs/pcs-mtk-lynxi.c -@@ -413,9 +413,12 @@ static int mtk_pcs_lynxi_probe(struct pl +@@ -416,9 +416,12 @@ static int mtk_pcs_lynxi_probe(struct pl if (of_property_read_bool(np->parent, "mediatek,pnswap")) flags |= MTK_SGMII_FLAG_PN_SWAP; @@ -26,7 +26,7 @@ Signed-off-by: Bo-Cun Chen reset_control_deassert(mpcs->rstc); mpcs->sgmii_sel = devm_clk_get_enabled(dev, "sgmii_sel"); -@@ -462,6 +465,7 @@ static void mtk_pcs_lynxi_remove(struct +@@ -465,6 +468,7 @@ static void mtk_pcs_lynxi_remove(struct } static const struct of_device_id mtk_pcs_lynxi_of_match[] = { diff --git a/target/linux/mediatek/patches-6.18/741-net-pcs-mtk-lynxi-add-phya-tx-rx-clock-path.patch b/target/linux/mediatek/patches-6.18/741-net-pcs-mtk-lynxi-add-phya-tx-rx-clock-path.patch index eef6e361a9..67f2ddc496 100644 --- a/target/linux/mediatek/patches-6.18/741-net-pcs-mtk-lynxi-add-phya-tx-rx-clock-path.patch +++ b/target/linux/mediatek/patches-6.18/741-net-pcs-mtk-lynxi-add-phya-tx-rx-clock-path.patch @@ -67,7 +67,7 @@ Signed-off-by: Bo-Cun Chen /* Release PHYA power down state * Only removing bit SGMII_PHYA_PWD isn't enough. -@@ -413,6 +424,9 @@ static int mtk_pcs_lynxi_probe(struct pl +@@ -416,6 +427,9 @@ static int mtk_pcs_lynxi_probe(struct pl if (of_property_read_bool(np->parent, "mediatek,pnswap")) flags |= MTK_SGMII_FLAG_PN_SWAP; diff --git a/target/linux/mediatek/patches-6.18/750-net-ethernet-mtk_eth_soc-add-mt7987-support.patch b/target/linux/mediatek/patches-6.18/750-net-ethernet-mtk_eth_soc-add-mt7987-support.patch index d27425592c..a9184c7021 100644 --- a/target/linux/mediatek/patches-6.18/750-net-ethernet-mtk_eth_soc-add-mt7987-support.patch +++ b/target/linux/mediatek/patches-6.18/750-net-ethernet-mtk_eth_soc-add-mt7987-support.patch @@ -31,7 +31,7 @@ Signed-off-by: Bo-Cun Chen if (MTK_HAS_CAPS(eth->soc->caps, MTK_U3_COPHY_V2)) { reg = USB_PHY_SWITCH_REG; val = SGMII_QPHY_SEL; -@@ -281,9 +282,9 @@ static const struct mtk_eth_muxc mtk_eth +@@ -283,9 +284,9 @@ static const struct mtk_eth_muxc mtk_eth .cap_bit = MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY, .set_path = set_mux_gmac2_gmac0_to_gephy, }, { @@ -46,7 +46,7 @@ Signed-off-by: Bo-Cun Chen .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY, --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -817,10 +817,16 @@ static void mtk_set_queue_speed(struct m +@@ -834,10 +834,16 @@ static void mtk_set_queue_speed(struct m return; val = MTK_QTX_SCH_MIN_RATE_EN | @@ -66,7 +66,7 @@ Signed-off-by: Bo-Cun Chen if (mtk_is_netsys_v1(eth)) val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; -@@ -847,6 +853,30 @@ static void mtk_set_queue_speed(struct m +@@ -864,6 +870,30 @@ static void mtk_set_queue_speed(struct m default: break; } @@ -97,16 +97,16 @@ Signed-off-by: Bo-Cun Chen } else { switch (speed) { case SPEED_10: -@@ -935,7 +965,7 @@ static void mtk_xgdm_mac_link_up(struct +@@ -944,7 +974,7 @@ static void mtk_xgdm_mac_link_up(struct return; /* Eliminate the interference(before link-up) caused by PHY noise */ - mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id)); + mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->hw, mac->id)); mdelay(20); - mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR, MTK_XMAC_CNT_CTRL(mac->id)); - -@@ -2908,10 +2938,16 @@ static int mtk_tx_alloc(struct mtk_eth * + mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR, + MTK_XMAC_CNT_CTRL(mac->id)); +@@ -2984,10 +3014,16 @@ static int mtk_tx_alloc(struct mtk_eth * mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); val = MTK_QTX_SCH_MIN_RATE_EN | @@ -126,7 +126,7 @@ Signed-off-by: Bo-Cun Chen if (mtk_is_netsys_v1(eth)) val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); -@@ -5892,6 +5928,36 @@ static const struct mtk_soc_data mt7986_ +@@ -5969,6 +6005,36 @@ static const struct mtk_soc_data mt7986_ }, }; @@ -163,7 +163,7 @@ Signed-off-by: Bo-Cun Chen static const struct mtk_soc_data mt7988_data = { .reg_map = &mt7988_reg_map, .ana_rgc3 = 0x128, -@@ -5953,6 +6019,7 @@ const struct of_device_id of_mtk_match[] +@@ -6030,6 +6096,7 @@ const struct of_device_id of_mtk_match[] { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, @@ -173,7 +173,7 @@ Signed-off-by: Bo-Cun Chen {}, --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -262,6 +262,13 @@ +@@ -264,6 +264,13 @@ #define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4) #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0) @@ -187,7 +187,7 @@ Signed-off-by: Bo-Cun Chen /* QDMA TX Scheduler Rate Control Register */ #define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15) -@@ -536,9 +543,23 @@ +@@ -539,9 +546,23 @@ #define XMAC_MCR_FORCE_RX_FC BIT(4) /* XFI Mac logic reset registers */ @@ -212,7 +212,7 @@ Signed-off-by: Bo-Cun Chen /* XFI Mac count global control */ #define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100) #define XMAC_GLB_CNTCLR BIT(0) -@@ -834,6 +855,17 @@ enum mtk_clks_map { +@@ -842,6 +863,17 @@ enum mtk_clks_map { BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) @@ -230,7 +230,7 @@ Signed-off-by: Bo-Cun Chen #define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ -@@ -990,12 +1022,14 @@ enum mkt_eth_capabilities { +@@ -998,12 +1030,14 @@ enum mkt_eth_capabilities { MTK_RSTCTRL_PPE2_BIT, MTK_U3_COPHY_V2_BIT, MTK_SRAM_BIT, @@ -246,7 +246,7 @@ Signed-off-by: Bo-Cun Chen MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT, MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, -@@ -1037,14 +1071,16 @@ enum mkt_eth_capabilities { +@@ -1045,14 +1079,16 @@ enum mkt_eth_capabilities { #define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT) #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) #define MTK_SRAM BIT_ULL(MTK_SRAM_BIT) @@ -265,7 +265,7 @@ Signed-off-by: Bo-Cun Chen #define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \ BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT) #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ -@@ -1076,12 +1112,13 @@ enum mkt_eth_capabilities { +@@ -1084,12 +1120,13 @@ enum mkt_eth_capabilities { #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) @@ -283,7 +283,7 @@ Signed-off-by: Bo-Cun Chen /* MUXes present on SoCs */ /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ -@@ -1091,9 +1128,9 @@ enum mkt_eth_capabilities { +@@ -1099,9 +1136,9 @@ enum mkt_eth_capabilities { #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) @@ -296,7 +296,7 @@ Signed-off-by: Bo-Cun Chen /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ -@@ -1133,18 +1170,24 @@ enum mkt_eth_capabilities { +@@ -1141,18 +1178,24 @@ enum mkt_eth_capabilities { #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ diff --git a/target/linux/mediatek/patches-6.18/751-net-ethernet-mtk_eth_soc-revise-hardware-configuration-for-mt7987.patch b/target/linux/mediatek/patches-6.18/751-net-ethernet-mtk_eth_soc-revise-hardware-configuration-for-mt7987.patch index cef30ef64e..c9f638f5e6 100644 --- a/target/linux/mediatek/patches-6.18/751-net-ethernet-mtk_eth_soc-revise-hardware-configuration-for-mt7987.patch +++ b/target/linux/mediatek/patches-6.18/751-net-ethernet-mtk_eth_soc-revise-hardware-configuration-for-mt7987.patch @@ -15,7 +15,7 @@ Signed-off-by: Bo-Cun Chen --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -4461,27 +4461,40 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -4570,27 +4570,40 @@ static int mtk_hw_init(struct mtk_eth *e mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) | PSE_DUMMY_WORK_GDM(2) | PSE_DUMMY_WORK_GDM(3) | DUMMY_PAGE_THR, PSE_DUMY_REQ); diff --git a/target/linux/mediatek/patches-6.18/752-net-phy-mediatek-i2p5g-add-support-for-mt7987.patch b/target/linux/mediatek/patches-6.18/752-net-phy-mtk-2p5ge-add-support-for-mt7987.patch similarity index 71% rename from target/linux/mediatek/patches-6.18/752-net-phy-mediatek-i2p5g-add-support-for-mt7987.patch rename to target/linux/mediatek/patches-6.18/752-net-phy-mtk-2p5ge-add-support-for-mt7987.patch index 54a5ae3d86..549243289c 100644 --- a/target/linux/mediatek/patches-6.18/752-net-phy-mediatek-i2p5g-add-support-for-mt7987.patch +++ b/target/linux/mediatek/patches-6.18/752-net-phy-mtk-2p5ge-add-support-for-mt7987.patch @@ -12,86 +12,85 @@ Signed-off-by: Daniel Golle --- --- a/drivers/net/phy/mediatek/mtk-2p5ge.c +++ b/drivers/net/phy/mediatek/mtk-2p5ge.c -@@ -12,13 +12,77 @@ +@@ -9,17 +9,76 @@ #include "mtk.h" -+#define MTK_2P5GPHY_ID_MT7987 (0x00339c91) - #define MTK_2P5GPHY_ID_MT7988 (0x00339c11) ++#define MTK_2P5GPHY_ID_MT7987 0x00339c91 + #define MTK_2P5GPHY_ID_MT7988 0x00339c11 +#define MT7987_2P5GE_PMB_FW "mediatek/mt7987/i2p5ge-phy-pmb.bin" -+#define MT7987_2P5GE_PMB_FW_SIZE (0x18000) -+#define MT7987_2P5GE_DSPBITTB \ -+ "mediatek/mt7987/i2p5ge-phy-DSPBitTb.bin" -+#define MT7987_2P5GE_DSPBITTB_SIZE (0x7000) ++#define MT7987_2P5GE_PMB_FW_SIZE 0x18000 ++#define MT7987_2P5GE_DSPBITTB "mediatek/mt7987/i2p5ge-phy-DSPBitTb.bin" ++#define MT7987_2P5GE_DSPBITTB_SIZE 0x7000 + #define MT7988_2P5GE_PMB_FW "mediatek/mt7988/i2p5ge-phy-pmb.bin" - #define MT7988_2P5GE_PMB_FW_SIZE (0x20000) + #define MT7988_2P5GE_PMB_FW_SIZE 0x20000 + #define MT7988_2P5GE_PMB_FW_BASE 0x0f100000 + #define MT7988_2P5GE_PMB_FW_LEN 0x20000 + -+#define MTK_2P5GPHY_PMD_REG_BASE (0x0f010000) -+#define MTK_2P5GPHY_PMD_REG_LEN (0x210) -+#define DO_NOT_RESET (0x28) -+#define DO_NOT_RESET_XBZ BIT(0) -+#define DO_NOT_RESET_PMA BIT(3) -+#define DO_NOT_RESET_RX BIT(5) -+#define FNPLL_PWR_CTRL1 (0x208) -+#define RG_SPEED_MASK GENMASK(3, 0) -+#define RG_SPEED_2500 BIT(3) -+#define RG_SPEED_100 BIT(0) -+#define FNPLL_PWR_CTRL_STATUS (0x20c) -+#define RG_STABLE_MASK GENMASK(3, 0) -+#define RG_SPEED_2500_STABLE BIT(3) -+#define RG_SPEED_100_STABLE BIT(0) ++#define MTK_2P5GPHY_PMD_REG_BASE 0x0f010000 ++#define MTK_2P5GPHY_PMD_REG_LEN 0x210 ++#define DO_NOT_RESET 0x28 ++#define DO_NOT_RESET_XBZ BIT(0) ++#define DO_NOT_RESET_PMA BIT(3) ++#define DO_NOT_RESET_RX BIT(5) ++#define FNPLL_PWR_CTRL1 0x208 ++#define RG_SPEED_MASK GENMASK(3, 0) ++#define RG_SPEED_2500 BIT(3) ++#define RG_SPEED_100 BIT(0) ++#define FNPLL_PWR_CTRL_STATUS 0x20c ++#define RG_STABLE_MASK GENMASK(3, 0) ++#define RG_SPEED_2500_STABLE BIT(3) ++#define RG_SPEED_100_STABLE BIT(0) + -+#define MTK_2P5GPHY_XBZ_PCS_REG_BASE (0x0f030000) -+#define MTK_2P5GPHY_XBZ_PCS_REG_LEN (0x844) -+#define PHY_CTRL_CONFIG (0x200) -+#define PMU_WP (0x800) -+#define WRITE_PROTECT_KEY (0xCAFEF00D) -+#define PMU_PMA_AUTO_CFG (0x820) -+#define POWER_ON_AUTO_MODE BIT(16) -+#define PMU_AUTO_MODE_EN BIT(0) -+#define PMU_PMA_STATUS (0x840) -+#define CLK_IS_DISABLED BIT(3) ++#define MTK_2P5GPHY_XBZ_PCS_REG_BASE 0x0f030000 ++#define MTK_2P5GPHY_XBZ_PCS_REG_LEN 0x844 ++#define PHY_CTRL_CONFIG 0x200 ++#define PMU_WP 0x800 ++#define WRITE_PROTECT_KEY 0xCAFEF00D ++#define PMU_PMA_AUTO_CFG 0x820 ++#define POWER_ON_AUTO_MODE BIT(16) ++#define PMU_AUTO_MODE_EN BIT(0) ++#define PMU_PMA_STATUS 0x840 ++#define CLK_IS_DISABLED BIT(3) + -+#define MTK_2P5GPHY_XBZ_PMA_RX_BASE (0x0f080000) -+#define MTK_2P5GPHY_XBZ_PMA_RX_LEN (0x5228) -+#define SMEM_WDAT0 (0x5000) -+#define SMEM_WDAT1 (0x5004) -+#define SMEM_WDAT2 (0x5008) -+#define SMEM_WDAT3 (0x500c) -+#define SMEM_CTRL (0x5024) -+#define SMEM_HW_RDATA_ZERO BIT(24) -+#define SMEM_ADDR_REF_ADDR (0x502c) -+#define CM_CTRL_P01 (0x5100) -+#define CM_CTRL_P23 (0x5124) -+#define DM_CTRL_P01 (0x5200) -+#define DM_CTRL_P23 (0x5224) ++#define MTK_2P5GPHY_XBZ_PMA_RX_BASE 0x0f080000 ++#define MTK_2P5GPHY_XBZ_PMA_RX_LEN 0x5228 ++#define SMEM_WDAT0 0x5000 ++#define SMEM_WDAT1 0x5004 ++#define SMEM_WDAT2 0x5008 ++#define SMEM_WDAT3 0x500c ++#define SMEM_CTRL 0x5024 ++#define SMEM_HW_RDATA_ZERO BIT(24) ++#define SMEM_ADDR_REF_ADDR 0x502c ++#define CM_CTRL_P01 0x5100 ++#define CM_CTRL_P23 0x5124 ++#define DM_CTRL_P01 0x5200 ++#define DM_CTRL_P23 0x5224 + -+#define MTK_2P5GPHY_CHIP_SCU_BASE (0x0f0cf800) -+#define MTK_2P5GPHY_CHIP_SCU_LEN (0x12c) -+#define SYS_SW_RESET (0x128) -+#define RESET_RST_CNT BIT(0) ++#define MTK_2P5GPHY_CHIP_SCU_BASE 0x0f0cf800 ++#define MTK_2P5GPHY_CHIP_SCU_LEN 0x12c ++#define SYS_SW_RESET 0x128 ++#define RESET_RST_CNT BIT(0) + -+#define MTK_2P5GPHY_MCU_CSR_BASE (0x0f0f0000) -+#define MTK_2P5GPHY_MCU_CSR_LEN (0x20) - #define MD32_EN_CFG (0x18) + #define MTK_2P5GPHY_MCU_CSR_BASE 0x0f0f0000 + #define MTK_2P5GPHY_MCU_CSR_LEN 0x20 + #define MD32_EN_CFG 0x18 #define MD32_EN BIT(0) -+#define MTK_2P5GPHY_PMB_FW_BASE (0x0f100000) -+//#define MTK_2P5GPHY_PMB_FW_LEN MT7988_2P5GE_PMB_FW_SIZE ++#define MTK_2P5GPHY_PMB_FW_BASE 0x0f100000 + -+#define MTK_2P5GPHY_APB_BASE (0x11c30000) -+#define MTK_2P5GPHY_APB_LEN (0x9c) -+#define SW_RESET (0x94) -+#define MD32_RESTART_EN_CLEAR BIT(9) ++#define MTK_2P5GPHY_APB_BASE 0x11c30000 ++#define MTK_2P5GPHY_APB_LEN 0x9c ++#define SW_RESET 0x94 ++#define MD32_RESTART_EN_CLEAR BIT(9) + -+ - #define BASE100T_STATUS_EXTEND (0x10) - #define BASE1000T_STATUS_EXTEND (0x11) - #define EXTEND_CTRL_AND_STATUS (0x16) -@@ -31,6 +95,14 @@ - #define MTK_PHY_LPI_PCS_DSP_CTRL (0x121) + #define BASE100T_STATUS_EXTEND 0x10 + #define BASE1000T_STATUS_EXTEND 0x11 + #define EXTEND_CTRL_AND_STATUS 0x16 +@@ -32,6 +91,14 @@ + #define MTK_PHY_LPI_PCS_DSP_CTRL 0x121 #define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8) +#define MTK_PHY_LINK_STATUS_RELATED (0x147) @@ -105,14 +104,13 @@ Signed-off-by: Daniel Golle #define MTK_PHY_HOST_CMD1 0x800e #define MTK_PHY_HOST_CMD2 0x800f /* Registers on Token Ring debug nodes */ -@@ -48,7 +120,249 @@ enum { +@@ -45,7 +112,243 @@ enum { PHY_AUX_SPD_2500, }; -static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev) +static int mt7987_2p5ge_phy_load_fw(struct phy_device *phydev) +{ -+ struct mtk_i2p5ge_phy_priv *priv = phydev->priv; + struct device *dev = &phydev->mdio.dev; + void __iomem *xbz_pcs_reg_base; + void __iomem *xbz_pma_rx_base; @@ -125,9 +123,6 @@ Signed-off-by: Daniel Golle + int ret, i; + u32 reg; + -+ if (priv->fw_loaded) -+ return 0; -+ + apb_base = ioremap(MTK_2P5GPHY_APB_BASE, + MTK_2P5GPHY_APB_LEN); + if (!apb_base) @@ -330,8 +325,6 @@ Signed-off-by: Daniel Golle + usleep_range(7000, 8000); + dev_info(dev, "Firmware loading/trigger ok.\n"); + -+ priv->fw_loaded = true; -+ +release_fw: + release_firmware(fw); +free_pmb_addr: @@ -354,49 +347,78 @@ Signed-off-by: Daniel Golle + +static int mt7988_2p5ge_phy_load_fw(struct phy_device *phydev) { - struct mtk_i2p5ge_phy_priv *priv = phydev->priv; + struct device *dev = &phydev->mdio.dev; void __iomem *mcu_csr_base, *pmb_addr; -@@ -135,15 +449,27 @@ static int mt798x_2p5ge_phy_config_init( - if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL) - return -ENODEV; +@@ -326,7 +629,15 @@ static int mt798x_2p5ge_phy_probe(struct + struct pinctrl *pinctrl; + int ret; + ++ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ phydev->priv = priv; ++ + switch (phydev->drv->phy_id) { ++ case MTK_2P5GPHY_ID_MT7987: + case MTK_2P5GPHY_ID_MT7988: + /* This built-in 2.5GbE hardware only sets MDIO_DEVS_PMAPMD. + * Set the rest by this driver since PCS/AN/VEND1/VEND2 MDIO +@@ -341,15 +652,36 @@ static int mt798x_2p5ge_phy_probe(struct + return -EINVAL; + } - ret = mt798x_2p5ge_phy_load_fw(phydev); + switch (phydev->drv->phy_id) { + case MTK_2P5GPHY_ID_MT7987: + ret = mt7987_2p5ge_phy_load_fw(phydev); ++ break; ++ case MTK_2P5GPHY_ID_MT7988: ++ ret = mt7988_2p5ge_phy_load_fw(phydev); ++ break; ++ default: ++ return -EINVAL; ++ } ++ + if (ret < 0) + return ret; + ++ switch (phydev->drv->phy_id) { ++ case MTK_2P5GPHY_ID_MT7987: + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, + MTK_PHY_LED_ON_POLARITY); + break; + case MTK_2P5GPHY_ID_MT7988: -+ ret = mt7988_2p5ge_phy_load_fw(phydev); + phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, + MTK_PHY_LED_ON_POLARITY); + break; + default: + return -EINVAL; + } - if (ret < 0) - return ret; ++ + /* Setup LED. On default, LED0 is on/off when link is up/down. As for + * LED1, it blinks as tx/rx transmission takes place. + */ +- phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, +- MTK_PHY_LED_ON_POLARITY | MTK_2P5GPHY_LED_ON_SET); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, + MTK_2P5GPHY_LED_TX_BLINK_SET | + MTK_2P5GPHY_LED_RX_BLINK_SET); +@@ -365,12 +697,6 @@ static int mt798x_2p5ge_phy_probe(struct + if (IS_ERR(pinctrl)) + dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n"); - /* Setup LED */ - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, -- MTK_PHY_LED_ON_POLARITY | MTK_PHY_LED_ON_LINK10 | -- MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK1000 | -- MTK_PHY_LED_ON_LINK2500); -+ MTK_PHY_LED_ON_LINK10 | MTK_PHY_LED_ON_LINK100 | -+ MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK2500); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, - MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX); +- priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), +- GFP_KERNEL); +- if (!priv) +- return -ENOMEM; +- phydev->priv = priv; +- + mtk_phy_leds_state_init(phydev); -@@ -293,6 +619,7 @@ static int mt798x_2p5ge_phy_probe(struct - return -ENOMEM; - - switch (phydev->drv->phy_id) { -+ case MTK_2P5GPHY_ID_MT7987: - case MTK_2P5GPHY_ID_MT7988: - /* The original hardware only sets MDIO_DEVS_PMAPMD */ - phydev->c45_ids.mmds_present |= MDIO_DEVS_PCS | -@@ -312,6 +639,20 @@ static int mt798x_2p5ge_phy_probe(struct + return 0; +@@ -378,6 +704,25 @@ static int mt798x_2p5ge_phy_probe(struct static struct phy_driver mtk_2p5gephy_driver[] = { { @@ -412,6 +434,11 @@ Signed-off-by: Daniel Golle + .resume = genphy_resume, + .read_page = mtk_phy_read_page, + .write_page = mtk_phy_write_page, ++ .led_blink_set = mt798x_2p5ge_phy_led_blink_set, ++ .led_brightness_set = mt798x_2p5ge_phy_led_brightness_set, ++ .led_hw_is_supported = mt798x_2p5ge_phy_led_hw_is_supported, ++ .led_hw_control_get = mt798x_2p5ge_phy_led_hw_control_get, ++ .led_hw_control_set = mt798x_2p5ge_phy_led_hw_control_set, + }, + { PHY_ID_MATCH_MODEL(MTK_2P5GPHY_ID_MT7988), diff --git a/target/linux/mediatek/patches-6.18/821-add-pwm-feature-for-mt7987.patch b/target/linux/mediatek/patches-6.18/821-add-pwm-feature-for-mt7987.patch index 5b8fe7efcf..834a01559d 100644 --- a/target/linux/mediatek/patches-6.18/821-add-pwm-feature-for-mt7987.patch +++ b/target/linux/mediatek/patches-6.18/821-add-pwm-feature-for-mt7987.patch @@ -9,32 +9,21 @@ Subject: [PATCH] add pwm reg-v3 support for mt7987 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c -@@ -64,6 +64,10 @@ static const unsigned int mtk_pwm_reg_of - 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 - }; - -+static const unsigned int mtk_pwm_reg_offset_v3[] = { -+ 0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x600, 0x700, 0x0800 -+}; -+ - static inline struct pwm_mediatek_chip * - to_pwm_mediatek_chip(struct pwm_chip *chip) - { -@@ -350,6 +354,13 @@ static const struct pwm_mediatek_of_data - .reg_offset = mtk_pwm_reg_offset_v1, +@@ -486,6 +486,13 @@ static const struct pwm_mediatek_of_data + .chanreg_width = 0x40, }; +static const struct pwm_mediatek_of_data mt7987_pwm_data = { + .num_pwms = 3, + .pwm45_fixup = false, -+ .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v3, ++ .chanreg_base = 0x100, ++ .chanreg_width = 0x100, +}; + static const struct pwm_mediatek_of_data mt7988_pwm_data = { .num_pwms = 8, .pwm45_fixup = false, -@@ -387,6 +398,7 @@ static const struct of_device_id pwm_med +@@ -535,6 +542,7 @@ static const struct of_device_id pwm_med { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, diff --git a/target/linux/mediatek/patches-6.18/840-cpufreq-add-support-to-adjust-cpu-volt-by-efuse-cali.patch b/target/linux/mediatek/patches-6.18/840-cpufreq-add-support-to-adjust-cpu-volt-by-efuse-cali.patch index 9aebab6689..5109c8a715 100644 --- a/target/linux/mediatek/patches-6.18/840-cpufreq-add-support-to-adjust-cpu-volt-by-efuse-cali.patch +++ b/target/linux/mediatek/patches-6.18/840-cpufreq-add-support-to-adjust-cpu-volt-by-efuse-cali.patch @@ -88,7 +88,7 @@ Subject: [PATCH 1/2] cpufreq: add support to adjust cpu volt by efuse static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, unsigned int index) { -@@ -584,6 +640,15 @@ static int mtk_cpufreq_init(struct cpufr +@@ -591,6 +647,15 @@ static int mtk_cpufreq_init(struct cpufr return -EINVAL; } diff --git a/target/linux/mediatek/patches-6.18/841-cpufreq-add-cpu-volt-correction-support-for-mt7988.patch b/target/linux/mediatek/patches-6.18/841-cpufreq-add-cpu-volt-correction-support-for-mt7988.patch index a6422b6402..1dc4ab62e4 100644 --- a/target/linux/mediatek/patches-6.18/841-cpufreq-add-cpu-volt-correction-support-for-mt7988.patch +++ b/target/linux/mediatek/patches-6.18/841-cpufreq-add-cpu-volt-correction-support-for-mt7988.patch @@ -12,7 +12,7 @@ Signed-off-by: Daniel Golle --- --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -741,6 +741,16 @@ static struct platform_driver mtk_cpufre +@@ -747,6 +747,16 @@ static struct platform_driver mtk_cpufre .probe = mtk_cpufreq_probe, }; @@ -29,7 +29,7 @@ Signed-off-by: Daniel Golle static const struct mtk_cpufreq_platform_data mt2701_platform_data = { .min_volt_shift = 100000, .max_volt_shift = 200000, -@@ -769,10 +779,12 @@ static const struct mtk_cpufreq_platform +@@ -775,10 +785,12 @@ static const struct mtk_cpufreq_platform static const struct mtk_cpufreq_platform_data mt7988_platform_data = { .min_volt_shift = 100000, .max_volt_shift = 200000, diff --git a/target/linux/mediatek/patches-6.18/842-mediatek-enable-using-efuse-cali-data-for-mt7988-cpu-volt.patch b/target/linux/mediatek/patches-6.18/842-mediatek-enable-using-efuse-cali-data-for-mt7988-cpu-volt.patch index 30115a2358..5656a752c8 100644 --- a/target/linux/mediatek/patches-6.18/842-mediatek-enable-using-efuse-cali-data-for-mt7988-cpu-volt.patch +++ b/target/linux/mediatek/patches-6.18/842-mediatek-enable-using-efuse-cali-data-for-mt7988-cpu-volt.patch @@ -10,7 +10,7 @@ Subject: [PATCH 2/2] cpufreq: mt7988: enable using efuse calibration data for --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -55,6 +55,8 @@ +@@ -54,6 +54,8 @@ <&topckgen CLK_TOP_XTAL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; @@ -19,7 +19,7 @@ Subject: [PATCH 2/2] cpufreq: mt7988: enable using efuse calibration data for mediatek,cci = <&cci>; }; -@@ -67,6 +69,8 @@ +@@ -66,6 +68,8 @@ <&topckgen CLK_TOP_XTAL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; @@ -28,7 +28,7 @@ Subject: [PATCH 2/2] cpufreq: mt7988: enable using efuse calibration data for mediatek,cci = <&cci>; }; -@@ -79,6 +83,8 @@ +@@ -78,6 +82,8 @@ <&topckgen CLK_TOP_XTAL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; @@ -37,7 +37,7 @@ Subject: [PATCH 2/2] cpufreq: mt7988: enable using efuse calibration data for mediatek,cci = <&cci>; }; -@@ -91,6 +97,8 @@ +@@ -90,6 +96,8 @@ <&topckgen CLK_TOP_XTAL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; diff --git a/target/linux/mediatek/patches-6.18/844-cpufreq-mediatek-Add-support-for-MT7987.patch b/target/linux/mediatek/patches-6.18/844-cpufreq-mediatek-Add-support-for-MT7987.patch index 5901b45b9b..3bfb57748b 100644 --- a/target/linux/mediatek/patches-6.18/844-cpufreq-mediatek-Add-support-for-MT7987.patch +++ b/target/linux/mediatek/patches-6.18/844-cpufreq-mediatek-Add-support-for-MT7987.patch @@ -11,7 +11,7 @@ Signed-off-by: Daniel Golle --- --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -781,6 +781,12 @@ static const struct mtk_cpufreq_platform +@@ -787,6 +787,12 @@ static const struct mtk_cpufreq_platform .ccifreq_supported = false, }; @@ -24,7 +24,7 @@ Signed-off-by: Daniel Golle static const struct mtk_cpufreq_platform_data mt7988_platform_data = { .min_volt_shift = 100000, .max_volt_shift = 200000, -@@ -825,6 +831,7 @@ static const struct of_device_id mtk_cpu +@@ -831,6 +837,7 @@ static const struct of_device_id mtk_cpu { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, diff --git a/target/linux/mediatek/patches-6.18/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch b/target/linux/mediatek/patches-6.18/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch index dd21397db2..ccf5742c0b 100644 --- a/target/linux/mediatek/patches-6.18/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch +++ b/target/linux/mediatek/patches-6.18/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch @@ -113,9 +113,9 @@ Signed-off-by: Daniel Golle +}; --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile -@@ -18,6 +18,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-b - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo +@@ -19,6 +19,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-b dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sata.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-respeaker-2mics.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb diff --git a/target/linux/mediatek/patches-6.18/870-iommu-mediatek-v1-add-.of_xlate-and-defer-arm_iommu_.patch b/target/linux/mediatek/patches-6.18/870-iommu-mediatek-v1-add-.of_xlate-and-defer-arm_iommu_.patch new file mode 100644 index 0000000000..a8d34d05c4 --- /dev/null +++ b/target/linux/mediatek/patches-6.18/870-iommu-mediatek-v1-add-.of_xlate-and-defer-arm_iommu_.patch @@ -0,0 +1,148 @@ +From e258b2fa7990bc8dac6f9dcbd5848ccf9dc9de1a Mon Sep 17 00:00:00 2001 +Message-ID: +From: Daniel Golle +Date: Tue, 14 Apr 2026 00:16:43 +0100 +Subject: [PATCH] iommu/mediatek-v1: add .of_xlate and defer + arm_iommu_create_mapping() +To: Yong Wu , + Joerg Roedel , + Will Deacon , + Robin Murphy , + Matthias Brugger , + AngeloGioacchino Del Regno , + Jason Gunthorpe , + Lorenzo Pieralisi , + Bjorn Helgaas , + iommu@lists.linux.dev, + linux-mediatek@lists.infradead.org, + linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org + +Since commit bcb81ac6ae3c ("iommu: Get DT/ACPI parsing into the proper +probe path") the iommu core populates the device's iommu_fwspec via +of_iommu_xlate() -> ops->of_xlate() before calling ops->probe_device(). +mtk_iommu_v1 did not provide .of_xlate and instead parsed the "iommus" +property itself from probe_device(); with the new flow of_iommu_xlate() +returns -ENODEV, the fwspec is never populated, probe_device() is never +called, and the device_link from consumers (disp-ovl, disp-rdma, ...) +to their smi-larb supplier is never created. As a result the larb is +never runtime-resumed, its SMI clocks are gated by clk_disable_unused(), +and display and GPU DMA through the SMI bus fabric hang as soon as +unused clocks are disabled at late_initcall_sync. + +Register mtk_iommu_v1_of_xlate() as .of_xlate and simplify +mtk_iommu_v1_probe_device() to just consume the already-populated +fwspec. arm_iommu_create_mapping() cannot run from the of_xlate path +because it eventually calls iommu_paging_domain_alloc() -> +dev_has_iommu(), which returns -ENODEV while the device is still in +the middle of its iommu setup and not yet attached to an iommu_group. +Move the mapping creation to probe_finalize(), which runs once the +iommu group has been set up for the device. + +Fixes: bcb81ac6ae3c ("iommu: Get DT/ACPI parsing into the proper probe path") +Cc: stable@vger.kernel.org +Signed-off-by: Daniel Golle +--- + drivers/iommu/mtk_iommu_v1.c | 58 +++++++++++++----------------------- + 1 file changed, 20 insertions(+), 38 deletions(-) + +--- a/drivers/iommu/mtk_iommu_v1.c ++++ b/drivers/iommu/mtk_iommu_v1.c +@@ -410,12 +410,10 @@ static const struct iommu_ops mtk_iommu_ + * MTK generation one iommu HW only support one iommu domain, and all the client + * sharing the same iova address space. + */ +-static int mtk_iommu_v1_create_mapping(struct device *dev, +- const struct of_phandle_args *args) ++static int mtk_iommu_v1_of_xlate(struct device *dev, ++ const struct of_phandle_args *args) + { +- struct mtk_iommu_v1_data *data; + struct platform_device *m4updev; +- struct dma_iommu_mapping *mtk_mapping; + int ret; + + if (args->args_count != 1) { +@@ -439,47 +437,17 @@ static int mtk_iommu_v1_create_mapping(s + put_device(&m4updev->dev); + } + +- ret = iommu_fwspec_add_ids(dev, args->args, 1); +- if (ret) +- return ret; +- +- data = dev_iommu_priv_get(dev); +- mtk_mapping = data->mapping; +- if (!mtk_mapping) { +- /* MTK iommu support 4GB iova address space. */ +- mtk_mapping = arm_iommu_create_mapping(dev, 0, 1ULL << 32); +- if (IS_ERR(mtk_mapping)) +- return PTR_ERR(mtk_mapping); +- +- data->mapping = mtk_mapping; +- } +- +- return 0; ++ return iommu_fwspec_add_ids(dev, args->args, 1); + } + + static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev) + { +- struct iommu_fwspec *fwspec = NULL; +- struct of_phandle_args iommu_spec; ++ struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct mtk_iommu_v1_data *data; +- int err, idx = 0, larbid, larbidx; ++ int idx, larbid, larbidx; + struct device_link *link; + struct device *larbdev; + +- while (!of_parse_phandle_with_args(dev->of_node, "iommus", +- "#iommu-cells", +- idx, &iommu_spec)) { +- +- err = mtk_iommu_v1_create_mapping(dev, &iommu_spec); +- of_node_put(iommu_spec.np); +- if (err) +- return ERR_PTR(err); +- +- /* dev->iommu_fwspec might have changed */ +- fwspec = dev_iommu_fwspec_get(dev); +- idx++; +- } +- + if (!fwspec) + return ERR_PTR(-ENODEV); + +@@ -513,9 +481,22 @@ static struct iommu_device *mtk_iommu_v1 + + static void mtk_iommu_v1_probe_finalize(struct device *dev) + { +- __maybe_unused struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); ++ struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); ++ struct dma_iommu_mapping *mtk_mapping; + int err; + ++ mtk_mapping = data->mapping; ++ if (!mtk_mapping) { ++ /* MTK iommu supports 4GB iova address space. */ ++ mtk_mapping = arm_iommu_create_mapping(dev, 0, 1ULL << 32); ++ if (IS_ERR(mtk_mapping)) { ++ dev_err(dev, "Failed to create IOMMU mapping: %ld\n", ++ PTR_ERR(mtk_mapping)); ++ return; ++ } ++ data->mapping = mtk_mapping; ++ } ++ + err = arm_iommu_attach_device(dev, data->mapping); + if (err) + dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); +@@ -582,6 +563,7 @@ static const struct iommu_ops mtk_iommu_ + .probe_finalize = mtk_iommu_v1_probe_finalize, + .release_device = mtk_iommu_v1_release_device, + .device_group = generic_device_group, ++ .of_xlate = mtk_iommu_v1_of_xlate, + .owner = THIS_MODULE, + .default_domain_ops = &(const struct iommu_domain_ops) { + .attach_dev = mtk_iommu_v1_attach_device, diff --git a/target/linux/mediatek/patches-6.18/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-6.18/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch index 03038d35d4..5a483b7862 100644 --- a/target/linux/mediatek/patches-6.18/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch +++ b/target/linux/mediatek/patches-6.18/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch @@ -17,8 +17,8 @@ Signed-off-by: Daniel Golle /* Attention: GPIO 90 is used to switch between PCIe@1,0 and * SATA functions. i.e. output-high: PCIe, output-low: SATA */ -- asm_sel { -+ asmsel: asm_sel { +- asm-sel-hog { ++ asmsel: asm-sel-hog { gpio-hog; gpios = <90 GPIO_ACTIVE_HIGH>; output-high; diff --git a/target/linux/mediatek/patches-6.18/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-6.18/901-arm-add-cmdline-override.patch index b127b0e348..302791113e 100644 --- a/target/linux/mediatek/patches-6.18/901-arm-add-cmdline-override.patch +++ b/target/linux/mediatek/patches-6.18/901-arm-add-cmdline-override.patch @@ -14,7 +14,7 @@ Signed-off-by: Yoonji Park --- --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -1505,6 +1505,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN +@@ -1490,6 +1490,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN endchoice @@ -23,7 +23,7 @@ Signed-off-by: Yoonji Park + help + Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can + be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the ++ devices. This setting enables using "chosen/bootargs-override" as the + cmdline if it exists in the device tree. + config CMDLINE @@ -31,7 +31,7 @@ Signed-off-by: Yoonji Park default "" --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c -@@ -1053,6 +1053,17 @@ int __init early_init_dt_scan_chosen(cha +@@ -1120,6 +1120,17 @@ int __init early_init_dt_scan_chosen(cha if (p != NULL && l > 0) strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE)); @@ -51,7 +51,7 @@ Signed-off-by: Yoonji Park * CONFIG_CMDLINE is meant to be a default in case nothing else --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig -@@ -2383,6 +2383,14 @@ config CMDLINE_FORCE +@@ -2386,6 +2386,14 @@ config CMDLINE_FORCE endchoice @@ -60,7 +60,7 @@ Signed-off-by: Yoonji Park + help + Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can + be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the ++ devices. This setting enables using "chosen/bootargs-override" as the + cmdline if it exists in the device tree. + config EFI_STUB diff --git a/target/linux/mediatek/patches-6.18/911-dts-mt7988a-bpi-r4-be14-wifi-eeprom.patch b/target/linux/mediatek/patches-6.18/912-dts-mt7988a-bpi-r4-be14-wifi-eeprom.patch similarity index 100% rename from target/linux/mediatek/patches-6.18/911-dts-mt7988a-bpi-r4-be14-wifi-eeprom.patch rename to target/linux/mediatek/patches-6.18/912-dts-mt7988a-bpi-r4-be14-wifi-eeprom.patch diff --git a/target/linux/mediatek/patches-6.18/930-spi-mt65xx-enable-sel-clk.patch b/target/linux/mediatek/patches-6.18/930-spi-mt65xx-enable-sel-clk.patch index b15dde1c3b..c809f87ebd 100644 --- a/target/linux/mediatek/patches-6.18/930-spi-mt65xx-enable-sel-clk.patch +++ b/target/linux/mediatek/patches-6.18/930-spi-mt65xx-enable-sel-clk.patch @@ -12,7 +12,7 @@ Signed-off-by: Chuanhong Guo --- --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c -@@ -1237,8 +1237,15 @@ static int mtk_spi_probe(struct platform +@@ -1289,8 +1289,15 @@ static int mtk_spi_probe(struct platform if (ret < 0) return dev_err_probe(dev, ret, "failed to enable hclk\n"); diff --git a/target/linux/mediatek/patches-6.18/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch b/target/linux/mediatek/patches-6.18/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch index 465f0eaf27..67eb486e27 100644 --- a/target/linux/mediatek/patches-6.18/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch +++ b/target/linux/mediatek/patches-6.18/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch @@ -19,19 +19,20 @@ Signed-off-by: Lorenzo Bianconi } static int --mtk_wed_get_memory_region(struct mtk_wed_hw *hw, int index, +-mtk_wed_get_memory_region(struct mtk_wed_hw *hw, const char *name, - struct mtk_wed_wo_memory_region *region) -+mtk_wed_get_reserved_memory_region(struct mtk_wed_hw *hw, int index, ++mtk_wed_get_reserved_memory_region(struct mtk_wed_hw *hw, const char *name, + struct mtk_wed_wo_memory_region *region) { - struct reserved_mem *rmem; - struct device_node *np; -@@ -325,7 +325,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - if (index < 0) - continue; + struct resource res; + int ret; +@@ -315,7 +315,8 @@ mtk_wed_mcu_load_firmware(struct mtk_wed -- ret = mtk_wed_get_memory_region(wo->hw, index, &mem_region[i]); -+ ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]); + /* load firmware region metadata */ + for (i = 0; i < ARRAY_SIZE(mem_region); i++) { +- ret = mtk_wed_get_memory_region(wo->hw, mem_region[i].name, &mem_region[i]); ++ ret = mtk_wed_get_reserved_memory_region(wo->hw, mem_region[i].name, ++ &mem_region[i]); if (ret) return ret; } diff --git a/target/linux/mediatek/patches-6.18/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.18/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch index a75a297e04..fa768d031d 100644 --- a/target/linux/mediatek/patches-6.18/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch +++ b/target/linux/mediatek/patches-6.18/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch @@ -52,7 +52,7 @@ Signed-off-by: Lorenzo Bianconi }; eth: ethernet@15100000 { -@@ -607,6 +603,11 @@ +@@ -623,6 +619,11 @@ interrupts = ; }; diff --git a/target/linux/mediatek/patches-6.18/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch b/target/linux/mediatek/patches-6.18/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch index 43014c5d12..3ef5c0ea73 100644 --- a/target/linux/mediatek/patches-6.18/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch +++ b/target/linux/mediatek/patches-6.18/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch @@ -53,7 +53,7 @@ Signed-off-by: Lorenzo Bianconi } static struct sk_buff * -@@ -317,6 +328,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed +@@ -313,8 +324,14 @@ mtk_wed_mcu_load_firmware(struct mtk_wed u32 val, boot_cr; int ret, i; @@ -62,18 +62,13 @@ Signed-off-by: Lorenzo Bianconi + /* load firmware region metadata */ for (i = 0; i < ARRAY_SIZE(mem_region); i++) { - int index = of_property_match_string(wo->hw->node, -@@ -325,6 +339,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - if (index < 0) - continue; - -+ if (index == MTK_WED_WO_REGION_BOOT && !IS_ERR(wo->boot_regmap)) ++ if (i == MTK_WED_WO_REGION_BOOT && !IS_ERR(wo->boot_regmap)) + continue; + - ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]); + ret = mtk_wed_get_reserved_memory_region(wo->hw, mem_region[i].name, + &mem_region[i]); if (ret) - return ret; -@@ -373,13 +390,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed +@@ -364,13 +381,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed boot_cr = MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR; else boot_cr = MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR; diff --git a/target/linux/mediatek/patches-6.18/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.18/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch index 641c2597f7..1c616491bc 100644 --- a/target/linux/mediatek/patches-6.18/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch +++ b/target/linux/mediatek/patches-6.18/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch @@ -20,7 +20,7 @@ Signed-off-by: Lorenzo Bianconi --- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c +++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -320,6 +320,39 @@ next: +@@ -316,6 +316,39 @@ next: } static int @@ -60,7 +60,7 @@ Signed-off-by: Lorenzo Bianconi mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo) { const struct mtk_wed_fw_trailer *trailer; -@@ -328,14 +361,20 @@ mtk_wed_mcu_load_firmware(struct mtk_wed +@@ -324,6 +357,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed u32 val, boot_cr; int ret, i; @@ -68,19 +68,13 @@ Signed-off-by: Lorenzo Bianconi wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, "mediatek,wo-cpuboot"); - /* load firmware region metadata */ - for (i = 0; i < ARRAY_SIZE(mem_region); i++) { -- int index = of_property_match_string(wo->hw->node, -- "memory-region-names", -- mem_region[i].name); -+ int index; -+ +@@ -332,6 +366,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed + if (i == MTK_WED_WO_REGION_BOOT && !IS_ERR(wo->boot_regmap)) + continue; + + if (mem_region[i].addr) + continue; + -+ index = of_property_match_string(wo->hw->node, -+ "memory-region-names", -+ mem_region[i].name); - if (index < 0) - continue; - + ret = mtk_wed_get_reserved_memory_region(wo->hw, mem_region[i].name, + &mem_region[i]); + if (ret) diff --git a/target/linux/mediatek/patches-6.18/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.18/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch index a7a854dd6e..90dea9b434 100644 --- a/target/linux/mediatek/patches-6.18/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch +++ b/target/linux/mediatek/patches-6.18/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch @@ -22,15 +22,16 @@ Signed-off-by: Lorenzo Bianconi --- a/drivers/net/ethernet/mediatek/mtk_wed.c +++ b/drivers/net/ethernet/mediatek/mtk_wed.c -@@ -1333,6 +1333,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device - struct device_node *np; - int index; +@@ -1329,14 +1329,31 @@ mtk_wed_rro_ring_alloc(struct mtk_wed_de + static int + mtk_wed_rro_alloc(struct mtk_wed_device *dev) + { ++ struct device_node *np; + struct resource res; + int ret; + np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0); + if (np) { -+ struct resource res; -+ int ret; -+ + ret = of_address_to_resource(np, 0, &res); + of_node_put(np); + @@ -44,13 +45,11 @@ Signed-off-by: Lorenzo Bianconi + /* For backward compatibility, we need to check if DLM + * node is defined through reserved memory property. + */ - index = of_property_match_string(dev->hw->node, "memory-region-names", - "wo-dlm"); - if (index < 0) -@@ -1349,6 +1367,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device - return -ENODEV; + ret = of_reserved_mem_region_to_resource_byname(dev->hw->node, "wo-dlm", &res); + if (ret) + return ret; - dev->rro.miod_phys = rmem->base; + dev->rro.miod_phys = res.start; +out: dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys; diff --git a/target/linux/mediatek/patches-6.18/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.18/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch index c64b3b37c3..5a944af56d 100644 --- a/target/linux/mediatek/patches-6.18/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch +++ b/target/linux/mediatek/patches-6.18/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch @@ -64,7 +64,7 @@ Signed-off-by: Lorenzo Bianconi mediatek,wo-cpuboot = <&wo_cpuboot>; }; -@@ -603,6 +591,16 @@ +@@ -619,6 +607,16 @@ interrupts = ; }; diff --git a/target/linux/mediatek/patches-6.18/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.18/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch index 13fe1f792c..d52b059a3f 100644 --- a/target/linux/mediatek/patches-6.18/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch +++ b/target/linux/mediatek/patches-6.18/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch @@ -62,7 +62,7 @@ Signed-off-by: Lorenzo Bianconi mediatek,wo-cpuboot = <&wo_cpuboot>; }; -@@ -601,6 +593,16 @@ +@@ -617,6 +609,16 @@ reg = <0 0x151f0000 0 0x8000>; }; diff --git a/target/linux/mediatek/patches-6.18/950-smartrg-i2c-led-driver.patch b/target/linux/mediatek/patches-6.18/950-smartrg-i2c-led-driver.patch index 5bc3debc82..e7c8ee1747 100644 --- a/target/linux/mediatek/patches-6.18/950-smartrg-i2c-led-driver.patch +++ b/target/linux/mediatek/patches-6.18/950-smartrg-i2c-led-driver.patch @@ -15,7 +15,7 @@ Signed-off-by: Daniel Golle --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -977,6 +977,16 @@ source "drivers/leds/flash/Kconfig" +@@ -1028,6 +1028,16 @@ source "drivers/leds/flash/Kconfig" comment "RGB LED drivers" source "drivers/leds/rgb/Kconfig" @@ -34,8 +34,8 @@ Signed-off-by: Daniel Golle --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile -@@ -81,6 +81,7 @@ obj-$(CONFIG_LEDS_POWERNV) += leds-powe - obj-$(CONFIG_LEDS_PWM) += leds-pwm.o +@@ -85,6 +85,7 @@ obj-$(CONFIG_LEDS_PWM) += leds-pwm.o + obj-$(CONFIG_LEDS_QNAP_MCU) += leds-qnap-mcu.o obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o +obj-$(CONFIG_LEDS_SMARTRG_LED) += leds-smartrg-system.o diff --git a/target/linux/mediatek/patches-6.18/955-dts-mt7968a-bpi-r3-add-label-to-gmac-for-sfp1-port.patch b/target/linux/mediatek/patches-6.18/955-dts-mt7968a-bpi-r3-add-label-to-gmac-for-sfp1-port.patch index b0c3bc018a..6c6549f504 100644 --- a/target/linux/mediatek/patches-6.18/955-dts-mt7968a-bpi-r3-add-label-to-gmac-for-sfp1-port.patch +++ b/target/linux/mediatek/patches-6.18/955-dts-mt7968a-bpi-r3-add-label-to-gmac-for-sfp1-port.patch @@ -14,7 +14,7 @@ Signed-off-by: Jonas Jelonek --- --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -195,6 +195,7 @@ +@@ -191,6 +191,7 @@ phy-mode = "2500base-x"; sfp = <&sfp1>; managed = "in-band-status"; diff --git a/target/linux/mediatek/patches-6.18/960-asus-hack-u-boot-ignore-mtdparts.patch b/target/linux/mediatek/patches-6.18/960-asus-hack-u-boot-ignore-mtdparts.patch index da27916469..797adb9043 100644 --- a/target/linux/mediatek/patches-6.18/960-asus-hack-u-boot-ignore-mtdparts.patch +++ b/target/linux/mediatek/patches-6.18/960-asus-hack-u-boot-ignore-mtdparts.patch @@ -29,7 +29,7 @@ Signed-off-by: Daniel Golle --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -1698,6 +1698,7 @@ static int spinand_remove(struct spi_mem +@@ -1778,6 +1778,7 @@ static int spinand_remove(struct spi_mem static const struct spi_device_id spinand_ids[] = { { .name = "spi-nand" }, @@ -37,7 +37,7 @@ Signed-off-by: Daniel Golle { /* sentinel */ }, }; MODULE_DEVICE_TABLE(spi, spinand_ids); -@@ -1705,6 +1706,7 @@ MODULE_DEVICE_TABLE(spi, spinand_ids); +@@ -1785,6 +1786,7 @@ MODULE_DEVICE_TABLE(spi, spinand_ids); #ifdef CONFIG_OF static const struct of_device_id spinand_of_ids[] = { { .compatible = "spi-nand" }, diff --git a/target/linux/mediatek/patches-6.18/965-dts-mt7988a-add-trng-support.patch b/target/linux/mediatek/patches-6.18/965-dts-mt7988a-add-trng-support.patch index 341055e5d8..f08e9e5997 100644 --- a/target/linux/mediatek/patches-6.18/965-dts-mt7988a-add-trng-support.patch +++ b/target/linux/mediatek/patches-6.18/965-dts-mt7988a-add-trng-support.patch @@ -11,7 +11,7 @@ Signed-off-by: Marcos Alano --- --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -1327,4 +1327,8 @@ +@@ -1332,4 +1332,8 @@ , ; }; diff --git a/target/linux/mediatek/patches-6.18/966-pcie-mediatek-gen3-Add-WIFI-HW-reset-flow.patch b/target/linux/mediatek/patches-6.18/966-pcie-mediatek-gen3-Add-WIFI-HW-reset-flow.patch index ae60a9645f..53e9df9533 100644 --- a/target/linux/mediatek/patches-6.18/966-pcie-mediatek-gen3-Add-WIFI-HW-reset-flow.patch +++ b/target/linux/mediatek/patches-6.18/966-pcie-mediatek-gen3-Add-WIFI-HW-reset-flow.patch @@ -16,35 +16,26 @@ Signed-off-by: Jianguo Zhang --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c -@@ -10,6 +10,8 @@ +@@ -10,6 +10,7 @@ #include #include #include -+#include +#include #include #include - #include -@@ -18,6 +20,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -160,6 +163,8 @@ struct mtk_msi_set { - * @phy: PHY controller block - * @clks: PCIe clocks + #include +@@ -189,6 +190,8 @@ struct mtk_msi_set { * @num_clks: PCIe clocks count for this port + * @max_link_speed: Maximum link speed (PCIe Gen) for this port + * @num_lanes: Number of PCIe lanes for this port + * @wifi_reset: reset pin for WIFI chip + * @wifi_reset_delay_ms: delay time for WIFI chip reset * @irq: PCIe controller interrupt number * @saved_irq_state: IRQ enable state saved at suspend time * @irq_lock: lock protecting IRQ register access -@@ -181,6 +186,9 @@ struct mtk_gen3_pcie { - struct clk_bulk_data *clks; - int num_clks; +@@ -211,6 +214,9 @@ struct mtk_gen3_pcie { + u8 max_link_speed; + u8 num_lanes; + struct gpio_desc *wifi_reset; + u32 wifi_reset_delay_ms; @@ -52,7 +43,7 @@ Signed-off-by: Jianguo Zhang int irq; u32 saved_irq_state; raw_spinlock_t irq_lock; -@@ -402,6 +410,12 @@ static int mtk_pcie_startup_port(struct +@@ -464,6 +470,12 @@ static int mtk_pcie_startup_port(struct val |= PCIE_DISABLE_DVFSRC_VLT_REQ; writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG); @@ -62,11 +53,11 @@ Signed-off-by: Jianguo Zhang + gpiod_set_value_cansleep(pcie->wifi_reset, 0); + } + - /* Assert all reset signals */ - val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); - val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; -@@ -864,6 +878,20 @@ static int mtk_pcie_parse_port(struct mt - return pcie->num_clks; + /* + * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal + * causing occasional PCIe link down. In order to overcome the issue, +@@ -926,6 +938,20 @@ static int mtk_pcie_parse_port(struct mt + pcie->num_lanes = num_lanes; } + ret = of_property_read_u32(dev->of_node, "wifi-reset-msleep",