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realtek: dsa: rtl93xx: Deduplicate distribution algo setup

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rtl9310 and rtl9300 have two slots for configuration of packet distribution
algorithm that can be assigned to multiple LAG groups. They also have the
same field descriptions

Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/21740
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Harshal Gohel 2026-01-27 17:19:46 +00:00 committed by Hauke Mehrtens
parent 6e63fac22a
commit 286445257d
4 changed files with 69 additions and 102 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c
View File

@ -447,6 +447,55 @@ int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port)
return 0;
}
int rtldsa_93xx_lag_set_distribution_algorithm(struct rtl838x_switch_priv *priv,
int group, int algoidx, u32 algomsk)
{
bool is_l3 = false;
u32 newmask = 0;
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) {
is_l3 = true;
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT;
}
if (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) {
is_l3 = true;
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT;
}
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
is_l3 = true;
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
}
if (algomsk & TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT) {
is_l3 = true;
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DST_L4PORT_BIT;
}
if (is_l3) {
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SPA_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT;
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT;
if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT;
if (algomsk & TRUNK_DISTRIBUTION_ALGO_VLAN_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT;
} else {
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SPA_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT;
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT;
if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT;
if (algomsk & TRUNK_DISTRIBUTION_ALGO_VLAN_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT;
}
sw_w32(newmask, priv->r->trk_hash_ctrl + (algoidx << 2));
return 0;
}
int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group,
struct netdev_lag_upper_info *info)
{

32
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h
View File

@ -382,23 +382,21 @@
#define TRUNK_DISTRIBUTION_ALGO_VLAN_BIT BIT(7)
#define TRUNK_DISTRIBUTION_ALGO_MASKALL GENMASK(6, 0)
#define TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT 0x01
#define TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT 0x02
#define TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT 0x04
#define TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT 0x08
#define TRUNK_DISTRIBUTION_ALGO_L2_MASKALL 0xF
#define TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT BIT(0)
#define TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT BIT(1)
#define TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT BIT(2)
#define TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT BIT(3)
#define TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT 0x01
#define TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT 0x02
#define TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT 0x04
#define TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT 0x08
#define TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT 0x10
#define TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT 0x20
#define TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT 0x40
#define TRUNK_DISTRIBUTION_ALGO_L3_DST_L4PORT_BIT 0x80
#define TRUNK_DISTRIBUTION_ALGO_L3_PROTO_BIT 0x100
#define TRUNK_DISTRIBUTION_ALGO_L3_FLOW_LABEL_BIT 0x200
#define TRUNK_DISTRIBUTION_ALGO_L3_MASKALL 0x3FF
#define TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT BIT(4 + 0)
#define TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT BIT(4 + 1)
#define TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT BIT(4 + 2)
#define TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT BIT(4 + 3)
#define TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT BIT(4 + 4)
#define TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT BIT(4 + 5)
#define TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT BIT(4 + 6)
#define TRUNK_DISTRIBUTION_ALGO_L3_DST_L4PORT_BIT BIT(4 + 7)
#define TRUNK_DISTRIBUTION_ALGO_L3_PROTO_BIT BIT(4 + 8)
#define TRUNK_DISTRIBUTION_ALGO_L3_FLOW_LABEL_BIT BIT(4 + 9)
#define RTL838X_TRK_MBR_CTR (0x3E00)
#define RTL838X_TRK_HASH_IDX_CTRL (0x3E20)
@ -1448,6 +1446,8 @@ struct rtl838x_switch_priv {
void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv);
void rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv);
int rtldsa_93xx_lag_set_distribution_algorithm(struct rtl838x_switch_priv *priv,
int group, int algoidx, u32 algomsk);
void rtldsa_counters_lock_register(struct rtl838x_switch_priv *priv, int port)
__acquires(&priv->ports[port].counters.lock);

45
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c
View File

@ -2513,48 +2513,6 @@ static void rtl930x_set_egr_filter(int port, enum egr_filter state)
RTL930X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2)));
}
static int rtl930x_set_distribution_algorithm(struct rtl838x_switch_priv *priv, int group,
int algoidx, u32 algomsk)
{
u32 l3shift = 0;
u32 newmask = 0;
/* TODO: for now we set algoidx to 0 */
algoidx = 0;
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) {
l3shift = 4;
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT;
}
if (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) {
l3shift = 4;
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT;
}
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
l3shift = 4;
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
}
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
l3shift = 4;
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
}
if (l3shift == 4) {
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT;
if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT;
} else {
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT;
if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT;
}
sw_w32(newmask << l3shift, RTL930X_TRK_HASH_CTRL + (algoidx << 2));
return 0;
}
static void rtldsa_930x_led_get_forced(const struct device_node *node,
const u8 leds_in_set[4],
u8 forced_leds_per_port[RTL930X_CPU_PORT])
@ -2842,5 +2800,6 @@ const struct rtldsa_config rtldsa_930x_cfg = {
.enable_flood = rtldsa_930x_enable_flood,
.set_receive_management_action = rtldsa_930x_set_receive_management_action,
.qos_init = rtldsa_930x_qos_init,
.lag_set_distribution_algorithm = rtl930x_set_distribution_algorithm,
.trk_hash_ctrl = RTL930X_TRK_HASH_CTRL,
.lag_set_distribution_algorithm = rtldsa_93xx_lag_set_distribution_algorithm,
};

45
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c
View File

@ -1624,48 +1624,6 @@ static void rtl931x_set_egr_filter(int port, enum egr_filter state)
RTL931X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2)));
}
static int rtl931x_set_distribution_algorithm(struct rtl838x_switch_priv *priv, int group,
int algoidx, u32 algomsk)
{
u32 l3shift = 0;
u32 newmask = 0;
/* TODO: for now we set algoidx to 0 */
algoidx = 0;
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) {
l3shift = 4;
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT;
}
if (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) {
l3shift = 4;
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT;
}
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
l3shift = 4;
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
}
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
l3shift = 4;
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
}
if (l3shift == 4) {
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT;
if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT;
} else {
if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT;
if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
newmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT;
}
sw_w32(newmask << l3shift, RTL931X_TRK_HASH_CTRL + (algoidx << 2));
return 0;
}
static void rtldsa_931x_led_get_forced(const struct device_node *node,
const u8 leds_in_set[4],
u8 forced_leds_per_port[RTL931X_CPU_PORT])
@ -1966,5 +1924,6 @@ const struct rtldsa_config rtldsa_931x_cfg = {
.enable_flood = rtldsa_931x_enable_flood,
.set_receive_management_action = rtldsa_931x_set_receive_management_action,
.qos_init = rtldsa_931x_qos_init,
.lag_set_distribution_algorithm = rtl931x_set_distribution_algorithm,
.trk_hash_ctrl = RTL931X_TRK_HASH_CTRL,
.lag_set_distribution_algorithm = rtldsa_93xx_lag_set_distribution_algorithm,
};