diff --git a/target/linux/qualcommax/patches-6.12/0190-clk-qcom-cmnpll-Account-for-reference-clock-divider.patch b/target/linux/qualcommax/patches-6.12/0190-clk-qcom-cmnpll-Account-for-reference-clock-divider.patch
new file mode 100644
index 0000000000..089075a910
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.12/0190-clk-qcom-cmnpll-Account-for-reference-clock-divider.patch
@@ -0,0 +1,47 @@
+From: Luo Jie <jie.luo@oss.qualcomm.com>
+Date: Tue, 06 Jan 2026 21:35:10 -0800
+Subject: [PATCH v2 1/5] clk: qcom: cmnpll: Account for reference clock divider
+
+The clk_cmn_pll_recalc_rate() function must account for the reference clock
+divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms
+with a reference divider other than 1 calculate incorrect CMN PLL rates.
+For example, on IPQ5332 where the reference divider is 2, the computed rate
+becomes twice the actual output.
+
+Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before
+applying the 2 * FACTOR scaling. This yields the correct rate calculation:
+rate = (parent_rate / ref_div) * 2 * factor.
+
+Maintain backward compatibility with earlier platforms (e.g. IPQ9574,
+IPQ5424, IPQ5018) that use ref_div = 1.
+
+Fixes: f81715a4c87c ("clk: qcom: Add CMN PLL clock controller driver for IPQ SoC")
+Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
+--- a/drivers/clk/qcom/ipq-cmn-pll.c
++++ b/drivers/clk/qcom/ipq-cmn-pll.c
+@@ -186,7 +186,7 @@ static unsigned long clk_cmn_pll_recalc_
+ 					     unsigned long parent_rate)
+ {
+ 	struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw);
+-	u32 val, factor;
++	u32 val, factor, ref_div;
+ 
+ 	/*
+ 	 * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted
+@@ -194,8 +194,15 @@ static unsigned long clk_cmn_pll_recalc_
+ 	 */
+ 	regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val);
+ 	factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val);
++	if (WARN_ON(factor == 0))
++		factor = 1;
+ 
+-	return parent_rate * 2 * factor;
++	regmap_read(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, &val);
++	ref_div = FIELD_GET(CMN_PLL_REFCLK_DIV, val);
++	if (WARN_ON(ref_div == 0))
++		ref_div = 1;
++
++	return div_u64((u64)parent_rate * 2 * factor, ref_div);
+ }
+ 
+ static int clk_cmn_pll_determine_rate(struct clk_hw *hw,
diff --git a/target/linux/qualcommax/patches-6.12/0818-arm64-dts-qcom-ipq5018-fix-assigned-cmn-pll-clock-rate.patch b/target/linux/qualcommax/patches-6.12/0818-arm64-dts-qcom-ipq5018-fix-assigned-cmn-pll-clock-rate.patch
new file mode 100644
index 0000000000..6ab9ba3788
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.12/0818-arm64-dts-qcom-ipq5018-fix-assigned-cmn-pll-clock-rate.patch
@@ -0,0 +1,34 @@
+From 5b00a1e17e98e99cc31b4dc6584b9ef93b8a62c4 Mon Sep 17 00:00:00 2001
+From: George Moussalem <george.moussalem@outlook.com>
+Date: Wed, 07 Jan 2026 18:21:49 +0400
+Subject: [PATCH] arm64: dts: qcom: ipq5018: fix assigned cmn-pll clock rate
+MIME-Version: 1.0
+Content-Type: text/plain; charset="utf-8"
+Content-Transfer-Encoding: 7bit
+Message-Id: <20260107-ipq5018-cmn-pll-rate-v1-6-9ab50c40cb32@outlook.com>
+
+In IPQ5018, the reference clock to the CMN PLL block from the on-board
+Wi-Fi has its divider set to 2. This divider wasn't taken into
+consideration when calculating the CMN PLL clock rate which meant the
+resulting clock rate was doubled.
+
+With the reference clock divider being accounted for in the driver,
+correct the assigned clock rate to 4.8GHz.
+
+Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node")
+Signed-off-by: George Moussalem <george.moussalem@outlook.com>
+---
+ arch/arm64/boot/dts/qcom/ipq5018.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+@@ -266,7 +266,7 @@
+ 				      "sys";
+ 			#clock-cells = <1>;
+ 			assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;
+-			assigned-clock-rates-u64 = /bits/ 64 <9600000000>;
++			assigned-clock-rates-u64 = /bits/ 64 <4800000000>;
+ 		};
+ 
+ 		qfprom: qfprom@a0000 {