realtek: dts,build: create common Linksys LGS328x DTSI and image-recipe
This is in preparation for the addition of the LGS328MPC, which is based on the LGS328C. It also drops the unused UBINIZE_OPTS, as UBI is only used during runtime of the firmware, not during build. Signed-off-by: Jan-Henrik Bruhn <git@jhbruhn.de> Link: https://github.com/openwrt/openwrt/pull/23466 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
This commit is contained in:
Jan-Henrik Bruhn
Jonas Jelonek
parent
67740e311b
commit
455d73619c
@ -1,148 +1,9 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later or MIT)
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include "rtl93xx_linksys_lgs3xxc_nand_common.dtsi"
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#include "rtl9301_linksys_lgs328x_nand_common.dtsi"
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/ {
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compatible = "linksys,lgs328c", "realtek,rtl9301-soc";
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model = "Linksys LGS328C";
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>, /* 256 MiB lowmem */
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<0x20000000 0x10000000>; /* 256 MiB highmem */
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};
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};
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&i2c_mst1 {
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status = "okay";
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i2c2: i2c@2 {
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reg = <2>;
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};
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i2c3: i2c@3 {
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reg = <3>;
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};
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i2c4: i2c@4 {
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reg = <4>;
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};
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i2c5: i2c@5 {
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reg = <5>;
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};
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};
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&sfp0 {
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i2c-bus = <&i2c2>;
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};
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&sfp1 {
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i2c-bus = <&i2c3>;
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};
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&sfp2 {
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i2c-bus = <&i2c4>;
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};
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&sfp3 {
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i2c-bus = <&i2c5>;
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};
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&mdio_aux {
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status = "okay";
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gpio1: expander@0 {
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compatible = "realtek,rtl8231";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio1 0 0 37>;
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led-controller {
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compatible = "realtek,rtl8231-leds";
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status = "disabled";
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};
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};
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};
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&mdio_bus0 {
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PHY_C22(0, 0)
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PHY_C22(1, 1)
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PHY_C22(2, 2)
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PHY_C22(3, 3)
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PHY_C22(4, 4)
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PHY_C22(5, 5)
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PHY_C22(6, 6)
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PHY_C22(7, 7)
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};
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&mdio_bus1 {
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PHY_C22(8, 8)
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PHY_C22(9, 9)
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PHY_C22(10, 10)
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PHY_C22(11, 11)
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PHY_C22(12, 12)
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PHY_C22(13, 13)
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PHY_C22(14, 14)
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PHY_C22(15, 15)
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};
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&mdio_bus2 {
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PHY_C22(16, 16)
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PHY_C22(17, 17)
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PHY_C22(18, 18)
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PHY_C22(19, 19)
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PHY_C22(20, 20)
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PHY_C22(21, 21)
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PHY_C22(22, 22)
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PHY_C22(23, 23)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT_SDS(0, 1, 0, qsgmii)
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SWITCH_PORT_SDS(1, 2, 0, qsgmii)
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SWITCH_PORT_SDS(2, 3, 0, qsgmii)
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SWITCH_PORT_SDS(3, 4, 0, qsgmii)
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SWITCH_PORT_SDS(4, 5, 1, qsgmii)
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SWITCH_PORT_SDS(5, 6, 1, qsgmii)
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SWITCH_PORT_SDS(6, 7, 1, qsgmii)
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SWITCH_PORT_SDS(7, 8, 1, qsgmii)
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SWITCH_PORT_SDS(8, 9, 2, usxgmii)
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SWITCH_PORT_SDS(9, 10, 2, usxgmii)
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SWITCH_PORT_SDS(10, 11, 2, usxgmii)
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SWITCH_PORT_SDS(11, 12, 2, usxgmii)
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SWITCH_PORT_SDS(12, 13, 2, usxgmii)
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SWITCH_PORT_SDS(13, 14, 2, usxgmii)
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SWITCH_PORT_SDS(14, 15, 2, usxgmii)
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SWITCH_PORT_SDS(15, 16, 2, usxgmii)
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SWITCH_PORT_SDS(16, 17, 3, usxgmii)
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SWITCH_PORT_SDS(17, 18, 3, usxgmii)
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SWITCH_PORT_SDS(18, 19, 3, usxgmii)
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SWITCH_PORT_SDS(19, 20, 3, usxgmii)
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SWITCH_PORT_SDS(20, 21, 3, usxgmii)
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SWITCH_PORT_SDS(21, 22, 3, usxgmii)
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SWITCH_PORT_SDS(22, 23, 3, usxgmii)
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SWITCH_PORT_SDS(23, 24, 3, usxgmii)
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SWITCH_PORT_SFP(24, 25, 4, 0, 0)
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SWITCH_PORT_SFP(25, 26, 6, 0, 1)
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SWITCH_PORT_SFP(26, 27, 8, 0, 2)
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SWITCH_PORT_SFP(27, 28, 9, 0, 3)
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port@28 {
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reg = <28>;
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ethernet = <ðernet0>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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@ -0,0 +1,129 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later or MIT)
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include "rtl93xx_linksys_lgs3xxc_nand_common.dtsi"
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/ {
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>, /* 256 MiB lowmem */
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<0x20000000 0x10000000>; /* 256 MiB highmem */
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};
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};
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&i2c_mst1 {
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status = "okay";
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i2c2: i2c@2 { reg = <2>; };
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i2c3: i2c@3 { reg = <3>; };
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i2c4: i2c@4 { reg = <4>; };
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i2c5: i2c@5 { reg = <5>; };
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};
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&sfp0 { i2c-bus = <&i2c2>; };
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&sfp1 { i2c-bus = <&i2c3>; };
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&sfp2 { i2c-bus = <&i2c4>; };
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&sfp3 { i2c-bus = <&i2c5>; };
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&mdio_aux {
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status = "okay";
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gpio1: expander@0 {
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compatible = "realtek,rtl8231";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio1 0 0 37>;
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led-controller {
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compatible = "realtek,rtl8231-leds";
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status = "disabled";
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};
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};
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};
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&mdio_bus0 {
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PHY_C22(0, 0)
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PHY_C22(1, 1)
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PHY_C22(2, 2)
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PHY_C22(3, 3)
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PHY_C22(4, 4)
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PHY_C22(5, 5)
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PHY_C22(6, 6)
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PHY_C22(7, 7)
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};
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&mdio_bus1 {
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PHY_C22(8, 8)
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PHY_C22(9, 9)
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PHY_C22(10, 10)
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PHY_C22(11, 11)
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PHY_C22(12, 12)
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PHY_C22(13, 13)
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PHY_C22(14, 14)
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PHY_C22(15, 15)
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};
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&mdio_bus2 {
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PHY_C22(16, 16)
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PHY_C22(17, 17)
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PHY_C22(18, 18)
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PHY_C22(19, 19)
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PHY_C22(20, 20)
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PHY_C22(21, 21)
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PHY_C22(22, 22)
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PHY_C22(23, 23)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT_SDS(0, 1, 0, qsgmii)
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SWITCH_PORT_SDS(1, 2, 0, qsgmii)
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SWITCH_PORT_SDS(2, 3, 0, qsgmii)
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SWITCH_PORT_SDS(3, 4, 0, qsgmii)
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SWITCH_PORT_SDS(4, 5, 1, qsgmii)
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SWITCH_PORT_SDS(5, 6, 1, qsgmii)
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SWITCH_PORT_SDS(6, 7, 1, qsgmii)
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SWITCH_PORT_SDS(7, 8, 1, qsgmii)
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SWITCH_PORT_SDS(8, 9, 2, usxgmii)
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SWITCH_PORT_SDS(9, 10, 2, usxgmii)
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SWITCH_PORT_SDS(10, 11, 2, usxgmii)
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SWITCH_PORT_SDS(11, 12, 2, usxgmii)
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SWITCH_PORT_SDS(12, 13, 2, usxgmii)
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SWITCH_PORT_SDS(13, 14, 2, usxgmii)
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SWITCH_PORT_SDS(14, 15, 2, usxgmii)
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SWITCH_PORT_SDS(15, 16, 2, usxgmii)
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SWITCH_PORT_SDS(16, 17, 3, usxgmii)
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SWITCH_PORT_SDS(17, 18, 3, usxgmii)
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SWITCH_PORT_SDS(18, 19, 3, usxgmii)
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SWITCH_PORT_SDS(19, 20, 3, usxgmii)
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SWITCH_PORT_SDS(20, 21, 3, usxgmii)
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SWITCH_PORT_SDS(21, 22, 3, usxgmii)
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SWITCH_PORT_SDS(22, 23, 3, usxgmii)
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SWITCH_PORT_SDS(23, 24, 3, usxgmii)
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SWITCH_PORT_SFP(24, 25, 4, 0, 0)
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SWITCH_PORT_SFP(25, 26, 6, 0, 1)
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SWITCH_PORT_SFP(26, 27, 8, 0, 2)
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SWITCH_PORT_SFP(27, 28, 9, 0, 3)
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port@28 {
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reg = <28>;
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ethernet = <ðernet0>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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@ -2,19 +2,16 @@
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include ./common.mk
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define Device/linksys_lgs328c
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define Device/linksys_lgs328
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$(Device/uimage-rt-loader)
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SOC := rtl9301
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IMAGE_SIZE := 29696k
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KERNEL_SIZE := 10240k
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DEVICE_VENDOR := Linksys
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DEVICE_MODEL := LGS328C
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BELKIN_MODEL := BKS-RTL93xx
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BELKIN_HEADER := 0x07600001
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LINKSYS_MODEL := 60412040
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PAGESIZE := 2048
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BLOCKSIZE := 128k
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UBINIZE_OPTS := -E 5
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KERNEL := \
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$$(KERNEL) | \
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pad-to $$(BLOCKSIZE)
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@ -24,4 +21,10 @@ define Device/linksys_lgs328c
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sysupgrade-tar rootfs=$$$$@ | \
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append-metadata
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endef
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define Device/linksys_lgs328c
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$(Device/linksys_lgs328)
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DEVICE_MODEL := LGS328C
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LINKSYS_MODEL := 60412040
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endef
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TARGET_DEVICES += linksys_lgs328c
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