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realtek: add support for Zyxel XS1930-12F

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Add support for RTL9313-based Zyxel XS1930-12F, a 12-port Multi-Gig
switch with 8x 1G/10G SFP+ ports and 2x 100M/1G/2.5G/5G/10G RJ45.

Hardware
========

  - RTL9313 SoC
  - 256MiB DDR3 RAM (Nanya NT5CC128M16JR-EK)
  - 32MiB SPI-NOR Flash (Macronix MX25L25645G)
  - 10x 1G/10G SFP+
  - 2x 100M/1G/2.5G/5G/10G RJ45 (2x Aquantia AQR113C)
  - 2x RTL8231 for GPIO expansion + port LEDs
  - TI PM555 GPIO expander
  - LM96000 I2C hardware monitor
  - 3-pin fan
  - Front LEDs: PWR, SYS, CLOUD, LOCATOR
  - Console: TTL 3.3V, 115200 8N1
  - Software chain:
    - Bootbase/stripped-down U-Boot
    - BootExt
    - RAS/ZyNOS

Console
=======

The console port is a 4-pin header reachable without opening case.
Looking at the front port-side of the device, turn the device 90 degrees
clockwise. On this side, there's a rectangular opening in the honeycomb
structure. Pinout is (from left/front to right/back): GND RX TX VCC

Hardware quirks
===============

* SFP slots are disabled by default. Several GPIO lines on the PM555
  GPIO expander need to be pulled low to activate SFPs, one for each SFP
  slot. Otherwise modules cannot respond to I2C requests and GPIO signals
  do not reach the SoC.

* Fan can only be set to SLOW or FAST mode, no real speed/PWM control.

Disclaimer
==========

Flashing OpenWrt will overwrite BootExtension + ZyNOS. BootExtension
functionality (e.g. initramfs boot as mentioned below) is not available
anymore then. The U-boot/Bootbase still has some limited functionality
which can be used in emergency cases.

Installation
============

Simple web upgrade:

1. Take the OpenWrt factory.bin image generated by the build.

2. In the ZyNOS web UI, login and go to Maintenance -> Firmware Upgrade.

3. Under "Boot Image", make sure the Config Boot Image is set to 1. In
   other words, make sure the switch booted from firmware image 1 or it
   will do so on next reboot.
   This is crucial, otherwise OpenWrt cannot boot.

4. Below, select and upload the factory.bin image. After clicking
   upgrade, the image will be flashed.

5. After flashing has finished, reboot the switch. It will now boot into
   OpenWrt.

Initramfs boot
==============

NOTE: You need to use Xmodem transfer, the bootloader doesn't support
      Ymodem nor any networking.
      This only works as long as the default ZyNOS firmware is
      installed.

1. Connect to the switch using serial and interrupt the boot process
   to enter debug/recovery mode.

2. You need to unlock the bootloader. Use known methods [1] and [2] to
   obtain the unlock code and unlock the bootloader with:

   > ATEN 1,<unlock_code>

3. Upload the initramfs image using Xmodem:

   > ATUP <address>,<file_length>

   <address>: you may use any RAM address >= 0x80300000
   <file_length>: length of image in bytes

4. After the transfer has finished, boot the image with:

   > ATGO <address>

5. Wait for OpenWrt to boot. At this stage, it might be wise to create a
   backup/dump of the Flash partitions.

Return to stock firmware
========================

1. Download the firmware for the switch from Zyxel website.

2. Unzip the download, there should be a .bin file with a alphanumeric
   name.

3. Upload this file to running OpenWrt.

4. Run (use -F since the image doesn't have image metadata):

   > sysupgrade -F <stock-firmware>.bin

5. Wait for the sysupgrade to succeed and the switch reboot. At the next
   boot, ZyNOS should come up again.

Recovery
========

The Bootbase loader is actually a modified U-Boot variant. You can enter
it by spamming $ during the DRAM test.

The U-Boot shell can be unlocked with [1] and [2]. Note that the command
is slightly different, using a space instead of a comma, and lowercase:

> aten 1 <unlock_code>

You should now have more-or-less a standard RTK-U-boot shell from where
you can upload and write a new image to flash. Use e.g.:

> upgradeY image2 81000000 115200

Wait for the upgrade process to finish and reboot the switch.

===
[1] https://akao.co.uk/tools/zyxel_unlocker/
[2] https://www.ixo.de/info/zyxel_uclinux/

Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22909
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Jonas Jelonek 2025-11-22 23:09:23 +00:00 committed by Robert Marko
parent be54b1d008
commit 4a9c32b264
3 changed files with 351 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
target/linux/realtek/base-files/lib/upgrade/platform.sh
View File

@ -44,7 +44,8 @@ platform_do_upgrade() {
linksys,lgs352c)
nand_do_upgrade "$1"
;;
zyxel,xs1930-10)
zyxel,xs1930-10|\
zyxel,xs1930-12f)
PART_NAME="factory"
default_do_upgrade "$1"
;;

344
target/linux/realtek/dts/rtl9313_zyxel_xs1930-12f.dts Normal file
View File

@ -0,0 +1,344 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;
#include "rtl9313_zyxel_xs1930.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/mux/mux.h>
/ {
compatible = "zyxel,xs1930-12f", "realtek,rtl9313-soc";
model = "Zyxel XS1930-12F";
leds {
led_pwr_green: led-2 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led_pwr_red: led-3 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_POWER;
gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
};
led_cloud_green: led-4 {
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
led_cloud_red: led-5 {
color = <LED_COLOR_ID_RED>;
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
led_locator: led-6 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_INDICATOR;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
};
led_set: led_set@0 {
compatible = "realtek,rtl9300-leds";
active-low;
/* SFP ports */
led_set0 = <(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)
(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_1G | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)>;
/* Base-T ports */
led_set1 = <(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_5G | RTL93XX_LED_SET_2P5G |
RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_1G | RTL93XX_LED_SET_100M |
RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
(RTL93XX_LED_SET_5G | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)>;
};
sfp1: sfp-p1 {
compatible = "sff,sfp";
i2c-bus = <&i2c0>;
los-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 3 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 36 GPIO_ACTIVE_HIGH>;
};
sfp2: sfp-p2 {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 4 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 21 GPIO_ACTIVE_HIGH>;
};
sfp3: sfp-p3 {
compatible = "sff,sfp";
i2c-bus = <&i2c2>;
los-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
};
sfp4: sfp-p4 {
compatible = "sff,sfp";
i2c-bus = <&i2c3>;
los-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 6 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
};
sfp5: sfp-p5 {
compatible = "sff,sfp";
i2c-bus = <&i2c4>;
los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 7 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
};
sfp6: sfp-p6 {
compatible = "sff,sfp";
i2c-bus = <&i2c5>;
los-gpio = <&gpio1 34 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 29 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>;
};
sfp7: sfp-p7 {
compatible = "sff,sfp";
i2c-bus = <&i2c6>;
los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 31 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
};
sfp8: sfp-p8 {
compatible = "sff,sfp";
i2c-bus = <&i2c7>;
los-gpio = <&gpio1 32 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 10 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
};
sfp9: sfp-p9 {
compatible = "sff,sfp";
i2c-bus = <&i2c8>;
los-gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 11 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
};
sfp10: sfp-p10 {
compatible = "sff,sfp";
i2c-bus = <&i2c9>;
los-gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
};
};
&gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_disable_jtag>,
<&pinmux_disable_led_sync>;
};
&i2c_mst1 {
status = "okay";
i2c0: i2c@0 {
reg = <0>;
};
i2c1: i2c@1 {
reg = <1>;
};
i2c2: i2c@2 {
reg = <2>;
};
i2c3: i2c@3 {
reg = <3>;
};
i2c4: i2c@4 {
reg = <4>;
};
i2c5: i2c@5 {
reg = <5>;
};
};
&i2c_mst2 {
status = "okay";
i2c6: i2c@6 {
reg = <6>;
};
i2c7: i2c@7 {
reg = <7>;
};
i2c8: i2c@8 {
reg = <8>;
};
i2c9: i2c@9 {
reg = <9>;
};
i2c11: i2c@b {
reg = <0xb>;
gpio2: pca9555@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/* These GPIOs must be held low to activate SFP slots.
* Otherwise, neither power, signals nor I2C work.
*/
sfp_enable_hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>, /* SFP1 */
<1 GPIO_ACTIVE_LOW>, /* SFP2 */
<2 GPIO_ACTIVE_LOW>, /* SFP3 */
<3 GPIO_ACTIVE_LOW>, /* SFP4 */
<4 GPIO_ACTIVE_LOW>, /* SFP5 */
<5 GPIO_ACTIVE_LOW>, /* SFP6 */
<6 GPIO_ACTIVE_LOW>, /* SFP7 */
<7 GPIO_ACTIVE_LOW>, /* SFP8 */
<8 GPIO_ACTIVE_LOW>, /* SFP9 */
<9 GPIO_ACTIVE_LOW>; /* SFP10 */
output-high;
line-name = "enable-sfp-slots";
};
};
lm96000: lm96000@2e {
compatible = "national,lm85";
reg = <0x2e>;
};
};
};
&mdio_aux {
status = "okay";
gpio1: gpio@1f {
compatible = "realtek,rtl8231";
reg = <0x1f>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio1 0 0 37>;
led-controller {
compatible = "realtek,rtl8231-leds";
status = "disabled";
};
};
};
&mdio_ctrl {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_enable_mdc_mdio_1>,
<&pinmux_enable_mdc_mdio_2>;
};
&mdio_bus1 {
PHY_C45(54, 0) /* AQR113C */
};
&mdio_bus2 {
PHY_C45(55, 8) /* AQR113C */
};
&switch0 {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SFP(0, 1, 2, 0, 1)
SWITCH_PORT_SFP(8, 2, 3, 0, 2)
SWITCH_PORT_SFP(16, 3, 4, 0, 3)
SWITCH_PORT_SFP(24, 4, 5, 0, 4)
SWITCH_PORT_SFP(32, 5, 6, 0, 5)
SWITCH_PORT_SFP(40, 6, 7, 0, 6)
SWITCH_PORT_SFP(48, 7, 8, 0, 7)
SWITCH_PORT_SFP(50, 8, 9, 0, 8)
SWITCH_PORT_SFP(52, 9, 10, 0, 9)
SWITCH_PORT_SFP(53, 10, 11, 0, 10)
/* Base-T ports */
SWITCH_PORT_LED(54, 11, 12, 1, usxgmii)
SWITCH_PORT_LED(55, 12, 13, 1, usxgmii)
/* CPU port */
port@56 {
reg = <56>;
ethernet = <&ethernet0>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
&port54 {
managed = "in-band-status";
};
&port55 {
managed = "in-band-status";
};
&serdes2 {
realtek,pnswap-tx;
};
&serdes3 {
realtek,pnswap-tx;
};
&serdes4 {
realtek,pnswap-tx;
};
&serdes5 {
realtek,pnswap-tx;
};
&serdes6 {
realtek,pnswap-tx;
};
&serdes7 {
realtek,pnswap-tx;
};
&serdes8 {
realtek,pnswap-tx;
};
&serdes9 {
realtek,pnswap-tx;
};
&serdes10 {
realtek,pnswap-tx;
};
&serdes11 {
realtek,pnswap-tx;
};

5
target/linux/realtek/image/rtl931x.mk
View File

@ -62,3 +62,8 @@ define Device/zyxel_xs1930-10
endef
TARGET_DEVICES += zyxel_xs1930-10
define Device/zyxel_xs1930-12f
DEVICE_MODEL := XS1930-12F
$(Device/zyxel_xs1930)
endef
TARGET_DEVICES += zyxel_xs1930-12f