From 593df577312e531a04d944faec5237f6b52891f6 Mon Sep 17 00:00:00 2001
From: Markus Stockhausen <markus.stockhausen@gmx.de>
Date: Fri, 1 May 2026 19:04:01 +0200
Subject: [PATCH] realtek: dts: adapt RTL839x mdio bus topology

The RTL839x actually has two mdio busses.

- mdio bus 0 serves ports 0..23
- mdio bus 1 serves ports 24..51

This is baked into hardware and cannot be changed during mdio driver
setup with any register write. With the recent changes the driver
handles ports, phys and busses in a more logical way. So a port X
is assigned to a bus Y and a phy Z (on that bus). This gives a
mapping like

- port 16 <=> bus 0, address 16
- port 32 <=> bus 1, address 8

This unique assignment is used in the mdio driver as follows:

- Request to read bus 1, address 8
- Lookup corresponding port = 32
- Read from port 32

Looking at RTL839x it becomes clear that bus/phy => port lookup can
be achieved in multiple different ways. The simple reason is, that
for this device the driver cannot setup the smi topology. It is
baked into the hardware. So adding a "virtual" second bus does not
change the hardware access but allows to keep phy addresses below 32.
Making an example

mdio_bus0 {
  PHY_C22(40, 40)
}

resolves to port 40. But the same can be achieved with

mdio_bus1 {
  PHY_C22(40, 16)
}

In the first case the kernel sees bus/phy = 0/40 and in the second
case it sees bus/phy = 1/16. Both result in the access to the same
phy device on hardware port 40.

Use this analogy for RTL839x devices to match the real hardware
topology. For this change the existing dts and

- activate mdio bus 1 in rtl839x.dtsi
- rearrange devices with ports 24..51 to make use of bus 1

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23186
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 .../dts/rtl8392_zyxel_gs1920-24hp-v1.dts      | 10 ++--
 .../dts/rtl8393_d-link_dgs-1210-52.dts        | 58 ++++++++++---------
 .../dts/rtl8393_edgecore_ecs4100-12ph.dts     | 10 ++--
 .../realtek/dts/rtl8393_hpe_1920-48g-poe.dts  | 10 ++--
 .../realtek/dts/rtl8393_hpe_1920-48g.dts      | 10 ++--
 .../linux/realtek/dts/rtl8393_hpe_1920.dtsi   | 50 ++++++++--------
 .../realtek/dts/rtl8393_netgear_gs750e.dts    | 50 ++++++++--------
 .../dts/rtl8393_panasonic_m48eg-pn28480k.dts  | 50 ++++++++--------
 .../realtek/dts/rtl8393_tplink_sg2452p-v4.dts | 50 ++++++++--------
 .../realtek/dts/rtl8393_zyxel_gs1900-48.dtsi  | 50 ++++++++--------
 target/linux/realtek/dts/rtl839x.dtsi         |  5 ++
 11 files changed, 186 insertions(+), 167 deletions(-)

diff --git a/target/linux/realtek/dts/rtl8392_zyxel_gs1920-24hp-v1.dts b/target/linux/realtek/dts/rtl8392_zyxel_gs1920-24hp-v1.dts
index 1eff3f5ee3..bc71e445ce 100644
--- a/target/linux/realtek/dts/rtl8392_zyxel_gs1920-24hp-v1.dts
+++ b/target/linux/realtek/dts/rtl8392_zyxel_gs1920-24hp-v1.dts
@@ -70,12 +70,12 @@
 	};
 };
 
-&mdio_bus0 {
+&mdio_bus1 {
 	/* External phy RTL8214FC #1 */
-	PHY_C22_SFP(48, 48, 0)
-	PHY_C22_SFP(49, 49, 1)
-	PHY_C22_SFP(50, 50, 2)
-	PHY_C22_SFP(51, 51, 3)
+	PHY_C22_SFP(48, 24, 0)
+	PHY_C22_SFP(49, 25, 1)
+	PHY_C22_SFP(50, 26, 2)
+	PHY_C22_SFP(51, 27, 3)
 };
 
 &switch0 {
diff --git a/target/linux/realtek/dts/rtl8393_d-link_dgs-1210-52.dts b/target/linux/realtek/dts/rtl8393_d-link_dgs-1210-52.dts
index 4001219f7d..374fee05be 100644
--- a/target/linux/realtek/dts/rtl8393_d-link_dgs-1210-52.dts
+++ b/target/linux/realtek/dts/rtl8393_d-link_dgs-1210-52.dts
@@ -40,42 +40,44 @@
 	PHY_C22(21, 21)
 	PHY_C22(22, 22)
 	PHY_C22(23, 23)
+};
 
+&mdio_bus1 {
 	/* External phy RTL8218B #4 */
-	PHY_C22(24, 24)
-	PHY_C22(25, 25)
-	PHY_C22(26, 26)
-	PHY_C22(27, 27)
-	PHY_C22(28, 28)
-	PHY_C22(29, 29)
-	PHY_C22(30, 30)
-	PHY_C22(31, 31)
+	PHY_C22(24, 0)
+	PHY_C22(25, 1)
+	PHY_C22(26, 2)
+	PHY_C22(27, 3)
+	PHY_C22(28, 4)
+	PHY_C22(29, 5)
+	PHY_C22(30, 6)
+	PHY_C22(31, 7)
 
 	/* External phy RTL8218B #5 */
-	PHY_C22(32, 32)
-	PHY_C22(33, 33)
-	PHY_C22(34, 34)
-	PHY_C22(35, 35)
-	PHY_C22(36, 36)
-	PHY_C22(37, 37)
-	PHY_C22(38, 38)
-	PHY_C22(39, 39)
+	PHY_C22(32, 8)
+	PHY_C22(33, 9)
+	PHY_C22(34, 10)
+	PHY_C22(35, 11)
+	PHY_C22(36, 12)
+	PHY_C22(37, 13)
+	PHY_C22(38, 14)
+	PHY_C22(39, 15)
 
 	/* External phy RTL8218B #6 */
-	PHY_C22(40, 40)
-	PHY_C22(41, 41)
-	PHY_C22(42, 42)
-	PHY_C22(43, 43)
-	PHY_C22(44, 44)
-	PHY_C22(45, 45)
-	PHY_C22(46, 46)
-	PHY_C22(47, 47)
+	PHY_C22(40, 16)
+	PHY_C22(41, 17)
+	PHY_C22(42, 18)
+	PHY_C22(43, 19)
+	PHY_C22(44, 20)
+	PHY_C22(45, 21)
+	PHY_C22(46, 22)
+	PHY_C22(47, 23)
 
 	/* External phy RTL8214FC */
-	PHY_C22_SFP(48, 48, 0)
-	PHY_C22_SFP(49, 49, 1)
-	PHY_C22_SFP(50, 50, 2)
-	PHY_C22_SFP(51, 51, 3)
+	PHY_C22_SFP(48, 24, 0)
+	PHY_C22_SFP(49, 25, 1)
+	PHY_C22_SFP(50, 26, 2)
+	PHY_C22_SFP(51, 27, 3)
 };
 
 &switch0 {
diff --git a/target/linux/realtek/dts/rtl8393_edgecore_ecs4100-12ph.dts b/target/linux/realtek/dts/rtl8393_edgecore_ecs4100-12ph.dts
index 1b8aebf5d5..5c65ac91da 100644
--- a/target/linux/realtek/dts/rtl8393_edgecore_ecs4100-12ph.dts
+++ b/target/linux/realtek/dts/rtl8393_edgecore_ecs4100-12ph.dts
@@ -180,12 +180,14 @@
 	PHY_C22(5, 5)
 	PHY_C22(6, 6)
 	PHY_C22(7, 7)
+};
 
+&mdio_bus1 {
 	/* External phy RTL8214FC */
-	PHY_C22_SFP(48, 48, 0)
-	PHY_C22_SFP(49, 49, 1)
-	PHY_C22_SFP(50, 50, 2)
-	PHY_C22_SFP(51, 51, 3)
+	PHY_C22_SFP(48, 24, 0)
+	PHY_C22_SFP(49, 25, 1)
+	PHY_C22_SFP(50, 26, 2)
+	PHY_C22_SFP(51, 27, 3)
 };
 
 &spi0 {
diff --git a/target/linux/realtek/dts/rtl8393_hpe_1920-48g-poe.dts b/target/linux/realtek/dts/rtl8393_hpe_1920-48g-poe.dts
index db813768c7..8c138a5a3a 100644
--- a/target/linux/realtek/dts/rtl8393_hpe_1920-48g-poe.dts
+++ b/target/linux/realtek/dts/rtl8393_hpe_1920-48g-poe.dts
@@ -90,11 +90,11 @@
 	};
 };
 
-&mdio_bus0 {
-	PHY_C22_SFP(48, 48, 0)
-	PHY_C22_SFP(49, 49, 1)
-	PHY_C22_SFP(50, 50, 2)
-	PHY_C22_SFP(51, 51, 3)
+&mdio_bus1 {
+	PHY_C22_SFP(48, 24, 0)
+	PHY_C22_SFP(49, 25, 1)
+	PHY_C22_SFP(50, 26, 2)
+	PHY_C22_SFP(51, 27, 3)
 };
 
 &switch0 {
diff --git a/target/linux/realtek/dts/rtl8393_hpe_1920-48g.dts b/target/linux/realtek/dts/rtl8393_hpe_1920-48g.dts
index 5393e8fbac..6b0760d696 100644
--- a/target/linux/realtek/dts/rtl8393_hpe_1920-48g.dts
+++ b/target/linux/realtek/dts/rtl8393_hpe_1920-48g.dts
@@ -80,11 +80,11 @@
 
 };
 
-&mdio_bus0 {
-	PHY_C22_SFP(48, 48, 1)
-	PHY_C22_SFP(49, 49, 3)
-	PHY_C22_SFP(50, 50, 0)
-	PHY_C22_SFP(51, 51, 2)
+&mdio_bus1 {
+	PHY_C22_SFP(48, 24, 1)
+	PHY_C22_SFP(49, 25, 3)
+	PHY_C22_SFP(50, 26, 0)
+	PHY_C22_SFP(51, 27, 2)
 };
 
 
diff --git a/target/linux/realtek/dts/rtl8393_hpe_1920.dtsi b/target/linux/realtek/dts/rtl8393_hpe_1920.dtsi
index a4d5299a27..05ca0c4896 100644
--- a/target/linux/realtek/dts/rtl8393_hpe_1920.dtsi
+++ b/target/linux/realtek/dts/rtl8393_hpe_1920.dtsi
@@ -51,33 +51,35 @@
 	PHY_C22(21, 21)
 	PHY_C22(22, 22)
 	PHY_C22(23, 23)
+};
 
-	PHY_C22(24, 24)
-	PHY_C22(25, 25)
-	PHY_C22(26, 26)
-	PHY_C22(27, 27)
-	PHY_C22(28, 28)
-	PHY_C22(29, 29)
-	PHY_C22(30, 30)
-	PHY_C22(31, 31)
+&mdio_bus1 {
+	PHY_C22(24, 0)
+	PHY_C22(25, 1)
+	PHY_C22(26, 2)
+	PHY_C22(27, 3)
+	PHY_C22(28, 4)
+	PHY_C22(29, 5)
+	PHY_C22(30, 6)
+	PHY_C22(31, 7)
 
-	PHY_C22(32, 32)
-	PHY_C22(33, 33)
-	PHY_C22(34, 34)
-	PHY_C22(35, 35)
-	PHY_C22(36, 36)
-	PHY_C22(37, 37)
-	PHY_C22(38, 38)
-	PHY_C22(39, 39)
+	PHY_C22(32, 8)
+	PHY_C22(33, 9)
+	PHY_C22(34, 10)
+	PHY_C22(35, 11)
+	PHY_C22(36, 12)
+	PHY_C22(37, 13)
+	PHY_C22(38, 14)
+	PHY_C22(39, 15)
 
-	PHY_C22(40, 40)
-	PHY_C22(41, 41)
-	PHY_C22(42, 42)
-	PHY_C22(43, 43)
-	PHY_C22(44, 44)
-	PHY_C22(45, 45)
-	PHY_C22(46, 46)
-	PHY_C22(47, 47)
+	PHY_C22(40, 16)
+	PHY_C22(41, 17)
+	PHY_C22(42, 18)
+	PHY_C22(43, 19)
+	PHY_C22(44, 20)
+	PHY_C22(45, 21)
+	PHY_C22(46, 22)
+	PHY_C22(47, 23)
 };
 
 &switch0 {
diff --git a/target/linux/realtek/dts/rtl8393_netgear_gs750e.dts b/target/linux/realtek/dts/rtl8393_netgear_gs750e.dts
index 906a04d9a3..bfdc357205 100644
--- a/target/linux/realtek/dts/rtl8393_netgear_gs750e.dts
+++ b/target/linux/realtek/dts/rtl8393_netgear_gs750e.dts
@@ -135,36 +135,38 @@
 	PHY_C22(21, 21)
 	PHY_C22(22, 22)
 	PHY_C22(23, 23)
+};
 
+&mdio_bus1 {
 	/* External phy RTL8218B #4 */
-	PHY_C22(24, 24)
-	PHY_C22(25, 25)
-	PHY_C22(26, 26)
-	PHY_C22(27, 27)
-	PHY_C22(28, 28)
-	PHY_C22(29, 29)
-	PHY_C22(30, 30)
-	PHY_C22(31, 31)
+	PHY_C22(24, 0)
+	PHY_C22(25, 1)
+	PHY_C22(26, 2)
+	PHY_C22(27, 3)
+	PHY_C22(28, 4)
+	PHY_C22(29, 5)
+	PHY_C22(30, 6)
+	PHY_C22(31, 7)
 
 	/* External phy RTL8218B #5 */
-	PHY_C22(32, 32)
-	PHY_C22(33, 33)
-	PHY_C22(34, 34)
-	PHY_C22(35, 35)
-	PHY_C22(36, 36)
-	PHY_C22(37, 37)
-	PHY_C22(38, 38)
-	PHY_C22(39, 39)
+	PHY_C22(32, 8)
+	PHY_C22(33, 9)
+	PHY_C22(34, 10)
+	PHY_C22(35, 11)
+	PHY_C22(36, 12)
+	PHY_C22(37, 13)
+	PHY_C22(38, 14)
+	PHY_C22(39, 15)
 
 	/* External phy RTL8218B #6 */
-	PHY_C22(40, 40)
-	PHY_C22(41, 41)
-	PHY_C22(42, 42)
-	PHY_C22(43, 43)
-	PHY_C22(44, 44)
-	PHY_C22(45, 45)
-	PHY_C22(46, 46)
-	PHY_C22(47, 47)
+	PHY_C22(40, 16)
+	PHY_C22(41, 17)
+	PHY_C22(42, 18)
+	PHY_C22(43, 19)
+	PHY_C22(44, 20)
+	PHY_C22(45, 21)
+	PHY_C22(46, 22)
+	PHY_C22(47, 23)
 };
 
 &switch0 {
diff --git a/target/linux/realtek/dts/rtl8393_panasonic_m48eg-pn28480k.dts b/target/linux/realtek/dts/rtl8393_panasonic_m48eg-pn28480k.dts
index 5c811f36fa..783f933ad3 100644
--- a/target/linux/realtek/dts/rtl8393_panasonic_m48eg-pn28480k.dts
+++ b/target/linux/realtek/dts/rtl8393_panasonic_m48eg-pn28480k.dts
@@ -269,34 +269,36 @@
 	PHY_C22(21, 21)
 	PHY_C22(22, 22)
 	PHY_C22(23, 23)
+};
 
-	PHY_C22(24, 24)
-	PHY_C22(25, 25)
-	PHY_C22(26, 26)
-	PHY_C22(27, 27)
-	PHY_C22(28, 28)
-	PHY_C22(29, 29)
-	PHY_C22(30, 30)
-	PHY_C22(31, 31)
+&mdio_bus1 {
+	PHY_C22(24, 0)
+	PHY_C22(25, 1)
+	PHY_C22(26, 2)
+	PHY_C22(27, 3)
+	PHY_C22(28, 4)
+	PHY_C22(29, 5)
+	PHY_C22(30, 6)
+	PHY_C22(31, 7)
 
-	PHY_C22(32, 32)
-	PHY_C22(33, 33)
-	PHY_C22(34, 34)
-	PHY_C22(35, 35)
-	PHY_C22(36, 36)
-	PHY_C22(37, 37)
-	PHY_C22(38, 38)
-	PHY_C22(39, 39)
+	PHY_C22(32, 8)
+	PHY_C22(33, 9)
+	PHY_C22(34, 10)
+	PHY_C22(35, 11)
+	PHY_C22(36, 12)
+	PHY_C22(37, 13)
+	PHY_C22(38, 14)
+	PHY_C22(39, 15)
 
 	/* RTL8218FB */
-	PHY_C22(40, 40)
-	PHY_C22(41, 41)
-	PHY_C22(42, 42)
-	PHY_C22(43, 43)
-	PHY_C22(44, 44)
-	PHY_C22(45, 45)
-	PHY_C22(46, 46)
-	PHY_C22(47, 47)
+	PHY_C22(40, 16)
+	PHY_C22(41, 17)
+	PHY_C22(42, 18)
+	PHY_C22(43, 19)
+	PHY_C22(44, 20)
+	PHY_C22(45, 21)
+	PHY_C22(46, 22)
+	PHY_C22(47, 23)
 };
 
 &switch0 {
diff --git a/target/linux/realtek/dts/rtl8393_tplink_sg2452p-v4.dts b/target/linux/realtek/dts/rtl8393_tplink_sg2452p-v4.dts
index 10526efc5c..8d0823d728 100644
--- a/target/linux/realtek/dts/rtl8393_tplink_sg2452p-v4.dts
+++ b/target/linux/realtek/dts/rtl8393_tplink_sg2452p-v4.dts
@@ -309,36 +309,38 @@
 	PHY_C22(21, 21)
 	PHY_C22(22, 22)
 	PHY_C22(23, 23)
+};
 
+&mdio_bus1 {
 	/* External phy RTL8218B #4 */
-	PHY_C22(24, 24)
-	PHY_C22(25, 25)
-	PHY_C22(26, 26)
-	PHY_C22(27, 27)
-	PHY_C22(28, 28)
-	PHY_C22(29, 29)
-	PHY_C22(30, 30)
-	PHY_C22(31, 31)
+	PHY_C22(24, 0)
+	PHY_C22(25, 1)
+	PHY_C22(26, 2)
+	PHY_C22(27, 3)
+	PHY_C22(28, 4)
+	PHY_C22(29, 5)
+	PHY_C22(30, 6)
+	PHY_C22(31, 7)
 
 	/* External phy RTL8218B #5 */
-	PHY_C22(32, 32)
-	PHY_C22(33, 33)
-	PHY_C22(34, 34)
-	PHY_C22(35, 35)
-	PHY_C22(36, 36)
-	PHY_C22(37, 37)
-	PHY_C22(38, 38)
-	PHY_C22(39, 39)
+	PHY_C22(32, 8)
+	PHY_C22(33, 9)
+	PHY_C22(34, 10)
+	PHY_C22(35, 11)
+	PHY_C22(36, 12)
+	PHY_C22(37, 13)
+	PHY_C22(38, 14)
+	PHY_C22(39, 15)
 
 	/* External phy RTL8218B #6 */
-	PHY_C22(40, 40)
-	PHY_C22(41, 41)
-	PHY_C22(42, 42)
-	PHY_C22(43, 43)
-	PHY_C22(44, 44)
-	PHY_C22(45, 45)
-	PHY_C22(46, 46)
-	PHY_C22(47, 47)
+	PHY_C22(40, 16)
+	PHY_C22(41, 17)
+	PHY_C22(42, 18)
+	PHY_C22(43, 19)
+	PHY_C22(44, 20)
+	PHY_C22(45, 21)
+	PHY_C22(46, 22)
+	PHY_C22(47, 23)
 };
 
 &switch0 {
diff --git a/target/linux/realtek/dts/rtl8393_zyxel_gs1900-48.dtsi b/target/linux/realtek/dts/rtl8393_zyxel_gs1900-48.dtsi
index bd19062b54..b6fe0d8904 100644
--- a/target/linux/realtek/dts/rtl8393_zyxel_gs1900-48.dtsi
+++ b/target/linux/realtek/dts/rtl8393_zyxel_gs1900-48.dtsi
@@ -274,36 +274,38 @@
 	PHY_C22(21, 21)
 	PHY_C22(22, 22)
 	PHY_C22(23, 23)
+};
 
+&mdio_bus1 {
 	/* External phy RTL8218B #4 */
-	PHY_C22(24, 24)
-	PHY_C22(25, 25)
-	PHY_C22(26, 26)
-	PHY_C22(27, 27)
-	PHY_C22(28, 28)
-	PHY_C22(29, 29)
-	PHY_C22(30, 30)
-	PHY_C22(31, 31)
+	PHY_C22(24, 0)
+	PHY_C22(25, 1)
+	PHY_C22(26, 2)
+	PHY_C22(27, 3)
+	PHY_C22(28, 4)
+	PHY_C22(29, 5)
+	PHY_C22(30, 6)
+	PHY_C22(31, 7)
 
 	/* External phy RTL8218B #5 */
-	PHY_C22(32, 32)
-	PHY_C22(33, 33)
-	PHY_C22(34, 34)
-	PHY_C22(35, 35)
-	PHY_C22(36, 36)
-	PHY_C22(37, 37)
-	PHY_C22(38, 38)
-	PHY_C22(39, 39)
+	PHY_C22(32, 8)
+	PHY_C22(33, 9)
+	PHY_C22(34, 10)
+	PHY_C22(35, 11)
+	PHY_C22(36, 12)
+	PHY_C22(37, 13)
+	PHY_C22(38, 14)
+	PHY_C22(39, 15)
 
 	/* External phy RTL8218B #6 */
-	PHY_C22(40, 40)
-	PHY_C22(41, 41)
-	PHY_C22(42, 42)
-	PHY_C22(43, 43)
-	PHY_C22(44, 44)
-	PHY_C22(45, 45)
-	PHY_C22(46, 46)
-	PHY_C22(47, 47)
+	PHY_C22(40, 16)
+	PHY_C22(41, 17)
+	PHY_C22(42, 18)
+	PHY_C22(43, 19)
+	PHY_C22(44, 20)
+	PHY_C22(45, 21)
+	PHY_C22(46, 22)
+	PHY_C22(47, 23)
 };
 
 &switch0 {
diff --git a/target/linux/realtek/dts/rtl839x.dtsi b/target/linux/realtek/dts/rtl839x.dtsi
index c06773f83e..48b383687d 100644
--- a/target/linux/realtek/dts/rtl839x.dtsi
+++ b/target/linux/realtek/dts/rtl839x.dtsi
@@ -236,6 +236,11 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 			};
+			mdio_bus1: mdio-bus@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
 		};
 
 		mdio_aux: mdio-aux {