airoha: an7583: fix wrong clock for SPI and SLIC
Due to confusing Documentation, the SPI and SLIC base clock and
register location for Airoha AN7583 SoC were wrong.
Fix them with new updated Documentation source to provide correct
clock support.
Fixes: c5b12fc02a ("airoha: Introduce support for Airoha AN7583 SoC")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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@ -32,7 +32,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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+static const u32 gsw7583_base[] = { 540672000, 270336000, 400000000, 200000000 };
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+static const u32 emi7583_base[] = { 540672000, 480000000, 400000000, 300000000 };
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+static const u32 bus7583_base[] = { 600000000, 540672000, 480000000, 400000000 };
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+static const u32 spi7583_base[] = { 100000000, 12500000 };
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+static const u32 spi7583_base[] = { 400000000, 12500000 };
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+static const u32 npu7583_base[] = { 666000000, 800000000, 720000000, 600000000 };
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+static const u32 crypto7583_base[] = { 540672000, 400000000 };
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+static const u32 emmc7583_base[] = { 150000000, 200000000 };
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@ -92,7 +92,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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+
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+ .base_reg = REG_SPI_CLK_FREQ_SEL,
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+ .base_bits = 1,
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+ .base_shift = 0,
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+ .base_shift = 1,
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+ .base_values = slic_base,
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+ .n_base_values = ARRAY_SIZE(slic_base),
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+
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@ -107,7 +107,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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+
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+ .base_reg = REG_SPI_CLK_FREQ_SEL,
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+ .base_bits = 1,
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+ .base_shift = 1,
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+ .base_shift = 0,
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+ .base_values = spi7583_base,
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+ .n_base_values = ARRAY_SIZE(spi7583_base),
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+
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