From 716661d562443ce71fc8b302b98832d6923b4373 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Mon, 9 Feb 2026 09:34:37 +0000 Subject: [PATCH] sunxi: add T113-S3 support The Allwinner T113-s3 (sun8i) SoC features a dual-core Cortex-A7 ARM CPU and 128MB of DDR3 memory in the same physical package. It supports industrial temperature ranges. Most of the IP blocks are shared with the D1/D1s core. There are multiple variants of the SoC, which may vary in the included memory size, with some of them including a C906 RISC-V co-processor. Boards supported: - MangoPi MQDual T113 - wireless-only (RTL8723DS) - MYIR MYD-YT113 eMMC - 1Gbit ethernet (Motorcomm YT8531 PHY) - 4GByte eMMC - M.2-type slot for 4G/5G cards, plus 2x SIM slot - USB 2.0 ports - GPIO/I2C/SPI/CAN ports - FNLink 6131 (rtl8733bu) wifi module - MYIR MYD-YT113 SPI - Same as above but with 256Mbyte SPI-NAND flash instead of eMMC - Rongpin RP-T113 - 100Mbit ethernet (ICplus IP101GR PHY) - miniPCIe slot for 4G cards, plus 1x SIM slot - 3x USB 2.0 ports - RTL8723BS wireless - HYM8563 RTC - GPIO/I2C/SPI/CAN ports - Olimex T113-Olinuxino - 100Mbit ethernet (ICplus IP101GR) - UEXT connector (GPIO/I2C/SPI ports) - 1x USB 2.0 - audio jack, LEDC Installation: Use the standard sunxi installation to an SD-card. Signed-off-by: Zoltan HERPAI --- package/boot/uboot-sunxi/Makefile | 37 ++ .../400-net-add-ICPlus-PHY-driver.patch | 129 +++++++ ...0_pins-on-Port-E-PE2-PE3-on-D1s-T113.patch | 25 ++ ...port-for-MangoPI-MQDual-T113-variant.patch | 99 ++++++ ...rt-for-UART5-in-Port-E-group-on-T113.patch | 59 ++++ ...-add-support-for-MYIR-MYD113X-boards.patch | 322 ++++++++++++++++++ ...nxi-add-support-for-UART3-on-PE-pins.patch | 89 +++++ ...dd-support-for-Rongpin-RP-T113-board.patch | 149 ++++++++ ...unxi-add-support-for-emac-on-PG-pins.patch | 29 ++ ...sunxi-enable-emac-on-Rongpin-RP-T113.patch | 86 +++++ ...1-t113-add-SDC2-pinmux-on-PC2-7-pins.patch | 26 ++ ...10-sunxi-support-console-on-uart4-pd.patch | 38 +++ .../411-sunxi-dts-add-olinuxino-t113.patch | 250 ++++++++++++++ package/boot/uboot-sunxi/uEnv-t113.ttyS3.txt | 8 + package/boot/uboot-sunxi/uEnv-t113.ttyS5.txt | 8 + target/linux/sunxi/base-files/etc/inittab | 2 + target/linux/sunxi/config-6.18 | 2 + target/linux/sunxi/cortexa7/config-6.18 | 3 + target/linux/sunxi/image/cortexa7.mk | 48 +++ ...ner-d1-Add-QSPI-pins-node-for-pinmux.patch | 30 ++ ...-riscv-add-uart0_pins-on-Port-E-pins.patch | 25 ++ ...d-support-for-MangoPI-MQDual-T113-va.patch | 80 +++++ ...d-support-for-MYIR-MYD-YT113X-boards.patch | 298 ++++++++++++++++ ...dd-support-for-Rongpin-RP-T113-board.patch | 238 +++++++++++++ ...-dts-allwinner-d1-Add-thermal-sensor.patch | 46 +++ ...nxi-add-support-for-LctechPi-PC-T113.patch | 98 ++++++ .../551-dts-support-uart4-on-pd.patch | 15 + .../552-dts-add-olimex-t113-olinuxino.patch | 218 ++++++++++++ ...53-dts-add-aliases-to-olinuxino-t113.patch | 14 + ...allwinner-d1-add-led-controller-node.patch | 60 ++++ .../555-dts-add-rgb-leds-to-olinuxino.patch | 43 +++ 31 files changed, 2574 insertions(+) create mode 100644 package/boot/uboot-sunxi/patches/400-net-add-ICPlus-PHY-driver.patch create mode 100644 package/boot/uboot-sunxi/patches/401-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T113.patch create mode 100644 package/boot/uboot-sunxi/patches/402-sunxi-add-support-for-MangoPI-MQDual-T113-variant.patch create mode 100644 package/boot/uboot-sunxi/patches/403-sunxi-add-support-for-UART5-in-Port-E-group-on-T113.patch create mode 100644 package/boot/uboot-sunxi/patches/404-sunxi-add-support-for-MYIR-MYD113X-boards.patch create mode 100644 package/boot/uboot-sunxi/patches/405-sunxi-add-support-for-UART3-on-PE-pins.patch create mode 100644 package/boot/uboot-sunxi/patches/406-sunxi-add-support-for-Rongpin-RP-T113-board.patch create mode 100644 package/boot/uboot-sunxi/patches/407-sunxi-add-support-for-emac-on-PG-pins.patch create mode 100644 package/boot/uboot-sunxi/patches/408-sunxi-enable-emac-on-Rongpin-RP-T113.patch create mode 100644 package/boot/uboot-sunxi/patches/409-sunxi-r528-d1-t113-add-SDC2-pinmux-on-PC2-7-pins.patch create mode 100644 package/boot/uboot-sunxi/patches/410-sunxi-support-console-on-uart4-pd.patch create mode 100644 package/boot/uboot-sunxi/patches/411-sunxi-dts-add-olinuxino-t113.patch create mode 100644 package/boot/uboot-sunxi/uEnv-t113.ttyS3.txt create mode 100644 package/boot/uboot-sunxi/uEnv-t113.ttyS5.txt create mode 100644 target/linux/sunxi/patches-6.18/540-riscv-dts-allwinner-d1-Add-QSPI-pins-node-for-pinmux.patch create mode 100644 target/linux/sunxi/patches-6.18/541-ARM-dts-riscv-add-uart0_pins-on-Port-E-pins.patch create mode 100644 target/linux/sunxi/patches-6.18/542-ARM-dts-sunxi-add-support-for-MangoPI-MQDual-T113-va.patch create mode 100644 target/linux/sunxi/patches-6.18/543-ARM-dts-add-support-for-MYIR-MYD-YT113X-boards.patch create mode 100644 target/linux/sunxi/patches-6.18/544-ARM-dts-add-support-for-Rongpin-RP-T113-board.patch create mode 100644 target/linux/sunxi/patches-6.18/545-riscv-dts-allwinner-d1-Add-thermal-sensor.patch create mode 100644 target/linux/sunxi/patches-6.18/550-ARM-dts-sunxi-add-support-for-LctechPi-PC-T113.patch create mode 100644 target/linux/sunxi/patches-6.18/551-dts-support-uart4-on-pd.patch create mode 100644 target/linux/sunxi/patches-6.18/552-dts-add-olimex-t113-olinuxino.patch create mode 100644 target/linux/sunxi/patches-6.18/553-dts-add-aliases-to-olinuxino-t113.patch create mode 100644 target/linux/sunxi/patches-6.18/554-dts-allwinner-d1-add-led-controller-node.patch create mode 100644 target/linux/sunxi/patches-6.18/555-dts-add-rgb-leds-to-olinuxino.patch diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile index 4de31ce60b..f27c5628a5 100644 --- a/package/boot/uboot-sunxi/Makefile +++ b/package/boot/uboot-sunxi/Makefile @@ -406,8 +406,44 @@ define U-Boot/bananapi_p2_zero BUILD_DEVICES:=sinovoip_bpi-p2-zero endef +define U-Boot/mangopi_mqdual_t113 + BUILD_SUBTARGET:=cortexa7 + NAME:=MangoPi MQDual (T113) + BUILD_DEVICES:=widora_mangopi-mqdual-t113 +endef + +define U-Boot/myir_myd_t113x-emmc + BUILD_SUBTARGET:=cortexa7 + NAME:=MYIR MYD-T113X eMMC + BUILD_DEVICES:=myir_myd-yt113x-emmc + UENV:=t113.ttyS5 +endef + +define U-Boot/myir_myd_t113x-spi + BUILD_SUBTARGET:=cortexa7 + NAME:=MYIR MYD-T113X SPI + BUILD_DEVICES:=myir_myd-yt113x-spi + UENV:=t113.ttyS5 +endef + +define U-Boot/olimex_olinuxino + BUILD_SUBTARGET:=cortexa7 + NAME:=Olimex Olinuxino T113 + BUILD_DEVICES:=olimex_olinuxino +endef + +define U-Boot/rongpin_rp_t113 + BUILD_SUBTARGET:=cortexa7 + NAME:=Rongpin RP-T113 + BUILD_DEVICES:=rongpin_rp-t113 + UENV:=t113.ttyS3 +endef UBOOT_TARGETS := \ + mangopi_mqdual_t113 \ + myir_myd_t113x-emmc \ + myir_myd_t113x-spi \ + rongpin_rp_t113 \ a64-olinuxino \ a64-olinuxino-emmc \ A10-OLinuXino-Lime \ @@ -444,6 +480,7 @@ UBOOT_TARGETS := \ nanopi_neo2 \ nanopi_r1 \ nanopi_r1s_h5 \ + olimex_olinuxino \ orangepi_zero \ orangepi_r1 \ orangepi_one \ diff --git a/package/boot/uboot-sunxi/patches/400-net-add-ICPlus-PHY-driver.patch b/package/boot/uboot-sunxi/patches/400-net-add-ICPlus-PHY-driver.patch new file mode 100644 index 0000000000..c180921cd6 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/400-net-add-ICPlus-PHY-driver.patch @@ -0,0 +1,129 @@ +From 13339996e5ffd1cf9e276e6403aa14948f27c56a Mon Sep 17 00:00:00 2001 +From: Yegor Yefremov +Date: Wed, 28 Nov 2012 11:15:18 +0100 +Subject: [PATCH 4001/4018] net: add ICPlus PHY driver + +The driver code was taken from Linux kernel source: +drivers/net/phy/icplus.c + +Signed-off-by: Zoltan HERPAI +Signed-off-by: Yegor Yefremov +--- + drivers/net/phy/Kconfig | 3 ++ + drivers/net/phy/Makefile | 1 + + drivers/net/phy/icplus.c | 87 ++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 91 insertions(+) + create mode 100644 drivers/net/phy/icplus.c + +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -173,6 +173,9 @@ config PHY_DAVICOM + config PHY_ET1011C + bool "LSI TruePHY ET1011C support" + ++config PHY_ICPLUS ++ bool "IC+ IP101 Ethernet PHY support" ++ + config PHY_LXT + bool "LXT971 Ethernet PHY support" + +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_PHY_CORTINA) += cortina.o + obj-$(CONFIG_PHY_CORTINA_ACCESS) += ca_phy.o + obj-$(CONFIG_PHY_DAVICOM) += davicom.o + obj-$(CONFIG_PHY_ET1011C) += et1011c.o ++obj-$(CONFIG_PHY_ICPLUS) += icplus.o + obj-$(CONFIG_PHY_LXT) += lxt.o + obj-$(CONFIG_PHY_MARVELL) += marvell.o + obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o +--- /dev/null ++++ b/drivers/net/phy/icplus.c +@@ -0,0 +1,87 @@ ++/* ++ * ICPlus PHY drivers ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Copyright (c) 2007 Freescale Semiconductor, Inc. ++ * ++ */ ++#include ++ ++/* IP101A/G - IP1001 */ ++#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */ ++#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */ ++#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */ ++#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */ ++#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */ ++#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */ ++#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */ ++#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED ++ ++static int ip1001_config(struct phy_device *phydev) ++{ ++ int c; ++ ++ /* Enable Auto Power Saving mode */ ++ c = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2); ++ if (c < 0) ++ return c; ++ c |= IP1001_APS_ON; ++ c = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c); ++ if (c < 0) ++ return c; ++ ++ /* INTR pin used: speed/link/duplex will cause an interrupt */ ++ c = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS, ++ IP101A_G_IRQ_DEFAULT); ++ if (c < 0) ++ return c; ++ ++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { ++ /* ++ * Additional delay (2ns) used to adjust RX clock phase ++ * at RGMII interface ++ */ ++ c = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS); ++ if (c < 0) ++ return c; ++ ++ c |= IP1001_PHASE_SEL_MASK; ++ c = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS, ++ c); ++ if (c < 0) ++ return c; ++ } ++ ++ return 0; ++} ++ ++static int ip1001_startup(struct phy_device *phydev) ++{ ++ genphy_update_link(phydev); ++ genphy_parse_link(phydev); ++ ++ return 0; ++} ++U_BOOT_PHY_DRIVER(lxt971) = { ++ .name = "ICPlus IP1001", ++ .uid = 0x02430d90, ++ .mask = 0x0ffffff0, ++ .features = PHY_GBIT_FEATURES, ++ .config = &ip1001_config, ++ .startup = &ip1001_startup, ++ .shutdown = &genphy_shutdown, ++}; diff --git a/package/boot/uboot-sunxi/patches/401-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T113.patch b/package/boot/uboot-sunxi/patches/401-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T113.patch new file mode 100644 index 0000000000..7ca5fa30c2 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/401-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T113.patch @@ -0,0 +1,25 @@ +From 1be7791f220325b0d6f42c3f2c383d8423936942 Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sat, 3 Jun 2023 00:52:04 +0200 +Subject: [PATCH 4005/4018] sunxi: add uart0_pins on Port E PE2/PE3 on D1s/T133 + +Signed-off-by: Zoltan HERPAI +--- + arch/riscv/dts/sunxi-d1s-t113.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/riscv/dts/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi +@@ -143,6 +143,12 @@ + pins = "PB6", "PB7"; + function = "uart3"; + }; ++ ++ /omit-if-no-ref/ ++ uart0_pins: uart0-pins { ++ pins = "PE2", "PE3"; ++ function = "uart0"; ++ }; + }; + + ccu: clock-controller@2001000 { diff --git a/package/boot/uboot-sunxi/patches/402-sunxi-add-support-for-MangoPI-MQDual-T113-variant.patch b/package/boot/uboot-sunxi/patches/402-sunxi-add-support-for-MangoPI-MQDual-T113-variant.patch new file mode 100644 index 0000000000..3a9901ad6a --- /dev/null +++ b/package/boot/uboot-sunxi/patches/402-sunxi-add-support-for-MangoPI-MQDual-T113-variant.patch @@ -0,0 +1,99 @@ +From 92c2cd5838666718cc55ee21f02e6959ab40e463 Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sat, 3 Jun 2023 00:52:40 +0200 +Subject: [PATCH 4006/4018] sunxi: add support for MangoPI MQDual T113 variant + +Signed-off-by: Zoltan HERPAI +--- + arch/arm/dts/Makefile | 3 +- + .../dts/sun8i-t113s-mangopi-mqdual-t113.dts | 50 +++++++++++++++++++ + configs/mangopi_mqdual_t113_defconfig | 17 +++++++ + 3 files changed, 69 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/dts/sun8i-t113s-mangopi-mqdual-t113.dts + create mode 100644 configs/mangopi_mqdual_t113_defconfig + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -651,7 +651,8 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ + sun8i-t3-cqa3t-bv3.dtb \ + sun8i-v40-bananapi-m2-berry.dtb + dtb-$(CONFIG_MACH_SUN8I_R528) += \ +- sun8i-t113s-mangopi-mq-r-t113.dtb ++ sun8i-t113s-mangopi-mq-r-t113.dtb \ ++ sun8i-t113s-mangopi-mqdual-t113.dtb + dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-bananapi-m2-plus.dtb \ + sun50i-h5-emlid-neutis-n5-devboard.dtb \ +--- /dev/null ++++ b/arch/arm/dts/sun8i-t113s-mangopi-mqdual-t113.dts +@@ -0,0 +1,50 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2022 Arm Ltd. ++ ++#include ++ ++/dts-v1/; ++ ++#include "sun8i-t113s.dtsi" ++#include "sunxi-d1s-t113-mangopi-mq-r.dtsi" ++ ++/ { ++ model = "MangoPi MQDual T113"; ++ compatible = "widora,mangopi-mqdual-t113", "allwinner,sun8i-t113s"; ++ ++ aliases { ++ serial0 = &uart0; ++ ethernet0 = &rtl8189ftv; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&cpu1 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&mmc1 { ++ rtl8189ftv: wifi@1 { ++ reg = <1>; ++ interrupt-parent = <&pio>; ++ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++ status = "okay"; ++}; ++ ++&uart3 { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/configs/mangopi_mqdual_t113_defconfig +@@ -0,0 +1,17 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-mangopi-mqdual-t113" ++CONFIG_SUNXI_MINIMUM_DRAM_MB=128 ++CONFIG_SPL=y ++CONFIG_MACH_SUN8I_R528=y ++CONFIG_CONS_INDEX=1 ++CONFIG_MMC0_CD_PIN="PF6" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_MONITOR_LEN=786432 ++CONFIG_DRAM_CLK=792 ++CONFIG_DRAM_ZQ=8092667 ++CONFIG_DRAM_SUNXI_ODT_EN=0 ++CONFIG_DRAM_SUNXI_TPR0=0x004a2195 ++CONFIG_DRAM_SUNXI_TPR11=0x340000 ++CONFIG_DRAM_SUNXI_TPR12=0x46 ++CONFIG_DRAM_SUNXI_TPR13=0x34000100 diff --git a/package/boot/uboot-sunxi/patches/403-sunxi-add-support-for-UART5-in-Port-E-group-on-T113.patch b/package/boot/uboot-sunxi/patches/403-sunxi-add-support-for-UART5-in-Port-E-group-on-T113.patch new file mode 100644 index 0000000000..892ee76fc5 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/403-sunxi-add-support-for-UART5-in-Port-E-group-on-T113.patch @@ -0,0 +1,59 @@ +From 41ee73b7621cd4b689ad9c9f107aff2e8c30ef2f Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sat, 3 Jun 2023 23:41:31 +0200 +Subject: [PATCH 4007/4018] sunxi: add support for UART5 in Port E group on + T133 + +Signed-off-by: Zoltan HERPAI +--- + arch/arm/include/asm/arch-sunxi/serial.h | 1 + + arch/arm/mach-sunxi/board.c | 4 ++++ + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 + + include/configs/sunxi-common.h | 3 +++ + 4 files changed, 9 insertions(+) + +--- a/arch/arm/include/asm/arch-sunxi/serial.h ++++ b/arch/arm/include/asm/arch-sunxi/serial.h +@@ -20,6 +20,7 @@ + #elif defined(CONFIG_SUNXI_GEN_NCAT2) + #define SUNXI_UART0_BASE 0x02500000 + #define SUNXI_R_UART_BASE 0 // 0x07080000 (?> ++#define SUNXI_UART5_BASE (SUNXI_UART0_BASE + 0x1400) + #else + #define SUNXI_UART0_BASE 0x01c28000 + #define SUNXI_R_UART_BASE 0x01f02800 +--- a/arch/arm/mach-sunxi/board.c ++++ b/arch/arm/mach-sunxi/board.c +@@ -185,6 +185,10 @@ static int gpio_init(void) + sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); + sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); + sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); ++#elif CONFIG_CONS_INDEX == 6 && defined(CONFIG_MACH_SUN8I_R528) ++ sunxi_gpio_set_cfgpin(SUNXI_GPE(6), 9); ++ sunxi_gpio_set_cfgpin(SUNXI_GPE(7), 9); ++ sunxi_gpio_set_pull(SUNXI_GPE(7), SUNXI_GPIO_PULL_UP); + #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \ + !defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1); +--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +@@ -615,6 +615,7 @@ static const struct sunxi_pinctrl_functi + { "uart1", 2 }, /* PG6-PG7 */ + { "uart2", 7 }, /* PB0-PB1 */ + { "uart3", 7 }, /* PB6-PB7 */ ++ { "uart5", 3 }, /* PE6-PE7 */ + }; + + static const struct sunxi_pinctrl_desc __maybe_unused sun20i_d1_pinctrl_desc = { +--- a/include/configs/sunxi-common.h ++++ b/include/configs/sunxi-common.h +@@ -30,6 +30,9 @@ + # define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE + # define CFG_SYS_NS16550_COM4 SUNXI_UART3_BASE + # define CFG_SYS_NS16550_COM5 SUNXI_R_UART_BASE ++#if defined(CONFIG_SUNXI_GEN_NCAT2) ++# define CFG_SYS_NS16550_COM6 SUNXI_UART5_BASE ++#endif + #endif + + /**************************************************************************** diff --git a/package/boot/uboot-sunxi/patches/404-sunxi-add-support-for-MYIR-MYD113X-boards.patch b/package/boot/uboot-sunxi/patches/404-sunxi-add-support-for-MYIR-MYD113X-boards.patch new file mode 100644 index 0000000000..9626d242cc --- /dev/null +++ b/package/boot/uboot-sunxi/patches/404-sunxi-add-support-for-MYIR-MYD113X-boards.patch @@ -0,0 +1,322 @@ +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -652,7 +652,9 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ + sun8i-v40-bananapi-m2-berry.dtb + dtb-$(CONFIG_MACH_SUN8I_R528) += \ + sun8i-t113s-mangopi-mq-r-t113.dtb \ +- sun8i-t113s-mangopi-mqdual-t113.dtb ++ sun8i-t113s-mangopi-mqdual-t113.dtb \ ++ sun8i-t113s-myir-myd-yt113x-emmc.dtb \ ++ sun8i-t113s-myir-myd-yt113x-spi.dtb + dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-bananapi-m2-plus.dtb \ + sun50i-h5-emlid-neutis-n5-devboard.dtb \ +--- /dev/null ++++ b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-emmc.dts +@@ -0,0 +1,32 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2022 Arm Ltd. ++ ++#include ++ ++/dts-v1/; ++ ++#include "sun8i-t113s-myir-myd-yt113x.dtsi" ++ ++/ { ++ model = "MYIR MYD-YT113X (eMMC)"; ++}; ++ ++&mmc2_pins { ++ bias-pull-up; ++ drive-strength = <40>; ++}; ++ ++&mmc2 { ++ pinctrl-0 = <&mmc2_pins>; ++ pinctrl-names = "default"; ++ vmmc-supply = <®_3v3>; ++ non-removable; ++ bus-width = <4>; ++ status = "okay"; ++ ++ emmc: emmc@0 { ++ reg = <0>; ++ compatible = "mmc-card"; ++ broken-hpi; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts +@@ -0,0 +1,50 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2025 Zoltan HERPAI ++ ++#include ++ ++/dts-v1/; ++ ++#include "sun8i-t113s-myir-myd-yt113x.dtsi" ++ ++/ { ++ model = "MYIR MYD-YT113X (SPI)"; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ status = "okay"; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "boot0"; ++ reg = <0x0 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "uboot"; ++ reg = <0x0 0x300000>; ++ }; ++ ++ partition@400000 { ++ label = "secure_storage"; ++ reg = <0x0 0x400000>; ++ }; ++ ++ partition@500000 { ++ label = "sys"; ++ reg = <0x0 0xfb00000>; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/configs/myir_myd_t113x-emmc_defconfig +@@ -0,0 +1,29 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-myir-myd-yt113x-emmc" ++CONFIG_SUNXI_MINIMUM_DRAM_MB=128 ++CONFIG_SPL=y ++CONFIG_MACH_SUN8I_R528=y ++CONFIG_CONS_INDEX=6 ++CONFIG_MMC0_CD_PIN="PF6" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_MONITOR_LEN=786432 ++CONFIG_DRAM_CLK=792 ++CONFIG_DRAM_ZQ=8092667 ++CONFIG_DRAM_SUNXI_ODT_EN=0 ++CONFIG_DRAM_SUNXI_TPR0=0x004a2195 ++CONFIG_DRAM_SUNXI_TPR11=0x340000 ++CONFIG_DRAM_SUNXI_TPR12=0x46 ++CONFIG_DRAM_SUNXI_TPR13=0x34000100 ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_PHY_MOTORCOMM=y ++CONFIG_SUN8I_EMAC=y ++CONFIG_RGMII=y ++CONFIG_RMII=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_IO_VOLTAGE=y ++CONFIG_SPL_MMC_IO_VOLTAGE=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_SPL_MMC_HS200_SUPPORT=y +--- /dev/null ++++ b/configs/myir_myd_t113x-spi_defconfig +@@ -0,0 +1,39 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-myir-myd-yt113x-spi" ++CONFIG_SUNXI_MINIMUM_DRAM_MB=128 ++CONFIG_SPL=y ++CONFIG_SPL_SPI_SUNXI=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MACH_SUN8I_R528=y ++CONFIG_CONS_INDEX=6 ++CONFIG_MMC0_CD_PIN="PF6" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_MONITOR_LEN=786432 ++CONFIG_DRAM_CLK=792 ++CONFIG_DRAM_ZQ=8092667 ++CONFIG_DRAM_SUNXI_ODT_EN=0 ++CONFIG_DRAM_SUNXI_TPR0=0x004a2195 ++CONFIG_DRAM_SUNXI_TPR11=0x340000 ++CONFIG_DRAM_SUNXI_TPR12=0x46 ++CONFIG_DRAM_SUNXI_TPR13=0x34000100 ++CONFIG_CLK_SUN20I_D1=y ++CONFIG_PHY_MOTORCOMM=y ++CONFIG_SUN8I_EMAC=y ++CONFIG_RGMII=y ++CONFIG_RMII=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_SYS_MTDPARTS_RUNTIME=y ++CONFIG_NAND_STM32_FMC2=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI=y ++CONFIG_MTD_UBI_FASTMAP=y +--- /dev/null ++++ b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x.dtsi +@@ -0,0 +1,144 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2025 Zoltan HERPAI ++ ++#include ++ ++/dts-v1/; ++ ++#include "sun8i-t113s.dtsi" ++#include ++ ++/ { ++ compatible = "myir,myd-yt113x", "myir,myc-yt113x", "allwinner,sun8i-t113s"; ++ ++ aliases { ++ serial5 = &uart5; ++ }; ++ ++ chosen { ++ stdout-path = "serial5:115200n8"; ++ }; ++ ++ reg_vcc5v: regulator-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ /* XC6206 LDO on the board */ ++ reg_avdd2v8: regulator-avdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "avdd2v8"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ vin-supply = <®_3v3>; ++ }; ++ ++ /* SY8008 DC/DC regulator on the board */ ++ reg_3v3: regulator-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ reg_vcc_core: regulator-core { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-core"; ++ regulator-min-microvolt = <880000>; ++ regulator-max-microvolt = <880000>; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */ ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&cpu1 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&dcxo { ++ clock-frequency = <24000000>; ++}; ++ ++&mmc0 { ++ pinctrl-0 = <&mmc0_pins>; ++ pinctrl-names = "default"; ++ vmmc-supply = <®_3v3>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&pio { ++ vcc-pb-supply = <®_3v3>; ++ vcc-pd-supply = <®_3v3>; ++ vcc-pe-supply = <®_avdd2v8>; ++ vcc-pf-supply = <®_3v3>; ++ vcc-pg-supply = <®_3v3>; ++ ++ rgmii_pg_pins: rgmii-pg-pins { ++ pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", ++ "PG6", "PG7", "PG8", "PG9", "PG10", ++ "PG12", "PG14", "PG15"; ++ function = "emac"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5_pins: uart5-pins { ++ pins = "PE6", "PE7"; ++ function = "uart5"; ++ }; ++}; ++ ++&uart3 { ++ status = "disabled"; ++}; ++ ++&uart5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart5_pins>; ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pg_pins>; ++ ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii-id"; ++ ++ status = "okay"; ++}; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@7 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <7>; ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; diff --git a/package/boot/uboot-sunxi/patches/405-sunxi-add-support-for-UART3-on-PE-pins.patch b/package/boot/uboot-sunxi/patches/405-sunxi-add-support-for-UART3-on-PE-pins.patch new file mode 100644 index 0000000000..875981b1a0 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/405-sunxi-add-support-for-UART3-on-PE-pins.patch @@ -0,0 +1,89 @@ +From e50a38fcd689bb3bc1e6cf191f482dbc179420b3 Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sat, 3 Jun 2023 23:57:46 +0200 +Subject: [PATCH 4009/4018] sunxi: add support for UART3 on PE pins + +Some boards use Port E pins for muxing the UART3 as console. Add a new +Kconfig option allowing to select this (mimicking MMC_PINS_PH). + +Pinmux taken from https://bbs.aw-ol.com/assets/uploads/files/1648883311844-t113-s3_datasheet_v1.2.pdf + +Signed-off-by: Zoltan HERPAI +--- + arch/arm/mach-sunxi/Kconfig | 6 ++++++ + arch/arm/mach-sunxi/board.c | 10 ++++++++-- + arch/riscv/dts/sunxi-d1s-t113.dtsi | 6 ++++++ + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 4 ++++ + 4 files changed, 24 insertions(+), 2 deletions(-) + +--- a/arch/arm/mach-sunxi/Kconfig ++++ b/arch/arm/mach-sunxi/Kconfig +@@ -897,6 +897,12 @@ config UART0_PORT_F + at the same time, the system can be only booted in the FEL mode. + Only enable this if you really know what you are doing. + ++config UART3_PINS_PE ++ bool "Pins for uart3 are on Port E" ++ ---help--- ++ Select this option for boards where uart3 uses the Port E pinmux. ++ (Some T113-S3 boards use uart3 as console.) ++ + config OLD_SUNXI_KERNEL_COMPAT + bool "Enable workarounds for booting old kernels" + ---help--- +--- a/arch/arm/mach-sunxi/board.c ++++ b/arch/arm/mach-sunxi/board.c +@@ -178,16 +178,22 @@ static int gpio_init(void) + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); + #elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_R528) ++#if defined(CONFIG_UART3_PINS_PE) ++ sunxi_gpio_set_cfgpin(SUNXI_GPE(8), 5); ++ sunxi_gpio_set_cfgpin(SUNXI_GPE(9), 5); ++ sunxi_gpio_set_pull(SUNXI_GPE(9), SUNXI_GPIO_PULL_UP); ++#else + sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7); + sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7); + sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP); ++#endif + #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); + sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); + sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); + #elif CONFIG_CONS_INDEX == 6 && defined(CONFIG_MACH_SUN8I_R528) +- sunxi_gpio_set_cfgpin(SUNXI_GPE(6), 9); +- sunxi_gpio_set_cfgpin(SUNXI_GPE(7), 9); ++ sunxi_gpio_set_cfgpin(SUNXI_GPE(6), 3); ++ sunxi_gpio_set_cfgpin(SUNXI_GPE(7), 3); + sunxi_gpio_set_pull(SUNXI_GPE(7), SUNXI_GPIO_PULL_UP); + #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \ + !defined(CONFIG_MACH_SUN8I_R40) +--- a/arch/riscv/dts/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi +@@ -145,6 +145,12 @@ + }; + + /omit-if-no-ref/ ++ uart3_pe_pins: uart3-pe-pins { ++ pins = "PE8", "PE9"; ++ function = "uart3"; ++ }; ++ ++ /omit-if-no-ref/ + uart0_pins: uart0-pins { + pins = "PE2", "PE3"; + function = "uart0"; +--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +@@ -614,7 +614,11 @@ static const struct sunxi_pinctrl_functi + #endif + { "uart1", 2 }, /* PG6-PG7 */ + { "uart2", 7 }, /* PB0-PB1 */ ++#if IS_ENABLED(CONFIG_UART3_PINS_PE) ++ { "uart3", 5 }, /* PE8-PE9 */ ++#else + { "uart3", 7 }, /* PB6-PB7 */ ++#endif + { "uart5", 3 }, /* PE6-PE7 */ + }; + diff --git a/package/boot/uboot-sunxi/patches/406-sunxi-add-support-for-Rongpin-RP-T113-board.patch b/package/boot/uboot-sunxi/patches/406-sunxi-add-support-for-Rongpin-RP-T113-board.patch new file mode 100644 index 0000000000..e373eccf95 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/406-sunxi-add-support-for-Rongpin-RP-T113-board.patch @@ -0,0 +1,149 @@ +From b1e6908b53c410fafe54a1b0c07f2bfbebcacf5d Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sat, 3 Jun 2023 23:42:33 +0200 +Subject: [PATCH 4010/4018] sunxi: add support for Rongpin RP-T113 board + +Signed-off-by: Zoltan HERPAI +--- + arch/arm/dts/Makefile | 3 +- + arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts | 99 ++++++++++++++++++++ + configs/rongpin_rp_t113_defconfig | 18 ++++ + 3 files changed, 119 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts + create mode 100644 configs/rongpin_rp_t113_defconfig + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -654,7 +654,8 @@ dtb-$(CONFIG_MACH_SUN8I_R528) += \ + sun8i-t113s-mangopi-mq-r-t113.dtb \ + sun8i-t113s-mangopi-mqdual-t113.dtb \ + sun8i-t113s-myir-myd-yt113x-emmc.dtb \ +- sun8i-t113s-myir-myd-yt113x-spi.dtb ++ sun8i-t113s-myir-myd-yt113x-spi.dtb \ ++ sun8i-t113s-rongpin-rp-t113.dtb + dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-bananapi-m2-plus.dtb \ + sun50i-h5-emlid-neutis-n5-devboard.dtb \ +--- /dev/null ++++ b/arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts +@@ -0,0 +1,99 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2022 Arm Ltd. ++ ++#include ++#include ++ ++/dts-v1/; ++ ++#include "sun8i-t113s.dtsi" ++ ++/ { ++ model = "Rongpin RP-T113"; ++ compatible = "rongpin,rp-t113", "allwinner,sun8i-t113s"; ++ ++ aliases { ++ serial3 = &uart3; ++ }; ++ ++ chosen { ++ stdout-path = "serial3:115200n8"; ++ }; ++ ++ /* board wide 5V supply directly from the USB-C socket */ ++ reg_vcc5v: regulator-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ /* SY8008 DC/DC regulator on the board */ ++ reg_3v3: regulator-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ ++ reg_vcc_core: regulator-core { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-core"; ++ regulator-min-microvolt = <880000>; ++ regulator-max-microvolt = <880000>; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ /* XC6206 LDO on the board */ ++ reg_avdd2v8: regulator-avdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "avdd2v8"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ vin-supply = <®_3v3>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&cpu1 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&pio { ++ vcc-pb-supply = <®_3v3>; ++ vcc-pd-supply = <®_3v3>; ++ vcc-pe-supply = <®_avdd2v8>; ++ vcc-pf-supply = <®_3v3>; ++ vcc-pg-supply = <®_3v3>; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pe_pins>; ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-0 = <&mmc0_pins>; ++ pinctrl-names = "default"; ++ vmmc-supply = <®_3v3>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-0 = <&mmc2_pins>; ++ pinctrl-names = "default"; ++ vmmc-supply = <®_3v3>; ++ non-removable; ++ bus-width = <4>; ++ status = "okay"; ++}; +--- /dev/null ++++ b/configs/rongpin_rp_t113_defconfig +@@ -0,0 +1,18 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-rongpin-rp-t113" ++CONFIG_SUNXI_MINIMUM_DRAM_MB=128 ++CONFIG_SPL=y ++CONFIG_MACH_SUN8I_R528=y ++CONFIG_CONS_INDEX=4 ++CONFIG_MMC0_CD_PIN="PF6" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_MONITOR_LEN=786432 ++CONFIG_DRAM_CLK=792 ++CONFIG_DRAM_ZQ=8092667 ++CONFIG_DRAM_SUNXI_ODT_EN=0 ++CONFIG_DRAM_SUNXI_TPR0=0x004a2195 ++CONFIG_DRAM_SUNXI_TPR11=0x340000 ++CONFIG_DRAM_SUNXI_TPR12=0x46 ++CONFIG_DRAM_SUNXI_TPR13=0x34000100 ++CONFIG_UART3_PINS_PE=y diff --git a/package/boot/uboot-sunxi/patches/407-sunxi-add-support-for-emac-on-PG-pins.patch b/package/boot/uboot-sunxi/patches/407-sunxi-add-support-for-emac-on-PG-pins.patch new file mode 100644 index 0000000000..960b2ab4ea --- /dev/null +++ b/package/boot/uboot-sunxi/patches/407-sunxi-add-support-for-emac-on-PG-pins.patch @@ -0,0 +1,29 @@ +From b843c0563d331c591a5dfd18c17c76b4dff12695 Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sat, 29 Jul 2023 11:29:26 +0200 +Subject: [PATCH 4012/4018] sunxi: add support for emac on PG pins + +Some boards use Port G pins for muxing EMAC. + +Signed-off-by: Zoltan HERPAI +--- + arch/riscv/dts/sunxi-d1s-t113.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/riscv/dts/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi +@@ -114,6 +114,14 @@ + }; + + /omit-if-no-ref/ ++ rgmii_pg_pins: rgmii-pg-pins { ++ pins = "PG0", "PG1", "PG2", "PG3", "PG4", ++ "PG5", "PG6", "PG7", "PG8", "PG9", ++ "PG11", "PG12", "PG13", "PG14", "PG15"; ++ function = "emac"; ++ }; ++ ++ /omit-if-no-ref/ + rmii_pe_pins: rmii-pe-pins { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9"; diff --git a/package/boot/uboot-sunxi/patches/408-sunxi-enable-emac-on-Rongpin-RP-T113.patch b/package/boot/uboot-sunxi/patches/408-sunxi-enable-emac-on-Rongpin-RP-T113.patch new file mode 100644 index 0000000000..95c0bbd402 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/408-sunxi-enable-emac-on-Rongpin-RP-T113.patch @@ -0,0 +1,86 @@ +From d771b39a2439f29ce4d6e0031cfc57abf54d0e4e Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sun, 4 Jun 2023 15:40:42 +0200 +Subject: [PATCH 4014/4018] sunxi: enable emac on Rongpin RP-T113 + +The emac is connected to an IC+ IP101 PHY, for which the driver +has been re-added (it was removed in 2014). + +Currently the driver init fails with the below, so further tweaking +will be required. + +CPU: Allwinner R528 (SUN8I) +Model: Rongpin RP-T113 +DRAM: 128 MiB +Core: 36 devices, 15 uclasses, devicetree: separate +MMC: mmc@4020000: 0, mmc@4022000: 1 +Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... +In: serial@2500c00 +Out: serial@2500c00 +Err: serial@2500c00 +Net: eth_sun8i_emac ethernet@4500000: failed to get TX clock +No ethernet found. + +Signed-off-by: Zoltan HERPAI +--- + arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts | 28 ++++++++++++++++++++ + configs/rongpin_rp_t113_defconfig | 3 +++ + 2 files changed, 31 insertions(+) + +--- a/arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts ++++ b/arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts +@@ -55,6 +55,16 @@ + regulator-max-microvolt = <2800000>; + vin-supply = <®_3v3>; + }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ ++ }; + }; + + &cpu0 { +@@ -79,6 +89,17 @@ + status = "okay"; + }; + ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rmii_pe_pins>; ++ ++ phy-supply = <®_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rmii"; ++ ++ status = "okay"; ++}; ++ + &mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; +@@ -97,3 +118,10 @@ + bus-width = <4>; + status = "okay"; + }; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++}; +--- a/configs/rongpin_rp_t113_defconfig ++++ b/configs/rongpin_rp_t113_defconfig +@@ -16,3 +16,6 @@ CONFIG_DRAM_SUNXI_TPR11=0x340000 + CONFIG_DRAM_SUNXI_TPR12=0x46 + CONFIG_DRAM_SUNXI_TPR13=0x34000100 + CONFIG_UART3_PINS_PE=y ++CONFIG_SUN8I_EMAC=y ++CONFIG_PHY_ICPLUS=y ++CONFIG_RMII=y diff --git a/package/boot/uboot-sunxi/patches/409-sunxi-r528-d1-t113-add-SDC2-pinmux-on-PC2-7-pins.patch b/package/boot/uboot-sunxi/patches/409-sunxi-r528-d1-t113-add-SDC2-pinmux-on-PC2-7-pins.patch new file mode 100644 index 0000000000..603865e5cb --- /dev/null +++ b/package/boot/uboot-sunxi/patches/409-sunxi-r528-d1-t113-add-SDC2-pinmux-on-PC2-7-pins.patch @@ -0,0 +1,26 @@ +From e01de46856ec0d86a0e193dae2a9e2e0c6fa28b1 Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sat, 26 Aug 2023 21:09:17 +0200 +Subject: [PATCH 4018/4018] sunxi: r528/d1/t113: add SDC2 pinmux on PC2-7 pins + +Signed-off-by: Zoltan HERPAI +--- + board/sunxi/board.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -419,6 +419,13 @@ static void mmc_pinmux_setup(int sdc) + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); ++#elif defined(CONFIG_MACH_SUN8I_R528) ++ /* SDC2: PC2-PC7 */ ++ for (pin = SUNXI_GPC(2); pin <= SUNXI_GPC(7); pin++) { ++ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); ++ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); ++ sunxi_gpio_set_drv(pin, 2); ++ } + #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) + /* SDC2: PC5-PC6, PC8-PC16 */ + for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { diff --git a/package/boot/uboot-sunxi/patches/410-sunxi-support-console-on-uart4-pd.patch b/package/boot/uboot-sunxi/patches/410-sunxi-support-console-on-uart4-pd.patch new file mode 100644 index 0000000000..f60a380923 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/410-sunxi-support-console-on-uart4-pd.patch @@ -0,0 +1,38 @@ +--- a/arch/arm/mach-sunxi/board.c ++++ b/arch/arm/mach-sunxi/board.c +@@ -191,6 +191,10 @@ static int gpio_init(void) + sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); + sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); + sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); ++#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I_R528) ++ sunxi_gpio_set_cfgpin(SUNXI_GPD(7), 5); ++ sunxi_gpio_set_cfgpin(SUNXI_GPD(8), 5); ++ sunxi_gpio_set_pull(SUNXI_GPD(8), SUNXI_GPIO_PULL_UP); + #elif CONFIG_CONS_INDEX == 6 && defined(CONFIG_MACH_SUN8I_R528) + sunxi_gpio_set_cfgpin(SUNXI_GPE(6), 3); + sunxi_gpio_set_cfgpin(SUNXI_GPE(7), 3); +--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +@@ -619,6 +619,7 @@ static const struct sunxi_pinctrl_functi + #else + { "uart3", 7 }, /* PB6-PB7 */ + #endif ++ { "uart4", 5 }, /* PD7-PD8 */ + { "uart5", 3 }, /* PE6-PE7 */ + }; + +--- a/arch/riscv/dts/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi +@@ -163,6 +163,12 @@ + pins = "PE2", "PE3"; + function = "uart0"; + }; ++ ++ /omit-if-no-ref/ ++ uart4_pd_pins: uart4-pd-pins { ++ pins = "PD7", "PD8"; ++ function = "uart4"; ++ }; + }; + + ccu: clock-controller@2001000 { diff --git a/package/boot/uboot-sunxi/patches/411-sunxi-dts-add-olinuxino-t113.patch b/package/boot/uboot-sunxi/patches/411-sunxi-dts-add-olinuxino-t113.patch new file mode 100644 index 0000000000..ee4717fe88 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/411-sunxi-dts-add-olinuxino-t113.patch @@ -0,0 +1,250 @@ +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -655,6 +655,7 @@ dtb-$(CONFIG_MACH_SUN8I_R528) += \ + sun8i-t113s-mangopi-mqdual-t113.dtb \ + sun8i-t113s-myir-myd-yt113x-emmc.dtb \ + sun8i-t113s-myir-myd-yt113x-spi.dtb \ ++ sun8i-t113s-olinuxino.dtb \ + sun8i-t113s-rongpin-rp-t113.dtb + dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-bananapi-m2-plus.dtb \ +--- /dev/null ++++ b/arch/arm/dts/sun8i-t113s-olinuxino.dts +@@ -0,0 +1,193 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2022 Arm Ltd. ++ ++#include ++#include ++#include ++ ++/dts-v1/; ++ ++#include "sun8i-t113s.dtsi" ++ ++/ { ++ model = "Olimex Olinuxino T113"; ++ compatible = "olimex,olinuxino-t113", "allwinner,sun8i-t113s"; ++ ++ aliases { ++ serial0 = &uart4; ++ ethernet0 = &rtl8723bs; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ /* board wide 5V supply directly from the USB-C socket */ ++ reg_vcc5v: regulator-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ /* SY8008 DC/DC regulator on the board */ ++ reg_3v3: regulator-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ ++ reg_vcc_core: regulator-core { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-core"; ++ regulator-min-microvolt = <880000>; ++ regulator-max-microvolt = <880000>; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ /* XC6206 LDO on the board */ ++ reg_avdd2v8: regulator-avdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "avdd2v8"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ vin-supply = <®_3v3>; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */ ++ }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&pio 3 12 GPIO_ACTIVE_LOW>; /* PD12 - WIFI_PMU_EN */ ++ }; ++ ++ leds { // TBD ++ compatible = "gpio-leds"; ++ ++ led-0 { ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&pio 4 12 GPIO_ACTIVE_LOW>; /* PE12 */ ++ }; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&cpu1 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&dcxo { ++ clock-frequency = <24000000>; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-0 = <&mmc0_pins>; ++ pinctrl-names = "default"; ++ vmmc-supply = <®_3v3>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-0 = <&mmc1_pins>; ++ pinctrl-names = "default"; ++ vmmc-supply = <®_3v3>; ++ non-removable; ++ bus-width = <4>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ status = "okay"; ++ ++ rtl8723bs: wifi@1 { ++ reg = <1>; ++ }; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&pio { ++ vcc-pb-supply = <®_3v3>; ++ vcc-pd-supply = <®_3v3>; ++ vcc-pe-supply = <®_avdd2v8>; ++ vcc-pf-supply = <®_3v3>; ++ vcc-pg-supply = <®_3v3>; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_vcc5v>; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++ status = "okay"; ++}; ++ ++&uart3 { ++ status = "disabled"; ++}; ++ ++&uart4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_pd_pins>; ++ status = "okay"; ++}; ++ ++&wdt { ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-0 = <&rmii_pe_pins>; ++ pinctrl-names = "default"; ++ phy-handle = <&ext_rmii_phy>; ++ phy-mode = "rmii"; ++ phy-supply = <®_gmac_3v3>; ++ status = "okay"; ++}; ++ ++&mdio { ++ ext_rmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++// reset-gpios = <&pio 4 13 GPIO_ACTIVE_LOW>; /* PE13 */ ++ }; ++}; ++ ++&spi0 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ ++ flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ }; ++}; +--- /dev/null ++++ b/configs/olimex_olinuxino_defconfig +@@ -0,0 +1,41 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-olinuxino" ++CONFIG_SUNXI_MINIMUM_DRAM_MB=128 ++CONFIG_SPL=y ++CONFIG_MACH_SUN8I_R528=y ++CONFIG_CONS_INDEX=5 ++CONFIG_MMC0_CD_PIN="PF6" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=-1 ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_MONITOR_LEN=786432 ++CONFIG_DRAM_CLK=792 ++CONFIG_DRAM_ZQ=8092667 ++CONFIG_DRAM_SUNXI_ODT_EN=0 ++CONFIG_DRAM_SUNXI_TPR0=0x004a2195 ++CONFIG_DRAM_SUNXI_TPR11=0x340000 ++CONFIG_DRAM_SUNXI_TPR12=0x46 ++CONFIG_DRAM_SUNXI_TPR13=0x34000100 ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_SUN8I_EMAC=y ++CONFIG_RMII=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_IO_VOLTAGE=y ++CONFIG_SPL_MMC_IO_VOLTAGE=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_SPL_MMC_HS200_SUPPORT=y ++CONFIG_REALTEK_PHY=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SYS_MTDPARTS_RUNTIME=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPL_SPI_FLASH_MTD=y ++CONFIG_SPL_SPI_SUNXI=y ++CONFIG_SPI=y diff --git a/package/boot/uboot-sunxi/uEnv-t113.ttyS3.txt b/package/boot/uboot-sunxi/uEnv-t113.ttyS3.txt new file mode 100644 index 0000000000..2f5fee7e3e --- /dev/null +++ b/package/boot/uboot-sunxi/uEnv-t113.ttyS3.txt @@ -0,0 +1,8 @@ +setenv fdt_high ffffffff +setenv mmc_rootpart 2 +part uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid +setenv loadkernel fatload mmc \$mmc_bootdev \$kernel_addr_r uImage +setenv loaddtb fatload mmc \$mmc_bootdev \$fdt_addr_r dtb +setenv bootargs console=ttyS3,115200 earlyprintk root=PARTUUID=${uuid} rootwait +setenv uenvcmd run loadkernel \&\& run loaddtb \&\& bootm \$kernel_addr_r - \$fdt_addr_r +run uenvcmd diff --git a/package/boot/uboot-sunxi/uEnv-t113.ttyS5.txt b/package/boot/uboot-sunxi/uEnv-t113.ttyS5.txt new file mode 100644 index 0000000000..353429bd09 --- /dev/null +++ b/package/boot/uboot-sunxi/uEnv-t113.ttyS5.txt @@ -0,0 +1,8 @@ +setenv fdt_high ffffffff +setenv mmc_rootpart 2 +part uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid +setenv loadkernel fatload mmc \$mmc_bootdev \$kernel_addr_r uImage +setenv loaddtb fatload mmc \$mmc_bootdev \$fdt_addr_r dtb +setenv bootargs console=ttyS5,115200 earlyprintk root=PARTUUID=${uuid} rootwait +setenv uenvcmd run loadkernel \&\& run loaddtb \&\& bootm \$kernel_addr_r - \$fdt_addr_r +run uenvcmd diff --git a/target/linux/sunxi/base-files/etc/inittab b/target/linux/sunxi/base-files/etc/inittab index be81ab3e23..4ab795b1d4 100644 --- a/target/linux/sunxi/base-files/etc/inittab +++ b/target/linux/sunxi/base-files/etc/inittab @@ -3,3 +3,5 @@ tts/0::askfirst:/usr/libexec/login.sh ttyS0::askfirst:/usr/libexec/login.sh tty1::askfirst:/usr/libexec/login.sh +ttyS3::askfirst:/usr/libexec/login.sh +ttyS5::askfirst:/usr/libexec/login.sh diff --git a/target/linux/sunxi/config-6.18 b/target/linux/sunxi/config-6.18 index 9ef0557655..c5d8692aab 100644 --- a/target/linux/sunxi/config-6.18 +++ b/target/linux/sunxi/config-6.18 @@ -313,6 +313,7 @@ CONFIG_MMC_BLOCK=y CONFIG_MMC_SUNXI=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_SPI_NAND=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPLIT_FIT_FW=y CONFIG_MUTEX_SPIN_ON_OWNER=y @@ -475,6 +476,7 @@ CONFIG_SPI_SUN6I=y CONFIG_SRCU=y CONFIG_STMMAC_ETH=y CONFIG_STMMAC_PLATFORM=y +# CONFIG_SND_SUN20I_D1_CODEC_ANALOG is not set # CONFIG_SUN20I_GPADC is not set # CONFIG_SUN20I_PPU is not set CONFIG_SUN4I_A10_CCU=y diff --git a/target/linux/sunxi/cortexa7/config-6.18 b/target/linux/sunxi/cortexa7/config-6.18 index 789a4e6f1b..2d64e3bbfa 100644 --- a/target/linux/sunxi/cortexa7/config-6.18 +++ b/target/linux/sunxi/cortexa7/config-6.18 @@ -12,6 +12,7 @@ CONFIG_GRO_CELLS=y # CONFIG_MACH_SUN5I is not set CONFIG_MDIO_BUS_MUX=y CONFIG_MICREL_PHY=y +CONFIG_MOTORCOMM_PHY=y CONFIG_MUSB_PIO_ONLY=y CONFIG_NET_DEVLINK=y CONFIG_NET_DSA=y @@ -22,6 +23,7 @@ CONFIG_NET_DSA_TAG_BRCM_LEGACY_FCS=y CONFIG_NET_DSA_TAG_BRCM_PREPEND=y CONFIG_NOP_USB_XCEIV=y CONFIG_PINCTRL_AXP209=y +CONFIG_PINCTRL_SUN20I_D1=y CONFIG_PINCTRL_SUN4I_A10=y CONFIG_PINCTRL_SUN6I_A31=y CONFIG_PINCTRL_SUN6I_A31_R=y @@ -38,6 +40,7 @@ CONFIG_PINCTRL_SUN9I_A80_R=y CONFIG_RTC_DRV_SUN6I=y CONFIG_SUN20I_D1_CCU=y CONFIG_SUN20I_D1_R_CCU=y +CONFIG_SUN6I_RTC_CCU=y CONFIG_USB_MUSB_DUAL_ROLE=y CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SUNXI=y diff --git a/target/linux/sunxi/image/cortexa7.mk b/target/linux/sunxi/image/cortexa7.mk index 50d9a29f4e..2baa2a8397 100644 --- a/target/linux/sunxi/image/cortexa7.mk +++ b/target/linux/sunxi/image/cortexa7.mk @@ -323,3 +323,51 @@ define Device/xunlong_orangepi-2 SOC := sun8i-h3 endef TARGET_DEVICES += xunlong_orangepi-2 + +define Device/widora_mangopi-mqdual-t113 + $(call Device/FitImageGzip) + DEVICE_VENDOR := Widora + DEVICE_MODEL := MangoPi MQDual T113 + DEVICE_PACKAGES:=kmod-rtc-sunxi + SOC := sun8i-t113s +endef +TARGET_DEVICES += widora_mangopi-mqdual-t113 + +define Device/myir_myd-yt113x-emmc + $(call Device/FitImageGzip) + DEVICE_VENDOR := MYIR + DEVICE_MODEL := MYD-YT113X (eMMC) + DEVICE_PACKAGES := kmod-rtc-sunxi kmod-eeprom-at24 kmod-gpio-pca953x kmod-rtc-rx8025 + SOC := sun8i-t113s + IMAGE/sdcard.img.gz := sunxi-sdcard | append-metadata | gzip +endef +TARGET_DEVICES += myir_myd-yt113x-emmc + +define Device/myir_myd-yt113x-spi + $(call Device/FitImageGzip) + DEVICE_VENDOR := MYIR + DEVICE_MODEL := MYD-YT113X (SPI) + DEVICE_PACKAGES := kmod-rtc-sunxi kmod-eeprom-at24 kmod-gpio-pca953x kmod-rtc-rx8025 + SOC := sun8i-t113s +endef +TARGET_DEVICES += myir_myd-yt113x-spi + +define Device/olimex_olinuxino + $(call Device/FitImageGzip) + DEVICE_VENDOR := Olimex + DEVICE_MODEL := Olinuxino T113 + DEVICE_PACKAGES:=kmod-rtc-sunxi + SOC := sun8i-t113s + IMAGE/sdcard.img.gz := sunxi-sdcard | append-metadata | gzip +endef +TARGET_DEVICES += olimex_olinuxino + +define Device/rongpin_rp-t113 + $(call Device/FitImageGzip) + DEVICE_VENDOR := Rongpin + DEVICE_MODEL := RP-T113 + DEVICE_PACKAGES:=kmod-rtc-sunxi kmod-rtl8xxxu rtl8723bu-firmware wpad-basic-mbedtls + SOC := sun8i-t113s + IMAGE/sdcard.img.gz := sunxi-sdcard | append-metadata | gzip +endef +TARGET_DEVICES += rongpin_rp-t113 diff --git a/target/linux/sunxi/patches-6.18/540-riscv-dts-allwinner-d1-Add-QSPI-pins-node-for-pinmux.patch b/target/linux/sunxi/patches-6.18/540-riscv-dts-allwinner-d1-Add-QSPI-pins-node-for-pinmux.patch new file mode 100644 index 0000000000..984471ed23 --- /dev/null +++ b/target/linux/sunxi/patches-6.18/540-riscv-dts-allwinner-d1-Add-QSPI-pins-node-for-pinmux.patch @@ -0,0 +1,30 @@ +From 76a51a14ba03f6d0277af06701705501d5e406f1 Mon Sep 17 00:00:00 2001 +From: Maksim Kiselev +Date: Sat, 24 Jun 2023 16:16:24 +0300 +Subject: [PATCH 14/25] riscv: dts: allwinner: d1: Add QSPI pins node for + pinmux PC port + +Add pinmux node that describes pins on PC port which required for +QSPI mode. + +Signed-off-by: Maksim Kiselev +--- + arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +@@ -191,6 +191,13 @@ + pins = "PB6", "PB7"; + function = "uart3"; + }; ++ ++ /omit-if-no-ref/ ++ qspi0_pc_pins: qspi0-pc-pins { ++ pins = "PC2", "PC3", "PC4", "PC5", "PC6", ++ "PC7"; ++ function = "spi0"; ++ }; + }; + + ccu: clock-controller@2001000 { diff --git a/target/linux/sunxi/patches-6.18/541-ARM-dts-riscv-add-uart0_pins-on-Port-E-pins.patch b/target/linux/sunxi/patches-6.18/541-ARM-dts-riscv-add-uart0_pins-on-Port-E-pins.patch new file mode 100644 index 0000000000..c93cee4c29 --- /dev/null +++ b/target/linux/sunxi/patches-6.18/541-ARM-dts-riscv-add-uart0_pins-on-Port-E-pins.patch @@ -0,0 +1,25 @@ +From 0208e409b80562ad8e9d2de31f123cdeed37d88e Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sun, 4 Jun 2023 16:46:05 +0200 +Subject: [PATCH 15/25] ARM: dts: riscv: add uart0_pins on Port E pins + +Signed-off-by: Zoltan HERPAI +--- + arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +@@ -198,6 +198,12 @@ + "PC7"; + function = "spi0"; + }; ++ ++ /omit-if-no-ref/ ++ uart0_pins: uart0-pins { ++ pins = "PE2", "PE3"; ++ function = "uart0"; ++ }; + }; + + ccu: clock-controller@2001000 { diff --git a/target/linux/sunxi/patches-6.18/542-ARM-dts-sunxi-add-support-for-MangoPI-MQDual-T113-va.patch b/target/linux/sunxi/patches-6.18/542-ARM-dts-sunxi-add-support-for-MangoPI-MQDual-T113-va.patch new file mode 100644 index 0000000000..ed479f4281 --- /dev/null +++ b/target/linux/sunxi/patches-6.18/542-ARM-dts-sunxi-add-support-for-MangoPI-MQDual-T113-va.patch @@ -0,0 +1,80 @@ +From 7d38e964a627c99d238978fd1e9b8ec946dc7541 Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sun, 4 Jun 2023 16:46:43 +0200 +Subject: [PATCH 16/25] ARM: dts: sunxi: add support for MangoPI MQDual T113 + variant + +Signed-off-by: Zoltan HERPAI +--- + arch/arm/boot/dts/Makefile | 1 + + .../dts/sun8i-t113s-mangopi-mqdual-t113.dts | 54 +++++++++++++++++++ + 2 files changed, 55 insertions(+) + create mode 100644 arch/arm/boot/dts/sun8i-t113s-mangopi-mqdual-t113.dts + +--- a/arch/arm/boot/dts/allwinner/Makefile ++++ b/arch/arm/boot/dts/allwinner/Makefile +@@ -262,6 +262,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-s3-lichee-zero-plus.dtb \ + sun8i-s3-pinecube.dtb \ + sun8i-t113s-mangopi-mq-r-t113.dtb \ ++ sun8i-t113s-mangopi-mqdual-t113.dtb \ + sun8i-t113s-netcube-nagami-basic-carrier.dtb \ + sun8i-t113s-netcube-nagami-keypad-carrier.dtb \ + sun8i-t3-cqa3t-bv3.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mqdual-t113.dts +@@ -0,0 +1,54 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2022 Arm Ltd. ++ ++#include ++ ++/dts-v1/; ++ ++#include "sun8i-t113s.dtsi" ++#include "sunxi-d1s-t113-mangopi-mq-r.dtsi" ++ ++/ { ++ model = "MangoPi MQDual T113"; ++ compatible = "widora,mangopi-mqdual-t113", "allwinner,sun8i-t113s"; ++ ++ aliases { ++ serial0 = &uart0; ++ ethernet0 = &rtl8189ftv; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&cpu1 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&mmc1 { ++ rtl8189ftv: wifi@1 { ++ reg = <1>; ++ interrupt-parent = <&pio>; ++ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++ status = "okay"; ++}; ++ ++&uart3 { ++ status = "disabled"; ++}; ++ ++&wdt { ++ status = "okay"; ++}; diff --git a/target/linux/sunxi/patches-6.18/543-ARM-dts-add-support-for-MYIR-MYD-YT113X-boards.patch b/target/linux/sunxi/patches-6.18/543-ARM-dts-add-support-for-MYIR-MYD-YT113X-boards.patch new file mode 100644 index 0000000000..2405544bf1 --- /dev/null +++ b/target/linux/sunxi/patches-6.18/543-ARM-dts-add-support-for-MYIR-MYD-YT113X-boards.patch @@ -0,0 +1,298 @@ +--- a/arch/arm/boot/dts/allwinner/Makefile ++++ b/arch/arm/boot/dts/allwinner/Makefile +@@ -263,6 +263,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-s3-pinecube.dtb \ + sun8i-t113s-mangopi-mq-r-t113.dtb \ + sun8i-t113s-mangopi-mqdual-t113.dtb \ ++ sun8i-t113s-myd-yt113x-emmc.dtb \ ++ sun8i-t113s-myd-yt113x-spi.dtb \ + sun8i-t113s-netcube-nagami-basic-carrier.dtb \ + sun8i-t113s-netcube-nagami-keypad-carrier.dtb \ + sun8i-t3-cqa3t-bv3.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-myd-yt113x.dtsi +@@ -0,0 +1,221 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2022 Arm Ltd. ++ ++#include ++#include ++ ++/dts-v1/; ++ ++#include "sun8i-t113s.dtsi" ++ ++/ { ++ compatible = "myir,myd-yt113x", "myir,myc-yt113x", "allwinner,sun8i-t113s"; ++ ++ aliases { ++ serial5 = &uart5; ++ ++ led-boot = &led_blue; ++ led-failsafe = &led_blue; ++ led-running = &led_blue; ++ led-upgrade = &led_blue; ++ }; ++ ++ chosen { ++ stdout-path = "serial5:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_blue: blue { ++ label = "blue"; ++ gpios = <&pio 4 2 GPIO_ACTIVE_LOW>; /* PD2 */ ++ }; ++ ++ green { ++ label = "green"; ++ gpios = <&pcf9555 6 GPIO_ACTIVE_LOW>; ++ default-state = "on"; ++ }; ++ }; ++ ++ /* board wide 5V supply directly from the USB-C socket */ ++ reg_vcc5v: regulator-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ /* SY8008 DC/DC regulator on the board */ ++ reg_3v3: regulator-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ ++ reg_vcc_core: regulator-core { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-core"; ++ regulator-min-microvolt = <880000>; ++ regulator-max-microvolt = <880000>; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ /* XC6206 LDO on the board */ ++ reg_avdd2v8: regulator-avdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "avdd2v8"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ vin-supply = <®_3v3>; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */ ++ }; ++}; ++ ++ ++&cpu0 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&cpu1 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&dcxo { ++ clock-frequency = <24000000>; ++}; ++ ++&pio { ++ vcc-pb-supply = <®_3v3>; ++ vcc-pd-supply = <®_3v3>; ++ vcc-pe-supply = <®_avdd2v8>; ++ vcc-pf-supply = <®_3v3>; ++ vcc-pg-supply = <®_3v3>; ++ ++ /omit-if-no-ref/ ++ uart5_pins: uart5-pins { ++ pins = "PE6", "PE7"; ++ function = "uart5"; ++ }; ++ ++ rgmii_pg_pins: rgmii-pg-pins { ++ pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", ++ "PG6", "PG7", "PG8", "PG9", "PG10", ++ "PG12", "PG14", "PG15"; ++ function = "emac"; ++ }; ++ ++ i2c1_pb_pins: i2c1-pb-pins { ++ pins = "PB4", "PB5"; ++ function = "i2c1"; ++ }; ++ ++ i2c3_pb_pins: i2c3-pb-pins { ++ pins = "PB6", "PB7"; ++ function = "i2c3"; ++ }; ++}; ++ ++&uart5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart5_pins>; ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-0 = <&mmc0_pins>; ++ pinctrl-names = "default"; ++ vmmc-supply = <®_3v3>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_vcc5v>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ pinctrl-0 = <&i2c1_pb_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++ ++ rtc@32 { ++ compatible = "epson,rx8025"; ++ reg = <0x32>; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-0 = <&i2c3_pb_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++ ++ eeprom@50 { ++ compatible = "atmel,24c32"; ++ reg = <0x50>; ++ }; ++ ++ pcf9555: pcf9555@20 { ++ #gpio-cells = <2>; ++ compatible = "nxp,pca9555"; ++ reg = <0x20>; ++ }; ++}; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ reset-gpios = <&pio 4 11 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pg_pins>; ++ ++ phy-supply = <®_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii"; ++ ++ status = "okay"; ++}; ++ ++&wdt { ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-myd-yt113x-emmc.dts +@@ -0,0 +1,27 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2022 Arm Ltd. ++ ++#include ++#include ++ ++/dts-v1/; ++ ++#include "sun8i-t113s-myd-yt113x.dtsi" ++ ++/ { ++ model = "MYIR MYD-YT113X (eMMC)"; ++}; ++ ++&mmc2_pins { ++ bias-pull-up; ++ drive-strength = <40>; ++}; ++ ++&mmc2 { ++ pinctrl-0 = <&mmc2_pins>; ++ pinctrl-names = "default"; ++ vmmc-supply = <®_3v3>; ++ non-removable; ++ bus-width = <4>; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-myd-yt113x-spi.dts +@@ -0,0 +1,30 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2022 Arm Ltd. ++ ++#include ++#include ++ ++/dts-v1/; ++ ++#include "sun8i-t113s-myd-yt113x.dtsi" ++ ++/ { ++ model = "MYIR MYD-YT113X (SPI)"; ++}; ++ ++&spi0 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&qspi0_pc_pins>; ++ ++ flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <40000000>; ++ }; ++ ++}; diff --git a/target/linux/sunxi/patches-6.18/544-ARM-dts-add-support-for-Rongpin-RP-T113-board.patch b/target/linux/sunxi/patches-6.18/544-ARM-dts-add-support-for-Rongpin-RP-T113-board.patch new file mode 100644 index 0000000000..631108f028 --- /dev/null +++ b/target/linux/sunxi/patches-6.18/544-ARM-dts-add-support-for-Rongpin-RP-T113-board.patch @@ -0,0 +1,238 @@ +From b96bdf955ab4131023a465dba2035940ee848fb4 Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Thu, 31 Aug 2023 13:35:06 +0200 +Subject: [PATCH 18/25] ARM: dts: add support for Rongpin RP-T113 board + +Signed-off-by: Zoltan HERPAI +--- + arch/arm/boot/dts/allwinner/Makefile | 1 + + arch/arm/boot/dts/allwinner/sun8i-t113s-rp-t113.dts | 184 ++++++++++++++++++++++ + 2 files changed, 185 insertions(+) + create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-rp-t113.dts + +--- a/arch/arm/boot/dts/allwinner/Makefile ++++ b/arch/arm/boot/dts/allwinner/Makefile +@@ -265,6 +265,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-t113s-mangopi-mqdual-t113.dtb \ + sun8i-t113s-myd-yt113x-emmc.dtb \ + sun8i-t113s-myd-yt113x-spi.dtb \ ++ sun8i-t113s-rp-t113.dtb \ + sun8i-t113s-netcube-nagami-basic-carrier.dtb \ + sun8i-t113s-netcube-nagami-keypad-carrier.dtb \ + sun8i-t3-cqa3t-bv3.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-rp-t113.dts +@@ -0,0 +1,213 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2022 Arm Ltd. ++ ++#include ++#include ++ ++/dts-v1/; ++ ++#include "sun8i-t113s.dtsi" ++ ++/ { ++ model = "Rongpin RP-T113"; ++ compatible = "rongpin,rp-t113", "allwinner,sun8i-t113s"; ++ ++ aliases { ++ serial3 = &uart3; ++ ++ led-boot = &led_green; ++ led-failsafe = &led_green; ++ led-running = &led_green; ++ led-upgrade = &led_green; ++ }; ++ ++ chosen { ++ stdout-path = "serial3:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_green: green { ++ label = "green"; ++ gpios = <&pio 3 16 GPIO_ACTIVE_HIGH>; /* PD16 */ ++ }; ++ }; ++ ++ ++ /* board wide 5V supply directly from the USB-C socket */ ++ reg_vcc5v: regulator-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ /* SY8008 DC/DC regulator on the board */ ++ reg_3v3: regulator-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ ++ reg_vcc_core: regulator-core { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-core"; ++ regulator-min-microvolt = <880000>; ++ regulator-max-microvolt = <880000>; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ /* XC6206 LDO on the board */ ++ reg_avdd2v8: regulator-avdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "avdd2v8"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ vin-supply = <®_3v3>; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PG11 */ ++ }; ++ ++ /* We need to pull up some GPIOs to enable the onboard wifi module ++ and the 4G mPCIe slot, mark these as always-on. */ ++ reg_vcc_usbwifi: vcc-usbwifi { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-usbwifi"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&pio 3 17 GPIO_ACTIVE_HIGH>; /* PD17 */ ++ regulator-always-on; ++ }; ++ ++ reg_vcc_4g: vcc-4g { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-4g"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&pio 4 1 GPIO_ACTIVE_HIGH>; /* PE1 */ ++ regulator-always-on; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&cpu1 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&dcxo { ++ clock-frequency = <24000000>; ++}; ++ ++&pio { ++ vcc-pb-supply = <®_3v3>; ++ vcc-pd-supply = <®_3v3>; ++ vcc-pe-supply = <®_avdd2v8>; ++ vcc-pf-supply = <®_3v3>; ++ vcc-pg-supply = <®_3v3>; ++ ++ /omit-if-no-ref/ ++ uart3_pe_pins: uart3-pe-pins { ++ pins = "PE8", "PE9"; ++ function = "uart3"; ++ }; ++ ++ /* move this over to riscv common dtsi */ ++ /omit-if-no-ref/ ++ rmii_pg_pins: rmii-pg-pins { ++ pins = "PG0", "PG1", "PG2", "PG3", "PG4", ++ "PG5", "PG12", "PG13", "PG14", "PG15"; ++ function = "emac"; ++ }; ++ ++ emac_25m_pins: emac-25m-pins { ++ pins = "PE10"; ++ function = "emac"; ++ }; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pe_pins>; ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-0 = <&mmc0_pins>; ++ pinctrl-names = "default"; ++ vmmc-supply = <®_3v3>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-0 = <&mmc2_pins>; ++ pinctrl-names = "default"; ++ vmmc-supply = <®_3v3>; ++ non-removable; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mdio { ++ clocks = <&ccu CLK_EMAC_25M>; ++ clock-names = "emac_25m"; ++ ++ ext_rmii_phy: ethernet-phy@1 { ++ reg = <1>; ++ reset-gpios = <&pio 4 11 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rmii_pg_pins>, <&emac_25m_pins>; ++ ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rmii_phy>; ++ phy-mode = "rmii"; ++ ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_vcc5v>; ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&wdt { ++ status = "okay"; ++}; ++ diff --git a/target/linux/sunxi/patches-6.18/545-riscv-dts-allwinner-d1-Add-thermal-sensor.patch b/target/linux/sunxi/patches-6.18/545-riscv-dts-allwinner-d1-Add-thermal-sensor.patch new file mode 100644 index 0000000000..1898087d11 --- /dev/null +++ b/target/linux/sunxi/patches-6.18/545-riscv-dts-allwinner-d1-Add-thermal-sensor.patch @@ -0,0 +1,46 @@ +From 2a4083dd87bb25878ab72ef0c99167be750a09b7 Mon Sep 17 00:00:00 2001 +From: Maxim Kiselev +Date: Wed, 14 Jun 2023 15:55:21 +0300 +Subject: [PATCH 23/25] riscv: dts: allwinner: d1: Add thermal sensor + +This patch adds a thermal sensor controller node for the D1/T113s. +Also it adds a THS calibration data cell to efuse node. + +Signed-off-by: Maxim Kiselev +--- + .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +@@ -227,6 +227,19 @@ + #io-channel-cells = <1>; + }; + ++ ths: thermal-sensor@2009400 { ++ compatible = "allwinner,sun20i-d1-ths"; ++ reg = <0x02009400 0x400>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_THS>; ++ clock-names = "bus"; ++ resets = <&ccu RST_BUS_THS>; ++ nvmem-cells = <&ths_calibration>; ++ nvmem-cell-names = "calibration"; ++ status = "disabled"; ++ #thermal-sensor-cells = <0>; ++ }; ++ + dmic: dmic@2031000 { + compatible = "allwinner,sun20i-d1-dmic", + "allwinner,sun50i-h6-dmic"; +@@ -487,6 +500,10 @@ + reg = <0x3006000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ ths_calibration: thermal-sensor-calibration@14 { ++ reg = <0x14 0x4>; ++ }; + }; + + crypto: crypto@3040000 { diff --git a/target/linux/sunxi/patches-6.18/550-ARM-dts-sunxi-add-support-for-LctechPi-PC-T113.patch b/target/linux/sunxi/patches-6.18/550-ARM-dts-sunxi-add-support-for-LctechPi-PC-T113.patch new file mode 100644 index 0000000000..432d302d56 --- /dev/null +++ b/target/linux/sunxi/patches-6.18/550-ARM-dts-sunxi-add-support-for-LctechPi-PC-T113.patch @@ -0,0 +1,98 @@ +From dbece70e4d86e39e4e384f553eae13d50819dd4b Mon Sep 17 00:00:00 2001 +From: Maksim Kiselev +Date: Fri, 26 Jan 2024 15:36:21 +0300 +Subject: [PATCH] ARM: dts: sunxi: add support for LctechPi PC-T113 + +Signed-off-by: Maksim Kiselev +--- + .../sun8i-t113s-lctechpi-pc-t113.dts | 74 +++++++++++++++++++ + 1 file changed, 74 insertions(+) + create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-lctechpi-pc-t113.dts + +--- /dev/null ++++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-lctechpi-pc-t113.dts +@@ -0,0 +1,74 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2024 Maksim Kiselev . ++ ++/dts-v1/; ++ ++#include "sun8i-t113s-mangopi-mq-r-t113.dts" ++ ++/ { ++ model = "LctechPi PC-T113"; ++ compatible = "lctechpi,pc-t113", "allwinner,sun8i-t113s"; ++ ++ aliases { ++ serial1 = &uart1; ++ }; ++ ++ chosen { ++ stdout-path = "serial1:115200n8"; ++ }; ++ ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 0>; ++ ++ trips { ++ cpu_hot_trip: cpu-hot { ++ temperature = <80000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_very_hot_trip: cpu-very-hot { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pg6_pins>; ++ status = "okay"; ++}; ++ ++&wdt { ++ status = "okay"; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ status = "okay"; ++ ++ flash@0 { /* W25Q128JVEI */ ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <100000000>; /* Up to 133 MHz */ ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <1>; ++ }; ++ ++}; ++ ++&ths { ++ status = "okay"; ++}; ++ ++&can1 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/allwinner/Makefile ++++ b/arch/arm/boot/dts/allwinner/Makefile +@@ -266,6 +266,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-t113s-myd-yt113x-emmc.dtb \ + sun8i-t113s-myd-yt113x-spi.dtb \ + sun8i-t113s-rp-t113.dtb \ ++ sun8i-t113s-lctechpi-pc-t113.dtb \ + sun8i-t113s-netcube-nagami-basic-carrier.dtb \ + sun8i-t113s-netcube-nagami-keypad-carrier.dtb \ + sun8i-t3-cqa3t-bv3.dtb \ diff --git a/target/linux/sunxi/patches-6.18/551-dts-support-uart4-on-pd.patch b/target/linux/sunxi/patches-6.18/551-dts-support-uart4-on-pd.patch new file mode 100644 index 0000000000..7f5d500c4f --- /dev/null +++ b/target/linux/sunxi/patches-6.18/551-dts-support-uart4-on-pd.patch @@ -0,0 +1,15 @@ +--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +@@ -204,6 +204,12 @@ + pins = "PE2", "PE3"; + function = "uart0"; + }; ++ ++ /omit-if-no-ref/ ++ uart4_pd_pins: uart4-pd-pins { ++ pins = "PD7", "PD8"; ++ function = "uart4"; ++ }; + }; + + ccu: clock-controller@2001000 { diff --git a/target/linux/sunxi/patches-6.18/552-dts-add-olimex-t113-olinuxino.patch b/target/linux/sunxi/patches-6.18/552-dts-add-olimex-t113-olinuxino.patch new file mode 100644 index 0000000000..a689dd1608 --- /dev/null +++ b/target/linux/sunxi/patches-6.18/552-dts-add-olimex-t113-olinuxino.patch @@ -0,0 +1,218 @@ +--- a/arch/arm/boot/dts/allwinner/Makefile ++++ b/arch/arm/boot/dts/allwinner/Makefile +@@ -265,6 +265,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-t113s-mangopi-mqdual-t113.dtb \ + sun8i-t113s-myd-yt113x-emmc.dtb \ + sun8i-t113s-myd-yt113x-spi.dtb \ ++ sun8i-t113s-olinuxino.dtb \ + sun8i-t113s-rp-t113.dtb \ + sun8i-t113s-lctechpi-pc-t113.dtb \ + sun8i-t113s-netcube-nagami-basic-carrier.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-olinuxino.dts +@@ -0,0 +1,205 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2022 Arm Ltd. ++ ++#include ++#include ++#include ++ ++/dts-v1/; ++ ++#include "sun8i-t113s.dtsi" ++ ++/ { ++ model = "Olimex Olinuxino T113"; ++ compatible = "olimex,olinuxino-t113", "allwinner,sun8i-t113s"; ++ ++ aliases { ++ serial0 = &uart4; ++ serial1 = &uart1; ++ mmc0 = &mmc0; ++ mmc1 = &mmc1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ /* board wide 5V supply directly from the USB-C socket */ ++ reg_vcc5v: regulator-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ /* SY8008 DC/DC regulator on the board */ ++ reg_3v3: regulator-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ ++ reg_vcc_core: regulator-core { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-core"; ++ regulator-min-microvolt = <880000>; ++ regulator-max-microvolt = <880000>; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ /* XC6206 LDO on the board */ ++ reg_avdd2v8: regulator-avdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "avdd2v8"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ vin-supply = <®_3v3>; ++ }; ++ ++ reg_usb1_vbus: usb1-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb1-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ enable-active-high; ++ gpio = <&pio 3 17 GPIO_ACTIVE_HIGH>; /* PD17 */ ++ status = "disabled"; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 - WIFI_PMU_EN */ ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_green: led-0 { ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&pio 4 12 GPIO_ACTIVE_LOW>; /* PE12 */ ++ }; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&cpu1 { ++ cpu-supply = <®_vcc_core>; ++}; ++ ++&dcxo { ++ clock-frequency = <24000000>; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-0 = <&mmc0_pins>; ++ pinctrl-names = "default"; ++ vmmc-supply = <®_3v3>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-0 = <&mmc1_pins>; ++ pinctrl-names = "default"; ++ vmmc-supply = <®_3v3>; ++ non-removable; ++ bus-width = <4>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&pio { ++ vcc-pb-supply = <®_3v3>; ++ vcc-pd-supply = <®_3v3>; ++ vcc-pe-supply = <®_avdd2v8>; ++ vcc-pf-supply = <®_3v3>; ++ vcc-pg-supply = <®_3v3>; ++}; ++ ++®_usb1_vbus { ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_usb1_vbus>; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++ status = "disabled"; ++}; ++ ++&uart3 { ++ status = "disabled"; ++}; ++ ++&uart4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_pd_pins>; ++ status = "okay"; ++}; ++ ++&wdt { ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-0 = <&rmii_pe_pins>; ++ pinctrl-names = "default"; ++ phy-handle = <&ext_rmii_phy>; ++ phy-mode = "rmii"; ++ phy-supply = <®_3v3>; ++ status = "okay"; ++}; ++ ++&mdio { ++ ext_rmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ reset-gpios = <&pio 4 13 GPIO_ACTIVE_LOW>; /* PE13 */ ++ }; ++}; ++ ++&spi0 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&qspi0_pc_pins>; ++ ++ flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <40000000>; ++ }; ++}; diff --git a/target/linux/sunxi/patches-6.18/553-dts-add-aliases-to-olinuxino-t113.patch b/target/linux/sunxi/patches-6.18/553-dts-add-aliases-to-olinuxino-t113.patch new file mode 100644 index 0000000000..45d3764132 --- /dev/null +++ b/target/linux/sunxi/patches-6.18/553-dts-add-aliases-to-olinuxino-t113.patch @@ -0,0 +1,14 @@ +--- a/arch/arm/boot/dts/allwinner/sun8i-t113s-olinuxino.dts ++++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-olinuxino.dts +@@ -18,6 +18,11 @@ + serial1 = &uart1; + mmc0 = &mmc0; + mmc1 = &mmc1; ++ ++ led-boot = &led_green; ++ led-failsafe = &led_green; ++ led-running = &led_green; ++ led-upgrade = &led_green; + }; + + chosen { diff --git a/target/linux/sunxi/patches-6.18/554-dts-allwinner-d1-add-led-controller-node.patch b/target/linux/sunxi/patches-6.18/554-dts-allwinner-d1-add-led-controller-node.patch new file mode 100644 index 0000000000..49e96f1a8f --- /dev/null +++ b/target/linux/sunxi/patches-6.18/554-dts-allwinner-d1-add-led-controller-node.patch @@ -0,0 +1,60 @@ +From: Samuel Holland +Subject: riscv: dts: allwinner: d1: Add LED controller node +Date: Sun, 29 Oct 2023 16:26:58 -0500 + +Allwinner D1 contains an LED controller. Add its devicetree node, as +well as the pinmux used by the reference board design. + +Acked-by: Guo Ren +Reviewed-by: Jernej Skrabec +Tested-by: Trevor Woerner +Signed-off-by: Samuel Holland +--- +(no changes since v5) + +Changes in v5: + - New patch for v5 + + arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 6 ++++++ + arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 15 +++++++++++++++ + 2 files changed, 21 insertions(+) + +--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi +@@ -59,6 +59,12 @@ + }; + + /omit-if-no-ref/ ++ ledc_pc0_pin: ledc-pc0-pin { ++ pins = "PC0"; ++ function = "ledc"; ++ }; ++ ++ /omit-if-no-ref/ + uart0_pb8_pins: uart0-pb8-pins { + pins = "PB8", "PB9"; + function = "uart0"; +--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +@@ -223,6 +223,21 @@ + #reset-cells = <1>; + }; + ++ ledc: led-controller@2008000 { ++ compatible = "allwinner,sun20i-d1-ledc", ++ "allwinner,sun50i-a100-ledc"; ++ reg = <0x2008000 0x400>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>; ++ clock-names = "bus", "mod"; ++ resets = <&ccu RST_BUS_LEDC>; ++ dmas = <&dma 42>; ++ dma-names = "tx"; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ + gpadc: adc@2009000 { + compatible = "allwinner,sun20i-d1-gpadc"; + reg = <0x2009000 0x400>; diff --git a/target/linux/sunxi/patches-6.18/555-dts-add-rgb-leds-to-olinuxino.patch b/target/linux/sunxi/patches-6.18/555-dts-add-rgb-leds-to-olinuxino.patch new file mode 100644 index 0000000000..a88d6b030f --- /dev/null +++ b/target/linux/sunxi/patches-6.18/555-dts-add-rgb-leds-to-olinuxino.patch @@ -0,0 +1,43 @@ +From: Zoltan HERPAI +Subject: riscv: dts: allwinner: sunxi: add LED to Olinuxino T113 +Date: Sun, 29 Oct 2023 16:26:59 -0500 + +Add LED controller support for the T113 Olinuxino, connected to PG13. + +Signed-off-by: Zoltan HERPAI + + .../boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts | 12 ++++++++++++ + arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts | 13 +++++++++++++ + 2 files changed, 25 insertions(+) + +--- a/arch/arm/boot/dts/allwinner/sun8i-t113s-olinuxino.dts ++++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-olinuxino.dts +@@ -145,6 +145,11 @@ + vcc-pe-supply = <®_avdd2v8>; + vcc-pf-supply = <®_3v3>; + vcc-pg-supply = <®_3v3>; ++ ++ ledc_pg13_pin: ledc-pg13-pin { ++ pins = "PG13"; ++ function = "ledc"; ++ }; + }; + + ®_usb1_vbus { +@@ -208,3 +213,16 @@ + spi-max-frequency = <40000000>; + }; + }; ++ ++&ledc { ++ pinctrl-0 = <&ledc_pg13_pin>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ multi-led@0 { ++ reg = <0x0>; ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ }; ++}; ++