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sifiveu: refresh config for 6.18

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Refresh config for 6.18.

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
This commit is contained in:
Zoltan HERPAI 2026-04-03 08:47:00 +00:00
parent 203743a01f
commit 71ab1575af
1 changed files with 17 additions and 0 deletions
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17
target/linux/sifiveu/config-6.18
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@ -1,4 +1,5 @@
CONFIG_64BIT=y
# CONFIG_ACLINT_SSWI is not set
# CONFIG_ACPI is not set
# CONFIG_ARCH_CANAAN is not set
CONFIG_ARCH_DEFAULT_CRASH_DUMP=y
@ -99,7 +100,10 @@ CONFIG_DUMMY_CONSOLE=y
CONFIG_DYNAMIC_SIGFRAME=y
CONFIG_EDAC=y
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_ECS is not set
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_MEM_REPAIR is not set
# CONFIG_EDAC_SCRUB is not set
CONFIG_EDAC_SIFIVE=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EFI=y
@ -273,6 +277,7 @@ CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OID_REGISTRY=y
CONFIG_PADATA=y
CONFIG_PAGE_BLOCK_MAX_ORDER=10
CONFIG_PAGE_OFFSET=0xff60000000000000
CONFIG_PAGE_POOL=y
CONFIG_PAGE_REPORTING=y
@ -289,6 +294,7 @@ CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DPC=y
# CONFIG_PCIE_DW_DEBUGFS is not set
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_FU740=y
CONFIG_PCIE_PTM=y
@ -340,30 +346,41 @@ CONFIG_RISCV_ALTERNATIVE=y
CONFIG_RISCV_APLIC=y
CONFIG_RISCV_APLIC_MSI=y
# CONFIG_RISCV_BOOT_SPINWAIT is not set
CONFIG_RISCV_COMBO_SPINLOCKS=y
CONFIG_RISCV_DMA_NONCOHERENT=y
# CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS is not set
CONFIG_RISCV_IMSIC=y
CONFIG_RISCV_IMSIC_PCI=y
CONFIG_RISCV_INTC=y
# CONFIG_RISCV_IOMMU is not set
CONFIG_RISCV_ISA_C=y
CONFIG_RISCV_ISA_FALLBACK=y
CONFIG_RISCV_ISA_SUPM=y
CONFIG_RISCV_ISA_SVNAPOT=y
CONFIG_RISCV_ISA_SVPBMT=y
CONFIG_RISCV_ISA_V=y
CONFIG_RISCV_ISA_VENDOR_EXT=y
CONFIG_RISCV_ISA_VENDOR_EXT_ANDES=y
# CONFIG_RISCV_ISA_VENDOR_EXT_MIPS is not set
CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE=y
# CONFIG_RISCV_ISA_VENDOR_EXT_THEAD is not set
CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y
CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD=768
# CONFIG_RISCV_ISA_XTHEADVECTOR is not set
CONFIG_RISCV_ISA_ZACAS=y
CONFIG_RISCV_ISA_ZAWRS=y
CONFIG_RISCV_ISA_ZBA=y
CONFIG_RISCV_ISA_ZBB=y
CONFIG_RISCV_ISA_ZBC=y
CONFIG_RISCV_ISA_ZBKB=y
CONFIG_RISCV_ISA_ZICBOM=y
CONFIG_RISCV_ISA_ZICBOP=y
CONFIG_RISCV_ISA_ZICBOZ=y
CONFIG_RISCV_MISALIGNED=y
CONFIG_RISCV_PROBE_UNALIGNED_ACCESS=y
CONFIG_RISCV_SBI=y
CONFIG_RISCV_SBI_V01=y
# CONFIG_RISCV_TICKET_SPINLOCKS is not set
CONFIG_RISCV_TIMER=y
CONFIG_RISCV_USE_LINKER_RELAXATION=y
CONFIG_RPS=y