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realtek: rtl931x: psx28: specify RTL8224 reset GPIO

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The nRESET pins of the RTL8224 PHYs on the PSX28/ESX28 are wired to GPIO29
of the SoC, but this was never described in the devicetree.

GPIO 29 is the global reset shared by all PHYs across all MDIO busses. It
is intentionally not declared as reset-gpios on any bus: the MDIO driver /
phylink only support a reset GPIO per bus, not on the parent controller.
Attaching it to a single bus would still reset the PHYs on the other busses
as a side effect, leaving their software state out of sync with the
hardware and likely breaking them.

Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/23297
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Sven Eckelmann 2026-03-18 16:08:08 +01:00 committed by Robert Marko
parent db0ce075e6
commit 80e53edc87
1 changed files with 17 additions and 0 deletions
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17
target/linux/realtek/dts/rtl9312_plasmacloud_common.dtsi
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@ -456,3 +456,20 @@
nvmem-cells = <&macaddr_ubootenv_ethaddr 28>;
nvmem-cell-names = "mac-address";
};
&gpio0 {
/*
* GPIO 29 is the global reset shared by all PHYs across all MDIO busses.
* It is intentionally not declared as reset-gpios on any bus: the MDIO
* driver / phylink only support a reset GPIO per bus, not on the parent
* controller. Attaching it to a single bus would still reset the PHYs
* on the other busses as a side effect, leaving their software state
* out of sync with the hardware and likely breaking them.
*/
phy_reset {
gpio-hog;
gpios = <29 GPIO_ACTIVE_LOW>;
output-low;
line-name = "phy-reset";
};
};