From 94c79aebe3d026fbdc0ad8b4397943bb1d1b1382 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Tue, 5 May 2026 19:05:21 +0200 Subject: [PATCH] realtek: mdio: cleanup defines Convert hexadecimal defines to lowercase and remove unneeded brackets like upstream mdio does. While we are here remove unused RTMDIO_DATA_MASK macro. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/23230 Signed-off-by: Robert Marko --- .../drivers/net/mdio/mdio-realtek-otto.c | 75 +++++++++---------- 1 file changed, 37 insertions(+), 38 deletions(-) diff --git a/target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c b/target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c index 1a8964aa46..5c6e13d8ef 100644 --- a/target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c +++ b/target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c @@ -51,14 +51,13 @@ /* MDIO bus registers/fields */ #define RTMDIO_C45_DATA(devnum, regnum) ((((devnum) & GENMASK(4, 0)) << 16) | \ ((regnum) & GENMASK(15, 0))) -#define RTMDIO_DATA_MASK GENMASK(15, 0) #define RTMDIO_RUN BIT(0) -#define RTMDIO_838X_SMI_GLB_CTRL (0xa100) +#define RTMDIO_838X_SMI_GLB_CTRL 0xa100 #define RTMDIO_838X_SMI_GLB_PHY_MAN_24_27 BIT(7) #define RTMDIO_838X_SMI_GLB_PHY_PATCH_DONE BIT(15) -#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0 (0xa1b8) -#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1 (0xa1bc) +#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0 0xa1b8 +#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1 0xa1bc #define RTMDIO_838X_CMD_FAIL 0 /* No hardware support */ #define RTMDIO_838X_CMD_READ_C22 0 #define RTMDIO_838X_CMD_READ_C45 BIT(1) @@ -66,11 +65,11 @@ #define RTMDIO_838X_CMD_WRITE_C45 (BIT(1) | BIT(2)) #define RTMDIO_838X_CMD_MASK GENMASK(2, 0) #define RTMDIO_838X_C22_DATA(page, reg) ((reg) << 20 | RTMDIO_PAGE_SELECT << 15 | (page) << 3) -#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2 (0xa1c0) -#define RTMDIO_838X_SMI_POLL_CTRL (0xa17c) -#define RTMDIO_838X_SMI_PORT0_5_ADDR_CTRL (0xa1c8) +#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2 0xa1c0 +#define RTMDIO_838X_SMI_POLL_CTRL 0xa17c +#define RTMDIO_838X_SMI_PORT0_5_ADDR_CTRL 0xa1c8 -#define RTMDIO_839X_PHYREG_ACCESS_CTRL (0x03DC) +#define RTMDIO_839X_PHYREG_ACCESS_CTRL 0x03dc #define RTMDIO_839X_CMD_FAIL BIT(1) #define RTMDIO_839X_CMD_READ_C22 0 #define RTMDIO_839X_CMD_READ_C45 BIT(2) @@ -80,17 +79,17 @@ #define RTMDIO_839X_C22_DATA(page, reg) ((reg) << 5 | (page) << 10 | \ (((page) == RTMDIO_RAW_PAGE(RTMDIO_839X_NUM_PAGES)) ? \ RTMDIO_PAGE_SELECT : 0) << 23) -#define RTMDIO_839X_PHYREG_CTRL (0x03e0) +#define RTMDIO_839X_PHYREG_CTRL 0x03e0 #define RTMDIO_839X_PHYREG_SKIP_EXT_PAGE GENMASK(8, 0) -#define RTMDIO_839X_PHYREG_DATA_CTRL (0x03F0) -#define RTMDIO_839X_SMI_PORT_POLLING_CTRL (0x03fc) -#define RTMDIO_839X_SMI_GLB_CTRL (0x03f8) +#define RTMDIO_839X_PHYREG_DATA_CTRL 0x03f0 +#define RTMDIO_839X_SMI_PORT_POLLING_CTRL 0x03fc +#define RTMDIO_839X_SMI_GLB_CTRL 0x03f8 -#define RTMDIO_930X_SMI_GLB_CTRL (0xCA00) +#define RTMDIO_930X_SMI_GLB_CTRL 0xca00 #define RTMDIO_930X_SMI_GLB_INTF_SEL(bus) BIT(16 + (bus)) #define RTMDIO_930X_SMI_GLB_POLL_SEL(bus) BIT(20 + (bus)) -#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0 (0xCB70) -#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1 (0xCB74) +#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0 0xcb70 +#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1 0xcb74 #define RTMDIO_930X_CMD_FAIL BIT(25) #define RTMDIO_930X_CMD_READ_C22 0 #define RTMDIO_930X_CMD_READ_C45 BIT(1) @@ -98,28 +97,28 @@ #define RTMDIO_930X_CMD_WRITE_C45 (BIT(1) | BIT(2)) #define RTMDIO_930X_CMD_MASK (GENMASK(2, 0) | BIT(25)) #define RTMDIO_930X_C22_DATA(page, reg) ((reg) << 20 | RTMDIO_PAGE_SELECT << 15 | (page) << 3) -#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2 (0xCB78) -#define RTMDIO_930X_SMI_PORT0_15_POLLING_SEL (0xCA08) -#define RTMDIO_930X_SMI_PORT16_27_POLLING_SEL (0xCA0C) -#define RTMDIO_930X_SMI_MAC_TYPE_CTRL (0xCA04) +#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2 0xcb78 +#define RTMDIO_930X_SMI_PORT0_15_POLLING_SEL 0xca08 +#define RTMDIO_930X_SMI_PORT16_27_POLLING_SEL 0xca0c +#define RTMDIO_930X_SMI_MAC_TYPE_CTRL 0xca04 #define RTMDIO_930X_SMI_MAC_TYPE_P0_23(pn) (GENMASK(1, 0) << (((pn) / 4) * 2)) #define RTMDIO_930X_SMI_MAC_TYPE_P24_27(pn) (GENMASK(2, 0) << (((pn) - 24) * 3 + 12)) -#define RTMDIO_930X_SMI_POLL_CTRL (0xca90) -#define RTMDIO_930X_SMI_PRVTE_POLLING_CTRL (0xCA10) -#define RTMDIO_930X_SMI_10G_POLLING_REG0_CFG (0xCBB4) -#define RTMDIO_930X_SMI_10G_POLLING_REG9_CFG (0xCBB8) -#define RTMDIO_930X_SMI_10G_POLLING_REG10_CFG (0xCBBC) -#define RTMDIO_930X_SMI_PORT0_5_ADDR_CTRL (0xCB80) +#define RTMDIO_930X_SMI_POLL_CTRL 0xca90 +#define RTMDIO_930X_SMI_PRVTE_POLLING_CTRL 0xca10 +#define RTMDIO_930X_SMI_10G_POLLING_REG0_CFG 0xcbb4 +#define RTMDIO_930X_SMI_10G_POLLING_REG9_CFG 0xcbb8 +#define RTMDIO_930X_SMI_10G_POLLING_REG10_CFG 0xcbbc +#define RTMDIO_930X_SMI_PORT0_5_ADDR_CTRL 0xcb80 -#define RTMDIO_931X_SMI_PORT_POLLING_CTRL (0x0CCC) -#define RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL (0x0C14) -#define RTMDIO_931X_SMI_GLB_CTRL0 (0x0CC0) +#define RTMDIO_931X_SMI_PORT_POLLING_CTRL 0x0ccc +#define RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL 0x0c14 +#define RTMDIO_931X_SMI_GLB_CTRL0 0x0cc0 #define RTMDIO_931X_SMI_GLB_PRVTE0_POLL(bus) BIT(20 + (bus)) #define RTMDIO_931X_SMI_GLB_PRVTE1_POLL(bus) BIT(24 + (bus)) -#define RTMDIO_931X_SMI_GLB_CTRL1 (0x0CBC) +#define RTMDIO_931X_SMI_GLB_CTRL1 0x0cbc #define RTMDIO_931X_SMI_GLB_FMT_SEL_C45(bus) BIT((bus) * 2 + 1) #define RTMDIO_931X_SMI_GLB_FMT_SEL_FRC(bus) BIT((bus) * 2) -#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0 (0x0C00) +#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0 0x0c00 #define RTMDIO_931X_CMD_FAIL BIT(1) #define RTMDIO_931X_CMD_READ_C22 0 #define RTMDIO_931X_CMD_READ_C45 BIT(3) @@ -127,18 +126,18 @@ #define RTMDIO_931X_CMD_WRITE_C45 (BIT(3) | BIT(4)) #define RTMDIO_931X_CMD_MASK GENMASK(4, 0) #define RTMDIO_931X_C22_DATA(page, reg) ((reg) << 6 | (page) << 11) -#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3 (0x0C10) +#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3 0x0c10 #define RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL(pn) (0x0cac + ((pn) / 16) * 4) #define RTMDIO_931X_SMI_PHY_ABLTY_MDIO 0x0 #define RTMDIO_931X_SMI_PHY_ABLTY_SDS 0x2 #define RTMDIO_931X_SMI_PHY_ABLTY_MASK(pn) (GENMASK(1, 0) << (((pn) % 16) * 2)) -#define RTMDIO_931X_SMI_PORT_POLLING_SEL (0x0C9C) -#define RTMDIO_931X_SMI_PORT_ADDR_CTRL (0x0C74) -#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL0 (0x0CF0) -#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL1 (0x0CF4) -#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL2 (0x0CF8) -#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL3 (0x0CFC) -#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL4 (0x0D00) +#define RTMDIO_931X_SMI_PORT_POLLING_SEL 0x0c9c +#define RTMDIO_931X_SMI_PORT_ADDR_CTRL 0x0c74 +#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL0 0x0cf0 +#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL1 0x0cf4 +#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL2 0x0cf8 +#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL3 0x0cfc +#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL4 0x0d00 #define for_each_port(ctrl, pn) \ for_each_set_bit(pn, (ctrl)->valid_ports, RTMDIO_MAX_PORTS)