From c5f9a5e61cd066766c2d7e26bb57a75ce8c784d7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 11 Apr 2026 22:38:33 +0200 Subject: [PATCH] kernel/ixp4xx: restore files for v6.12 This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Link: https://github.com/openwrt/openwrt/pull/22896 Signed-off-by: Linus Walleij --- target/linux/ixp4xx/config-6.12 | 257 ++++++++++++ ...1-ARM-dts-ixp4xx-Fix-up-PCI-on-WG302.patch | 41 ++ ...ts-ixp4xx-Add-Netgear-WG302-v1-GPIOs.patch | 60 +++ ...dd-compatible-for-the-ixp4xx-eb-MMIO.patch | 26 ++ ...18-ARM-dts-Fix-up-wrv54g-device-tree.patch | 156 +++++++ ...xp4xx-Actiontec-MI424WR-device-trees.patch | 391 ++++++++++++++++++ ...x-Fix-up-Actiontec-MI424WR-DTS-files.patch | 70 ++++ ...dts-ixp4xx-Boot-NSLU2-from-harddrive.patch | 24 ++ ...2-ARM-dts-ixp4xx-OpenWrt-LED-aliases.patch | 228 ++++++++++ 9 files changed, 1253 insertions(+) create mode 100644 target/linux/ixp4xx/config-6.12 create mode 100644 target/linux/ixp4xx/patches-6.12/0001-ARM-dts-ixp4xx-Fix-up-PCI-on-WG302.patch create mode 100644 target/linux/ixp4xx/patches-6.12/0002-ARM-dts-ixp4xx-Add-Netgear-WG302-v1-GPIOs.patch create mode 100644 target/linux/ixp4xx/patches-6.12/0003-v6.18-gpio-mmio-Add-compatible-for-the-ixp4xx-eb-MMIO.patch create mode 100644 target/linux/ixp4xx/patches-6.12/0004-v6.18-ARM-dts-Fix-up-wrv54g-device-tree.patch create mode 100644 target/linux/ixp4xx/patches-6.12/0005-v6.18-ARM-dts-Add-ixp4xx-Actiontec-MI424WR-device-trees.patch create mode 100644 target/linux/ixp4xx/patches-6.12/0006-v6.19-ARM-dts-ixp4xx-Fix-up-Actiontec-MI424WR-DTS-files.patch create mode 100644 target/linux/ixp4xx/patches-6.12/301-ARM-dts-ixp4xx-Boot-NSLU2-from-harddrive.patch create mode 100644 target/linux/ixp4xx/patches-6.12/302-ARM-dts-ixp4xx-OpenWrt-LED-aliases.patch diff --git a/target/linux/ixp4xx/config-6.12 b/target/linux/ixp4xx/config-6.12 new file mode 100644 index 0000000000..499d9efc9f --- /dev/null +++ b/target/linux/ixp4xx/config-6.12 @@ -0,0 +1,257 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_AMD_PHY=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_IXP4XX=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_CPU_AUTO=y +# CONFIG_ARCH_MULTI_V4 is not set +# CONFIG_ARCH_MULTI_V4T is not set +CONFIG_ARCH_MULTI_V4_V5=y +CONFIG_ARCH_MULTI_V5=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_APPENDED_DTB=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +CONFIG_ARM_HAS_GROUP_RELOCS=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ATA=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BUFFER_HEAD=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_ENDIAN_BE32=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CPU_XSCALE=y +CONFIG_CRC16=y +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_DEV_IXP4XX=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_UART_8250=y +CONFIG_DEBUG_UART_8250_SHIFT=2 +CONFIG_DEBUG_UART_PHYS=0xc8000003 +CONFIG_DEBUG_UART_VIRT=0xfec00003 +CONFIG_DMA_OPS=y +CONFIG_DTC=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +# CONFIG_FARSYNC is not set +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FORCE_PCI=y +# CONFIG_FRAMER is not set +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GW_PLD=y +CONFIG_GPIO_IXP4XX=y +CONFIG_GRO_CELLS=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HDLC=y +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_IXP4XX=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_IOP3XX=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INTEL_IXP4XX_EB=y +CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_IWMMXT is not set +CONFIG_IXP4XX_ETH=y +CONFIG_IXP4XX_HSS=y +CONFIG_IXP4XX_IRQ=y +CONFIG_IXP4XX_NPE=y +CONFIG_IXP4XX_QMGR=y +CONFIG_IXP4XX_TIMER=y +CONFIG_IXP4XX_WATCHDOG=y +CONFIG_JBD2=y +CONFIG_LEDS_GPIO=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_OTP=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_IXP4XX=y +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux" +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_EGRESS=y +CONFIG_NET_INGRESS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_VENDOR_XSCALE=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y +CONFIG_PATA_IXP4XX_CF=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_IXP4XX=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REALTEK_PHY=y +CONFIG_REALTEK_PHY_HWMON=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SG_POOL=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SWPHY=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +CONFIG_USB_PCI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USE_OF=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WAN=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/target/linux/ixp4xx/patches-6.12/0001-ARM-dts-ixp4xx-Fix-up-PCI-on-WG302.patch b/target/linux/ixp4xx/patches-6.12/0001-ARM-dts-ixp4xx-Fix-up-PCI-on-WG302.patch new file mode 100644 index 0000000000..666c3e9af3 --- /dev/null +++ b/target/linux/ixp4xx/patches-6.12/0001-ARM-dts-ixp4xx-Fix-up-PCI-on-WG302.patch @@ -0,0 +1,41 @@ +From eff2700d2ec99aac06fff0ad35cbc594bd3e04a8 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Mon, 10 Feb 2025 10:31:16 +0100 +Subject: [PATCH 1/2] ARM: dts: ixp4xx: Fix up PCI on WG302 + +Looking at the board file for WG302 v2 was not a good idea +because the GPIO IRQ for slot 2 differs, and v1 uses GPIO +10 instead of GPIO 9. Fix it up. + +Signed-off-by: Linus Walleij +Link: https://lore.kernel.org/20250210-ixp4xx-dts-v1-2-6b752d745e04@linaro.org +--- + .../dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts +@@ -57,7 +57,7 @@ + status = "okay"; + + /* +- * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c) ++ * Taken from WG302 v1 PCI boardfile (wg302v1-pci.c) + * We have slots (IDSEL) 1 and 2 with one assigned IRQ + * each handling all IRQs. + */ +@@ -70,10 +70,10 @@ + <0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */ + <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ + /* IDSEL 2 */ +- <0x1000 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 9 */ +- <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ +- <0x1000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 9 */ +- <0x1000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 9 */ ++ <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ ++ <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */ ++ <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */ ++ <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */ + }; + + ethernet@c8009000 { diff --git a/target/linux/ixp4xx/patches-6.12/0002-ARM-dts-ixp4xx-Add-Netgear-WG302-v1-GPIOs.patch b/target/linux/ixp4xx/patches-6.12/0002-ARM-dts-ixp4xx-Add-Netgear-WG302-v1-GPIOs.patch new file mode 100644 index 0000000000..a855cef5d1 --- /dev/null +++ b/target/linux/ixp4xx/patches-6.12/0002-ARM-dts-ixp4xx-Add-Netgear-WG302-v1-GPIOs.patch @@ -0,0 +1,60 @@ +From f8a9ef38de91ddffa51255d15589c460bb6d9916 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Mon, 10 Feb 2025 10:31:17 +0100 +Subject: [PATCH 2/2] ARM: dts: ixp4xx: Add Netgear WG302 v1 GPIOs + +This adds GPIO LED indicators, the reset GPIO RESET +button on the Netgear WG302 v1 to the device tree. + +Signed-off-by: Linus Walleij +Link: https://lore.kernel.org/20250210-ixp4xx-dts-v1-3-6b752d745e04@linaro.org +--- + .../ixp/intel-ixp42x-netgear-wg302v1.dts | 30 +++++++++++++++++++ + 1 file changed, 30 insertions(+) + +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts +@@ -8,6 +8,7 @@ + + #include "intel-ixp42x.dtsi" + #include ++#include + + / { + model = "Netgear WG302 v1"; +@@ -32,6 +33,35 @@ + serial0 = &uart1; + }; + ++ leds { ++ compatible = "gpio-leds"; ++ test_led: led-test { ++ color = ; ++ function = "test"; ++ gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ wlan_led: led-wlan { ++ color = ; ++ function = LED_FUNCTION_WLAN; ++ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ linux,default-trigger = "phy0tx"; ++ }; ++ }; ++ ++ gpio_keys { ++ /* RESET is on GPIO13 which can't fire interrupts */ ++ compatible = "gpio-keys-polled"; ++ poll-interval = <100>; ++ ++ button-reset { ++ linux,code = ; ++ label = "reset"; ++ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ + soc { + bus@c4000000 { + flash@0,0 { diff --git a/target/linux/ixp4xx/patches-6.12/0003-v6.18-gpio-mmio-Add-compatible-for-the-ixp4xx-eb-MMIO.patch b/target/linux/ixp4xx/patches-6.12/0003-v6.18-gpio-mmio-Add-compatible-for-the-ixp4xx-eb-MMIO.patch new file mode 100644 index 0000000000..01ebf1c0b1 --- /dev/null +++ b/target/linux/ixp4xx/patches-6.12/0003-v6.18-gpio-mmio-Add-compatible-for-the-ixp4xx-eb-MMIO.patch @@ -0,0 +1,26 @@ +From 38623d532c99ebd926f4eebb7c7de19cb7e5aef4 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Fri, 22 Aug 2025 17:46:28 +0200 +Subject: [PATCH] gpio: mmio: Add compatible for the ixp4xx eb MMIO + +The IXP4xx expansion bus can have simple memory-mapped GPIO +on it. Using the proper device tree bindings, support probing +this directly from the device tree. + +Signed-off-by: Linus Walleij +Link: https://lore.kernel.org/r/20250822-ixp4xx-eb-mmio-gpio-v2-3-bd2edd4a9c74@linaro.org +Signed-off-by: Bartosz Golaszewski +--- + drivers/gpio/gpio-mmio.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpio/gpio-mmio.c ++++ b/drivers/gpio/gpio-mmio.c +@@ -687,6 +687,7 @@ static const struct of_device_id bgpio_o + { .compatible = "brcm,bcm6345-gpio" }, + { .compatible = "wd,mbl-gpio" }, + { .compatible = "ni,169445-nand-gpio" }, ++ { .compatible = "intel,ixp4xx-expansion-bus-mmio-gpio" }, + { } + }; + MODULE_DEVICE_TABLE(of, bgpio_of_match); diff --git a/target/linux/ixp4xx/patches-6.12/0004-v6.18-ARM-dts-Fix-up-wrv54g-device-tree.patch b/target/linux/ixp4xx/patches-6.12/0004-v6.18-ARM-dts-Fix-up-wrv54g-device-tree.patch new file mode 100644 index 0000000000..d1a1263c1a --- /dev/null +++ b/target/linux/ixp4xx/patches-6.12/0004-v6.18-ARM-dts-Fix-up-wrv54g-device-tree.patch @@ -0,0 +1,156 @@ +From c9cc6b6a7d23eea7ada69a9185a550c4f0b62319 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Wed, 25 Jun 2025 08:51:25 +0200 +Subject: [PATCH] ARM: dts: Fix up wrv54g device tree + +Fix up the KS8995 switch and PHYs the way that is most likely: + +- Phy 1-4 is certainly the PHYs of the KS8995 (mask 0x1e in + the outoftree code masks PHYs 1,2,3,4). +- Phy 5 is the MII-P5 separate WAN phy of the KS8995 directly + connected to EthC. +- The EthB MII is probably connected as CPU interface to the + KS8995. + +Properly integrate the KS8995 switch using the new bindings. + +Signed-off-by: Linus Walleij +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/20250625-ks8995-dsa-bindings-v2-2-ce71dce9be0b@linaro.org +Signed-off-by: Jakub Kicinski +--- + .../intel/ixp/intel-ixp42x-linksys-wrv54g.dts | 92 ++++++++++++++++--- + 1 file changed, 78 insertions(+), 14 deletions(-) + +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts +@@ -72,10 +72,55 @@ + cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + +- switch@0 { ++ ethernet-switch@0 { + compatible = "micrel,ks8995"; + reg = <0>; + spi-max-frequency = <50000000>; ++ ++ /* ++ * The PHYs are accessed over the external MDIO ++ * bus and not internally through the switch control ++ * registers. ++ */ ++ ethernet-ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ethernet-port@0 { ++ reg = <0>; ++ label = "1"; ++ phy-mode = "mii"; ++ phy-handle = <&phy1>; ++ }; ++ ethernet-port@1 { ++ reg = <1>; ++ label = "2"; ++ phy-mode = "mii"; ++ phy-handle = <&phy2>; ++ }; ++ ethernet-port@2 { ++ reg = <2>; ++ label = "3"; ++ phy-mode = "mii"; ++ phy-handle = <&phy3>; ++ }; ++ ethernet-port@3 { ++ reg = <3>; ++ label = "4"; ++ phy-mode = "mii"; ++ phy-handle = <&phy4>; ++ }; ++ ethernet-port@4 { ++ reg = <4>; ++ ethernet = <ðb>; ++ phy-mode = "mii"; ++ fixed-link { ++ speed = <100>; ++ full-duplex; ++ }; ++ }; ++ ++ }; + }; + }; + +@@ -135,40 +180,59 @@ + }; + + /* +- * EthB - connected to the KS8995 switch ports 1-4 +- * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to +- * all four switch ports, also using an out of tree multiphy patch. +- * Do we need a new binding and property for this? ++ * EthB connects to the KS8995 CPU port and faces ports 1-4 ++ * through the switch fabric. ++ * ++ * To complicate things, the MDIO channel is also only ++ * accessible through EthB, but used independently for PHY ++ * control. + */ +- ethernet@c8009000 { ++ ethb: ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; +- phy-mode = "rgmii"; +- phy-handle = <&phy4>; ++ phy-mode = "mii"; ++ fixed-link { ++ speed = <100>; ++ full-duplex; ++ }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + +- /* Should be ports 1-4 on the KS8995 switch */ ++ /* ++ * LAN ports 1-4 on the KS8995 switch ++ * and PHY5 for WAN need to be accessed ++ * through this external MDIO channel. ++ */ ++ phy1: ethernet-phy@1 { ++ reg = <1>; ++ }; ++ phy2: ethernet-phy@2 { ++ reg = <2>; ++ }; ++ phy3: ethernet-phy@3 { ++ reg = <3>; ++ }; + phy4: ethernet-phy@4 { + reg = <4>; + }; +- +- /* Should be port 5 on the KS8995 switch */ + phy5: ethernet-phy@5 { + reg = <5>; + }; + }; + }; + +- /* EthC - connected to KS8995 switch port 5 */ +- ethernet@c800a000 { ++ /* ++ * EthC connects to MII-P5 on the KS8995 bypassing ++ * all of the switch logic and facing PHY5 ++ */ ++ ethc: ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; +- phy-mode = "rgmii"; ++ phy-mode = "mii"; + phy-handle = <&phy5>; + }; + }; diff --git a/target/linux/ixp4xx/patches-6.12/0005-v6.18-ARM-dts-Add-ixp4xx-Actiontec-MI424WR-device-trees.patch b/target/linux/ixp4xx/patches-6.12/0005-v6.18-ARM-dts-Add-ixp4xx-Actiontec-MI424WR-device-trees.patch new file mode 100644 index 0000000000..cff30e693f --- /dev/null +++ b/target/linux/ixp4xx/patches-6.12/0005-v6.18-ARM-dts-Add-ixp4xx-Actiontec-MI424WR-device-trees.patch @@ -0,0 +1,391 @@ +From 85ac6b806993200fe117f4fd047c74784ec6b515 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Fri, 22 Aug 2025 19:56:16 +0200 +Subject: [PATCH] ARM: dts: Add ixp4xx Actiontec MI424WR device trees + +The Actiontex MI424WR is a pretty widespread home router, made +in many different revisions. + +Revisions A, C and D are based on IXP42x. We add a device tree +for the A/C variant and one for the D variant as these differ in +the location of the WAN PHY on the MDIO bus, and the ethernet +interfaces for the WAN PHY and the DSA switch are switched around. + +Signed-off-by: Linus Walleij +Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-3-cc804884474d@linaro.org +--- + arch/arm/boot/dts/intel/ixp/Makefile | 2 + + .../ixp/intel-ixp42x-actiontec-mi424wr-ac.dts | 37 +++ + .../ixp/intel-ixp42x-actiontec-mi424wr-d.dts | 38 +++ + .../ixp/intel-ixp42x-actiontec-mi424wr.dtsi | 272 ++++++++++++++++++ + 4 files changed, 349 insertions(+) + create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts + create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts + create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi + +--- a/arch/arm/boot/dts/intel/ixp/Makefile ++++ b/arch/arm/boot/dts/intel/ixp/Makefile +@@ -1,5 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_IXP4XX) += \ ++ intel-ixp42x-actiontec-mi424wr-ac.dtb \ ++ intel-ixp42x-actiontec-mi424wr-d.dtb \ + intel-ixp42x-linksys-nslu2.dtb \ + intel-ixp42x-linksys-wrv54g.dtb \ + intel-ixp42x-freecom-fsg-3.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts +@@ -0,0 +1,37 @@ ++// SPDX-License-Identifier: ISC ++/* ++ * Device Tree file for the IXP425-based Actiontec MI424WR revision A and C ++ * Based on a board file from OpenWrt by Jose Vasconcellos. ++ */ ++ ++/dts-v1/; ++ ++#include "intel-ixp42x-actiontec-mi424wr.dtsi" ++ ++/ { ++ model = "Actiontec MI424WR rev A/C"; ++ compatible = "actiontec,mi424wr-ac", "intel,ixp42x"; ++ ++ soc { ++ /* EthB used for WAN */ ++ ethernet@c8009000 { ++ phy-handle = <&phy17>; // 17 on revision A-C ++ ++ mdio { ++ phy17: ethernet-phy@17 { ++ /* WAN */ ++ reg = <17>; ++ }; ++ }; ++ }; ++ ++ /* EthC used for LAN */ ++ ethernet@c800a000 { ++ /* Fixed link to the CPU MII port on the KS8995 */ ++ fixed-link { ++ speed = <100>; ++ full-duplex; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts +@@ -0,0 +1,38 @@ ++// SPDX-License-Identifier: ISC ++/* ++ * Device Tree file for the IXP425-based Actiontec MI424WR revision D ++ * Based on a board file from OpenWrt by Jose Vasconcellos. ++ */ ++ ++/dts-v1/; ++ ++#include "intel-ixp42x-actiontec-mi424wr.dtsi" ++ ++/ { ++ model = "Actiontec MI424WR rev D"; ++ compatible = "actiontec,mi424wr-d", "intel,ixp42x"; ++ ++ soc { ++ /* EthB used for LAN */ ++ ethernet@c8009000 { ++ /* Fixed link to the CPU MII port on the KS8995 */ ++ fixed-link { ++ speed = <100>; ++ full-duplex; ++ }; ++ ++ mdio { ++ /* PHY ID 0x00221450 */ ++ phy5: ethernet-phy@5 { ++ /* WAN */ ++ reg = <5>; ++ }; ++ }; ++ }; ++ ++ /* EthC used for WAN */ ++ ethernet@c800a000 { ++ phy-handle = <&phy5>; // 5 on revision D ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi +@@ -0,0 +1,272 @@ ++// SPDX-License-Identifier: ISC ++/* ++ * Device Tree file for the IXP425-based Actiontec MI424WR ++ * Based on a board file from OpenWrt by Jose Vasconcellos. ++ */ ++ ++#include "intel-ixp42x.dtsi" ++#include ++#include ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x00000000 0x02000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8"; ++ stdout-path = "uart1:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led-wan-coax { ++ color = ; ++ function = "wan-coax"; ++ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ led-power-alarm { ++ color = ; ++ function = LED_FUNCTION_ALARM; ++ gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ led-power { ++ color = ; ++ function = LED_FUNCTION_POWER; ++ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ led-wireless { ++ color = ; ++ function = LED_FUNCTION_WLAN; ++ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ led-internet-down { ++ color = ; ++ function = "internet-down"; ++ gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ led-internet-up { ++ color = ; ++ function = "internet-up"; ++ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ led-lan-coax { ++ color = ; ++ function = "lan-coax"; ++ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ led-wan-ethernet-alarm { ++ color = ; ++ function = "wan-ethernet-alarm"; ++ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ /* The last three LEDs are not mounted but traces exist on the PCB */ ++ led-phone-1 { ++ color = ; ++ function = "phone-1"; ++ gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ led-phone-2 { ++ color = ; ++ function = "phone-2"; ++ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ led-voip { ++ color = ; ++ function = "voip"; ++ gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ ++ button-reset { ++ wakeup-source; ++ linux,code = ; ++ label = "reset"; ++ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ spi { ++ compatible = "spi-gpio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ sck-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; ++ mosi-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; ++ miso-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; ++ cs-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; ++ num-chipselects = <1>; ++ ++ ethernet-switch@0 { ++ compatible = "micrel,ks8995"; ++ reg = <0>; ++ spi-max-frequency = <50000000>; ++ ++ ethernet-ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ethernet-port@0 { ++ reg = <0>; ++ label = "lan1"; ++ phy-mode = "mii"; ++ phy-handle = <&phy1>; ++ }; ++ ethernet-port@1 { ++ reg = <1>; ++ label = "lan2"; ++ phy-mode = "mii"; ++ phy-handle = <&phy2>; ++ }; ++ ethernet-port@2 { ++ reg = <2>; ++ label = "lan3"; ++ phy-mode = "mii"; ++ phy-handle = <&phy3>; ++ }; ++ ethernet-port@3 { ++ reg = <3>; ++ label = "lan4"; ++ phy-mode = "mii"; ++ phy-handle = <&phy4>; ++ }; ++ ethernet-port@4 { ++ reg = <4>; ++ ethernet = <ðc>; ++ phy-mode = "mii"; ++ fixed-link { ++ speed = <100>; ++ full-duplex; ++ }; ++ }; ++ ++ }; ++ }; ++ }; ++ ++ soc { ++ bus@c4000000 { ++ flash@0,0 { ++ compatible = "intel,ixp4xx-flash", "cfi-flash"; ++ bank-width = <2>; ++ /* ++ * 8 MB of Flash in 64 0x20000 sized blocks ++ * mapped in at CS0. ++ */ ++ reg = <0 0x00000000 0x0800000>; ++ ++ /* Configure expansion bus to allow writes */ ++ intel,ixp4xx-eb-write-enable = <1>; ++ ++ partitions { ++ compatible = "redboot-fis"; ++ fis-index-block = <0x3f>; ++ }; ++ }; ++ gpio1: gpio@1,0 { ++ /* MMIO GPIO at CS1 */ ++ compatible = "intel,ixp4xx-expansion-bus-mmio-gpio"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ big-endian; ++ reg = <1 0x00000000 0x2>; ++ reg-names = "dat"; ++ /* Expansion bus settings */ ++ intel,ixp4xx-eb-write-enable = <1>; ++ ++ pci-reset-hog { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "PCI reset"; ++ }; ++ pstn-relay-hog-1 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "PSTN relay control 1"; ++ }; ++ pstn-relay-hog-2 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "PSTN relay control 2"; ++ }; ++ }; ++ }; ++ ++ pci@c0000000 { ++ status = "okay"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0xf800 0 0 7>; ++ interrupt-map = ++ /* IDSEL 13 */ ++ <0x6800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 8 */ ++ <0x6800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 6 */ ++ /* IDSEL 14 */ ++ <0x7000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */ ++ <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 8 */ ++ /* IDSEL 15 */ ++ <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 6 */ ++ <0x7800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 15 is irq 7 */ ++ }; ++ ++ ethb: ethernet@c8009000 { ++ status = "okay"; ++ queue-rx = <&qmgr 3>; ++ queue-txready = <&qmgr 20>; ++ phy-mode = "mii"; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* 1, 2, 3 and 4 are ports on the KS8995 switch */ ++ phy1: ethernet-phy@1 { ++ /* LAN1 */ ++ reg = <1>; ++ }; ++ phy2: ethernet-phy@2 { ++ /* LAN2 */ ++ reg = <2>; ++ }; ++ phy3: ethernet-phy@3 { ++ /* LAN3 */ ++ reg = <3>; ++ }; ++ phy4: ethernet-phy@4 { ++ /* LAN4 */ ++ reg = <4>; ++ }; ++ }; ++ }; ++ ++ ethc: ethernet@c800a000 { ++ status = "okay"; ++ queue-rx = <&qmgr 4>; ++ queue-txready = <&qmgr 21>; ++ phy-mode = "mii"; ++ }; ++ }; ++}; diff --git a/target/linux/ixp4xx/patches-6.12/0006-v6.19-ARM-dts-ixp4xx-Fix-up-Actiontec-MI424WR-DTS-files.patch b/target/linux/ixp4xx/patches-6.12/0006-v6.19-ARM-dts-ixp4xx-Fix-up-Actiontec-MI424WR-DTS-files.patch new file mode 100644 index 0000000000..2cdabfada3 --- /dev/null +++ b/target/linux/ixp4xx/patches-6.12/0006-v6.19-ARM-dts-ixp4xx-Fix-up-Actiontec-MI424WR-DTS-files.patch @@ -0,0 +1,70 @@ +From ececfba255bf3616301419e47a5c824e04b60ab8 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Thu, 11 Dec 2025 14:05:01 +0100 +Subject: [PATCH] ARM: dts: ixp4xx: Fix up Actiontec MI424WR DTS files + +The KS8995 switch was unconditionally wired to EthC (eth1) +on both MI424WR variants, this is wrong: the D revision has +the switch connected to EthB (eth0) so pull this assingment +out of the generic MI424WR DTSI file and make it a property +of the respective variants instead. + +Signed-off-by: Linus Walleij +Link: https://patch.msgid.link/20251211-ixp4xx-actiontec-dts-fix-v1-1-97af8e79d474@kernel.org +Signed-off-by: Krzysztof Kozlowski +--- + .../intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts | 11 +++++++++++ + .../intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts | 11 +++++++++++ + .../dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi | 1 - + 3 files changed, 22 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts +@@ -12,6 +12,17 @@ + model = "Actiontec MI424WR rev A/C"; + compatible = "actiontec,mi424wr-ac", "intel,ixp42x"; + ++ /* Connect the switch to EthC */ ++ spi { ++ ethernet-switch@0 { ++ ethernet-ports { ++ ethernet-port@4 { ++ ethernet = <ðc>; ++ }; ++ }; ++ }; ++ }; ++ + soc { + /* EthB used for WAN */ + ethernet@c8009000 { +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts +@@ -12,6 +12,17 @@ + model = "Actiontec MI424WR rev D"; + compatible = "actiontec,mi424wr-d", "intel,ixp42x"; + ++ /* Connect the switch to EthB */ ++ spi { ++ ethernet-switch@0 { ++ ethernet-ports { ++ ethernet-port@4 { ++ ethernet = <ðb>; ++ }; ++ }; ++ }; ++ }; ++ + soc { + /* EthB used for LAN */ + ethernet@c8009000 { +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi +@@ -152,7 +152,6 @@ + }; + ethernet-port@4 { + reg = <4>; +- ethernet = <ðc>; + phy-mode = "mii"; + fixed-link { + speed = <100>; diff --git a/target/linux/ixp4xx/patches-6.12/301-ARM-dts-ixp4xx-Boot-NSLU2-from-harddrive.patch b/target/linux/ixp4xx/patches-6.12/301-ARM-dts-ixp4xx-Boot-NSLU2-from-harddrive.patch new file mode 100644 index 0000000000..2a82ec0a2d --- /dev/null +++ b/target/linux/ixp4xx/patches-6.12/301-ARM-dts-ixp4xx-Boot-NSLU2-from-harddrive.patch @@ -0,0 +1,24 @@ +From 6484f966af53447deefcd4b805c201d8624981cb Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Mon, 29 May 2023 23:32:44 +0200 +Subject: [PATCH] ARM: dts: ixp4xx: Boot NSLU2 from harddrive + +This enforces harddrive boot on the NSLU2. The flash is too small +to hold any rootfs these days. + +Signed-off-by: Linus Walleij +--- + arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts +@@ -21,7 +21,7 @@ + }; + + chosen { +- bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; ++ bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; + stdout-path = "uart0:115200n8"; + }; + diff --git a/target/linux/ixp4xx/patches-6.12/302-ARM-dts-ixp4xx-OpenWrt-LED-aliases.patch b/target/linux/ixp4xx/patches-6.12/302-ARM-dts-ixp4xx-OpenWrt-LED-aliases.patch new file mode 100644 index 0000000000..7fd1854a0e --- /dev/null +++ b/target/linux/ixp4xx/patches-6.12/302-ARM-dts-ixp4xx-OpenWrt-LED-aliases.patch @@ -0,0 +1,228 @@ +From d672011e10097e5e61659a5d64ac9cb7b7544b60 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Wed, 25 Dec 2024 01:09:20 +0100 +Subject: [PATCH] ARM: dts: ixp4xx OpenWrt LED aliases + +This outoftree patch adds OpenWrt LED aliases to the DTS files +of supported devices. + +Signed-off-by: Linus Walleij +--- + .../boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts | 9 ++++++--- + .../boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts | 10 +++++++--- + .../dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts | 6 +++++- + .../boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts | 9 ++++++--- + .../boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 9 ++++++--- + .../dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts | 3 +++ + .../dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts | 5 ++++- + .../dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts | 6 +++++- + 8 files changed, 42 insertions(+), 15 deletions(-) + +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts +@@ -31,16 +31,19 @@ + }; + + aliases { ++ led-boot = &led_power; ++ led-failsafe = &led_power; ++ led-running = &led_power; ++ led-upgrade = &led_power; + serial0 = &uart0; + }; + + leds { + compatible = "gpio-leds"; +- led-power { ++ led_power: led-power { + label = "dsmg600:green:power"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; +- linux,default-trigger = "heartbeat"; + }; + led-wlan { + label = "dsmg600:green:wlan"; +@@ -48,7 +51,7 @@ + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + default-state = "on"; + /* We don't have WLAN trigger in the kernel (yet) */ +- linux,default-trigger = "netdev"; ++ linux,default-trigger = "phy0tx"; + }; + }; + +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts +@@ -29,6 +29,10 @@ + }; + + aliases { ++ led-boot = &led_ring; ++ led-failsafe = &led_sync; ++ led-running = &led_ring; ++ led-upgrade = &led_sync; + serial0 = &uart0; + }; + +@@ -112,7 +116,7 @@ + reg = <0x00 0x02>; + mask = <0x01>; + label = "fsg:blue:wlan"; +- linux,default-trigger = "wlan"; ++ linux,default-trigger = "phy0tx"; + default-state = "on"; + }; + led@0,1 { +@@ -139,7 +143,7 @@ + linux,default-trigger = ""; + default-state = "on"; + }; +- led@0,4 { ++ led_sync: led@0,4 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x08>; +@@ -147,7 +151,7 @@ + linux,default-trigger = ""; + default-state = "on"; + }; +- led@0,5 { ++ led_ring: led@0,5 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x10>; +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts +@@ -26,12 +26,16 @@ + }; + + aliases { ++ led-boot = &usr_led; ++ led-failsafe = &usr_led; ++ led-running = &usr_led; ++ led-upgrade = &usr_led; + serial0 = &uart0; + }; + + leds { + compatible = "gpio-leds"; +- led-user { ++ usr_led: led-user { + label = "gw2348:green:user"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + default-state = "on"; +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts +@@ -26,6 +26,10 @@ + }; + + aliases { ++ led-boot = &pwr_led; ++ led-failsafe = &pwr_led; ++ led-running = &pwr_led; ++ led-upgrade = &pwr_led; + serial0 = &uart0; + }; + +@@ -36,7 +40,7 @@ + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + /* We don't have WLAN trigger in the kernel (yet) */ +- linux,default-trigger = "netdev"; ++ linux,default-trigger = "phy0tx"; + }; + led-disk { + label = "nas100d:red:disk"; +@@ -44,11 +48,10 @@ + default-state = "on"; + linux,default-trigger = "disk-activity"; + }; +- led-power { ++ pwr_led: led-power { + label = "nas100d:red:power"; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + default-state = "on"; +- linux,default-trigger = "heartbeat"; + }; + }; + +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts +@@ -26,18 +26,21 @@ + }; + + aliases { ++ led-boot = &led_status; ++ led-failsafe = &led_status; ++ led-running = &led_ready; ++ led-upgrade = &led_status; + serial0 = &uart0; + }; + + leds { + compatible = "gpio-leds"; +- led-status { ++ led_status: led-status { + label = "nslu2:red:status"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; +- linux,default-trigger = "heartbeat"; + }; +- led-ready { ++ led_ready: led-ready { + label = "nslu2:green:ready"; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts +@@ -29,6 +29,9 @@ + }; + + aliases { ++ led-boot = &test_led; ++ led-failsafe = &test_led; ++ led-upgrade = &test_led; + /* These are switched around */ + serial0 = &uart1; + }; +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts +@@ -29,6 +29,10 @@ + }; + + aliases { ++ led-boot = &pwr_led; ++ led-failsafe = &pwr_led; ++ led-running = &pwr_led; ++ led-upgrade = &pwr_led; + /* These are switched around */ + serial0 = &uart1; + serial1 = &uart0; +@@ -67,7 +71,6 @@ + label = "usr8200:green:pwr"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; +- linux,default-trigger = "heartbeat"; + }; + }; + +--- a/arch/arm/boot/dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts ++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts +@@ -25,12 +25,16 @@ + }; + + aliases { ++ led-boot = &usr_led; ++ led-failsafe = &usr_led; ++ led-running = &usr_led; ++ led-upgrade = &usr_led; + serial0 = &uart0; + }; + + leds { + compatible = "gpio-leds"; +- led-user { ++ usr_led: led-user { + label = "gw2358:green:LED"; + gpios = <&pld1 0 GPIO_ACTIVE_LOW>; + default-state = "on";