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realtek: eth: sort and rename defines

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Several defines still use the old prefix and are not sorted
alphabetically. Rearange the header file and the configuration
structures.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23145
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Markus Stockhausen 2026-04-28 21:16:38 +02:00 committed by Robert Marko
parent b07fe8216d
commit c689be9eba
2 changed files with 24 additions and 29 deletions
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24
target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c
View File

@ -1326,14 +1326,14 @@ static const struct rteth_config rteth_838x_cfg = {
.qm_pkt2cpu_intpri_map = RTETH_838X_QM_PKT2CPU_INTPRI_MAP,
.qm_rsn2cpuqid_ctrl = RTETH_838X_QM_PKT2CPU_INTPRI_0,
.qm_rsn2cpuqid_cnt = RTETH_838X_QM_PKT2CPU_INTPRI_CNT,
.dma_if_ctrl = RTETH_838X_DMA_IF_CTRL,
.dma_if_intr_sts = RTETH_838X_DMA_IF_INTR_STS,
.dma_if_intr_msk = RTETH_838X_DMA_IF_INTR_MSK,
.dma_if_rx_ring_cntr = RTETH_838X_DMA_IF_RX_RING_CNTR,
.dma_if_rx_ring_size = RTETH_838X_DMA_IF_RX_RING_SIZE,
.dma_if_ctrl = RTL838X_DMA_IF_CTRL,
.dma_rx_base = RTETH_838X_DMA_RX_BASE,
.dma_tx_base = RTETH_838X_DMA_TX_BASE,
.mac_force_mode_ctrl = RTETH_838X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL838X_DMA_RX_BASE,
.dma_tx_base = RTL838X_DMA_TX_BASE,
.rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
.mac_reg = { RTETH_838X_MAC_ADDR_CTRL,
RTETH_838X_MAC_ADDR_CTRL_ALE,
@ -1372,14 +1372,14 @@ static const struct rteth_config rteth_839x_cfg = {
.qm_pkt2cpu_intpri_map = RTETH_839X_QM_PKT2CPU_INTPRI_MAP,
.qm_rsn2cpuqid_ctrl = RTETH_839X_QM_PKT2CPU_INTPRI_0,
.qm_rsn2cpuqid_cnt = RTETH_839X_QM_PKT2CPU_INTPRI_CNT,
.dma_if_ctrl = RTETH_839X_DMA_IF_CTRL,
.dma_if_intr_sts = RTETH_839X_DMA_IF_INTR_STS,
.dma_if_intr_msk = RTETH_839X_DMA_IF_INTR_MSK,
.dma_if_rx_ring_cntr = RTETH_839X_DMA_IF_RX_RING_CNTR,
.dma_if_rx_ring_size = RTETH_839X_DMA_IF_RX_RING_SIZE,
.dma_if_ctrl = RTL839X_DMA_IF_CTRL,
.dma_rx_base = RTETH_839X_DMA_RX_BASE,
.dma_tx_base = RTETH_839X_DMA_TX_BASE,
.mac_force_mode_ctrl = RTETH_839X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL839X_DMA_RX_BASE,
.dma_tx_base = RTL839X_DMA_TX_BASE,
.rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
.mac_reg = { RTETH_839X_MAC_ADDR_CTRL },
.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
@ -1416,16 +1416,16 @@ static const struct rteth_config rteth_930x_cfg = {
.mac_l2_port_ctrl = RTETH_930X_MAC_L2_PORT_CTRL,
.qm_rsn2cpuqid_ctrl = RTETH_930X_QM_RSN2CPUQID_CTRL_0,
.qm_rsn2cpuqid_cnt = RTETH_930X_QM_RSN2CPUQID_CTRL_CNT,
.dma_if_ctrl = RTETH_930X_DMA_IF_CTRL,
.dma_if_intr_sts = RTETH_930X_DMA_IF_INTR_STS,
.dma_if_intr_msk = RTETH_930X_DMA_IF_INTR_MSK,
.dma_if_rx_ring_cntr = RTETH_930X_DMA_IF_RX_RING_CNTR,
.dma_if_rx_ring_size = RTETH_930X_DMA_IF_RX_RING_SIZE,
.dma_rx_base = RTETH_930X_DMA_RX_BASE,
.dma_tx_base = RTETH_930X_DMA_TX_BASE,
.l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
.l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,
.dma_if_ctrl = RTL930X_DMA_IF_CTRL,
.mac_force_mode_ctrl = RTETH_930X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL930X_DMA_RX_BASE,
.dma_tx_base = RTL930X_DMA_TX_BASE,
.rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,
.mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL },
.l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
@ -1461,16 +1461,16 @@ static const struct rteth_config rteth_931x_cfg = {
.mac_l2_port_ctrl = RTETH_931X_MAC_L2_PORT_CTRL,
.qm_rsn2cpuqid_ctrl = RTETH_931X_QM_RSN2CPUQID_CTRL_0,
.qm_rsn2cpuqid_cnt = RTETH_931X_QM_RSN2CPUQID_CTRL_CNT,
.dma_if_ctrl = RTETH_931X_DMA_IF_CTRL,
.dma_if_intr_sts = RTETH_931X_DMA_IF_INTR_STS,
.dma_if_intr_msk = RTETH_931X_DMA_IF_INTR_MSK,
.dma_if_rx_ring_cntr = RTETH_931X_DMA_IF_RX_RING_CNTR,
.dma_if_rx_ring_size = RTETH_931X_DMA_IF_RX_RING_SIZE,
.dma_rx_base = RTETH_931X_DMA_RX_BASE,
.dma_tx_base = RTETH_931X_DMA_TX_BASE,
.l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
.l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,
.dma_if_ctrl = RTL931X_DMA_IF_CTRL,
.mac_force_mode_ctrl = RTETH_931X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL931X_DMA_RX_BASE,
.dma_tx_base = RTL931X_DMA_TX_BASE,
.rst_glb_ctrl = RTL931X_RST_GLB_CTRL,
.mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL },
.l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,

29
target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.h
View File

@ -8,10 +8,13 @@
/* Register definition */
#define RTETH_838X_CPU_PORT 28
#define RTETH_838X_DMA_IF_CTRL (0x9f58)
#define RTETH_838X_DMA_IF_INTR_MSK (0x9f50)
#define RTETH_838X_DMA_IF_INTR_STS (0x9f54)
#define RTETH_838X_DMA_IF_RX_RING_CNTR (0xb7e8)
#define RTETH_838X_DMA_IF_RX_RING_SIZE (0xb7e4)
#define RTETH_838X_DMA_RX_BASE (0x9f00)
#define RTETH_838X_DMA_TX_BASE (0x9f40)
#define RTETH_838X_MAC_ADDR_CTRL (0xa9ec)
#define RTETH_838X_MAC_ADDR_CTRL_ALE (0x6b04)
#define RTETH_838X_MAC_ADDR_CTRL_MAC (0xa320)
@ -24,10 +27,13 @@
#define RTETH_838X_RMA_CTRL_1 (0x4304)
#define RTETH_839X_CPU_PORT 52
#define RTETH_839X_DMA_IF_CTRL (0x786c)
#define RTETH_839X_DMA_IF_INTR_MSK (0x7864)
#define RTETH_839X_DMA_IF_INTR_STS (0x7868)
#define RTETH_839X_DMA_IF_RX_RING_CNTR (0x603c)
#define RTETH_839X_DMA_IF_RX_RING_SIZE (0x6038)
#define RTETH_839X_DMA_RX_BASE (0x780c)
#define RTETH_839X_DMA_TX_BASE (0x784c)
#define RTETH_839X_MAC_ADDR_CTRL (0x02b4)
#define RTETH_839X_MAC_FORCE_MODE_CTRL (0x02bc + RTETH_839X_CPU_PORT * 4)
#define RTETH_839X_MAC_L2_PORT_CTRL (0x8004 + RTETH_839X_CPU_PORT * 128)
@ -40,10 +46,13 @@
#define RTETH_839X_RMA_CTRL_3 (0x120c)
#define RTETH_930X_CPU_PORT 28
#define RTETH_930X_DMA_IF_CTRL (0xe028)
#define RTETH_930X_DMA_IF_INTR_MSK (0xe010)
#define RTETH_930X_DMA_IF_INTR_STS (0xe01c)
#define RTETH_930X_DMA_IF_RX_RING_CNTR (0x7c8c)
#define RTETH_930X_DMA_IF_RX_RING_SIZE (0x7c60)
#define RTETH_930X_DMA_RX_BASE (0xdf00)
#define RTETH_930X_DMA_TX_BASE (0xe000)
#define RTETH_930X_MAC_FORCE_MODE_CTRL (0xca1c + RTETH_930X_CPU_PORT * 4)
#define RTETH_930X_MAC_L2_ADDR_CTRL (0xc714)
#define RTETH_930X_MAC_L2_PORT_CTRL (0x3268 + RTETH_930X_CPU_PORT * 64)
@ -54,10 +63,13 @@
#define RTETH_930X_RMA_CTRL_2 (0x9e68)
#define RTETH_931X_CPU_PORT 56
#define RTETH_931X_DMA_IF_CTRL (0x0928)
#define RTETH_931X_DMA_IF_INTR_MSK (0x0910)
#define RTETH_931X_DMA_IF_INTR_STS (0x091c)
#define RTETH_931X_DMA_IF_RX_RING_CNTR (0x20ac)
#define RTETH_931X_DMA_IF_RX_RING_SIZE (0x2080)
#define RTETH_931X_DMA_RX_BASE (0x0800)
#define RTETH_931X_DMA_TX_BASE (0x0900)
#define RTETH_931X_MAC_FORCE_MODE_CTRL (0x0dcc + RTETH_931X_CPU_PORT * 4)
#define RTETH_931X_MAC_L2_ADDR_CTRL (0x135c)
#define RTETH_931X_MAC_L2_PORT_CTRL (0x6000 + RTETH_931X_CPU_PORT * 128)
@ -87,32 +99,15 @@
*/
/* DMA interrupt control and status registers */
#define RTL838X_DMA_IF_CTRL (0x9f58)
#define RTL839X_DMA_IF_CTRL (0x786c)
#define RTL930X_DMA_IF_CTRL (0xe028)
#define RTL930X_L2_NTFY_IF_INTR_MSK (0xe04C)
#define RTL930X_L2_NTFY_IF_INTR_STS (0xe050)
/* TODO: RTL931X_DMA_IF_CTRL has different bits meanings */
#define RTL931X_DMA_IF_CTRL (0x0928)
#define RTL931X_L2_NTFY_IF_INTR_MSK (0x09E4)
#define RTL931X_L2_NTFY_IF_INTR_STS (0x09E8)
#define RTL839X_DMA_IF_INTR_NOTIFY_MASK GENMASK(22, 20)
/* Ringbuffer setup */
#define RTL838X_DMA_RX_BASE (0x9f00)
#define RTL839X_DMA_RX_BASE (0x780c)
#define RTL930X_DMA_RX_BASE (0xdf00)
#define RTL931X_DMA_RX_BASE (0x0800)
#define RTL838X_DMA_TX_BASE (0x9f40)
#define RTL839X_DMA_TX_BASE (0x784c)
#define RTL930X_DMA_TX_BASE (0xe000)
#define RTL931X_DMA_TX_BASE (0x0900)
#define RTL838X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0x9F48)
#define RTL930X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0xE008)