updated dts
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@ -0,0 +1,258 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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// Copyright (c) 2026, Your Name <your@email.com>
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/*
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* What is working?
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*
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* - CPU
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- RAM
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- 8MB Flash (bootloader)
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* - USB
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*
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* What is NOT working?
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*
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* - 128MB nand (2x kernel, 2x rootfs, 1x rootfs_data)
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* - switches (QCA8075, QCA8335)
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* - wifi (QCA9984, * wifi I did get working, I just have to copy the DTS code + board.bin binaries back)
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*
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* WARNING: ENSURE BOARD.BIN AND CALDATA IS NOT COMMITTED TO GIT REPOSITORY (INTELLECTUAL PROPERTY CONCERNS)
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*
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*/
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#include "qcom-ipq4019-ap.dk04.1.dtsi"
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/*
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* REQUIRED: The following is required as recent mainline versions of OpenWRT
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* now define these with settings that are incorrect for our router
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*
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* The conflict is with reserved/in-use memory & the "qcom,nand@7980000" node
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*
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*/
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/delete-node/ &nand;
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/* /delete-node/ &qpic_bam; */
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/ {
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model = "TRENDnet TEW-829DRU";
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compatible = "trendnet,tew-829dru", "qcom,ipq4019-dk04.1-c1", "qcom,ipq4019";
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/* temporary, delete the inherited reserved memory node */
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/delete-node/ reserved-memory;
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chosen {
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/* For Mainline/OpenWrt 21.02+ kernels: */
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bootargs = "console=ttyHSL0,115200n8 rootfstype=squashfs,jffs2";
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};
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&qpic_bam {
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status = "okay";
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};
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soc {
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qcom,nand@7980000 {
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compatible = "qcom,msm-nand";
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status = "okay";
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reg = <0x07980000 0x40000>, <0x07984000 0x1a000>;
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reg-names = "nand_phys", "bam_phys";
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interrupts = <0 101 0>;
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interrupt-names = "bam_irq";
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_QPIC_AHB_CLK>, <&gcc GCC_QPIC_CLK>;
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/* KEEP dmas property - it references &qpic_bam */
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dmas = <&qpic_bam 0>, <&qpic_bam 1>, <&qpic_bam 2>;
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dma-names = "tx", "rx", "cmd";
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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nand@0 {
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compatible = "qcom,nandcs";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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nand-bus-width = <8>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* 8MB BOOTLOADER LAYOUT */
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partition@0 { label = "0:SBL1"; reg = <0x0 0x40000>; read-only; };
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partition@40000 { label = "0:MIBIB"; reg = <0x40000 0x20000>; read-only; };
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partition@60000 { label = "0:QSEE"; reg = <0x60000 0x60000>; read-only; };
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partition@c0000 { label = "0:CDT"; reg = <0xc0000 0x10000>; read-only; };
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partition@d0000 { label = "0:DDRPARAMS"; reg = <0xd0000 0x10000>; read-only; };
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partition@e0000 { label = "0:APPSBLENV"; reg = <0xe0000 0x10000>; };
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partition@f0000 { label = "0:APPSBL"; reg = <0xf0000 0x80000>; read-only; };
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partition@170000 { label = "0:ART"; reg = <0x170000 0x10000>; read-only; };
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/* 128MB NAND LAYOUT */
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/* Critical: Physical offsets calculated from sequential layout */
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partition@180000 { label = "rootfs"; reg = <0x180000 0x3000000>; };
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partition@3180000 { label = "rootfs_1"; reg = <0x3180000 0x3000000>; };
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partition@6180000 { label = "overlay"; reg = <0x6180000 0x2000000>; };
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};
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/*end of partition block */
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};
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/* end of nand@0 block */
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};
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/* end of &nand block */
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};
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/* end of soc block */
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};
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/* end of root block */
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&usb3 {
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status = "okay";
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dr_mode = "host";
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phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
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phy-names = "usb2-phy", "usb3-phy";
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/* vbus-supply removed because GPIO 48 hog handles power enable */
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};
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&usb3_hs_phy {
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status = "okay";
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};
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&usb3_ss_phy {
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status = "okay";
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};
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&usb2 {
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status = "okay";
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};
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&usb2_hs_phy {
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status = "okay";
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};
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&blsp1_uart1 {
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status = "okay";
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pinctrl-0 = <&tew_uart0_pins>;
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pinctrl-names = "default";
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};
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&blsp1_uart2 {
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status = "okay";
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pinctrl-0 = <&tew_uart1_pins>;
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pinctrl-names = "default";
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};
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&tlmm {
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/* Add this GPIO Hog for USB Power */
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usb_power_en: usb-power-en {
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gpio-hog;
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gpios = <48 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "usb-power-enable";
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};
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/* pinmux / gpios */
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/* Using Stock Router Pinout for UART0 (Console) */
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tew_uart0_pins: uart0-state {
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pins = "gpio16", "gpio17";
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function = "blsp_uart0";
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bias-disable;
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};
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/* Using Stock Router Pinout for UART1 (2 pins, not 4) */
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tew_uart1_pins: uart1-state {
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pins = "gpio8", "gpio9";
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function = "blsp_uart1";
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bias-disable;
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};
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led0_pinmux {
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linux,phandle = <0x52>;
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phandle = <0x52>;
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mux_1 {
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pins = "gpio36";
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function = "led0";
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bias-pull-down;
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};
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mux_2 {
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pins = "gpio40";
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function = "led4";
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bias-pull-down;
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};
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};
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uart1_pinmux {
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linux,phandle = <0x56>;
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phandle = <0x56>;
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mux {
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pins = "gpio8\0gpio9\0gpio10\0gpio11";
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function = "blsp_uart1";
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bias-disable;
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};
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};
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spi_0_pinmux {
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linux,phandle = <0x4a>;
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phandle = <0x4a>;
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mux {
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pins = "gpio12\0gpio13\0gpio14\0gpio15";
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function = "blsp_spi0";
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bias-disable;
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};
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};
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i2c_0_pinmux {
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linux,phandle = <0x4f>;
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phandle = <0x4f>;
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mux {
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pins = "gpio20\0gpio21";
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function = "blsp_i2c0";
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bias-disable;
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};
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};
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ts_0_pinmux {
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mux_1 {
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pins = "gpio34";
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output-high;
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};
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mux_2 {
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pins = "gpio35";
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input-enable;
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bias-pull-up;
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};
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};
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/* end of pinmux/gpios */
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};
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/* CHANGE 5: Add Switch Configuration if not present in the .dtsi */
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/* The AP-DK04.1.dtsi might not have the specific QCA8337 setup for the TEW-829DRU */
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/* If the SDK .dtsi already has the switch defined correctly, you can skip this. */
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/* If not, append the &gmac1 and &mdio blocks here (from previous steps). */
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/* CHANGE 6: Add wifi from existing/old DTS config attempts, and copy board*.bin (CALDATA) files */
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