fixing things
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@ -60,123 +60,21 @@
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};
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};
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&mdio {
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status = "okay";
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pinctrl-0 = <&mdio_pins>;
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pinctrl-names = "default";
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/*
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* DELETE the upstream qca8075-package@0 node.
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* Upstream qcom-ipq4019.dtsi defines the package at reg=<0> (addresses 0-4).
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* Our board hardware-straps QCA8075 to MDIO addresses 8-12.
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* Without this delete, the driver probes addresses 0-5 and panics on missing addr 5.
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*/
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/delete-node/ ethernet-phy-package@0;
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/*
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* QCA8075: 5-port PHY package.
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* Board hardware-straps the MDIO base address to 8.
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* PHYs at addresses 8-12, PSGMII calibration PHY implicit at base+5=13.
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* The qcom,qca8075-package driver handles PSGMII bring-up internally.
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* tx-drive-strength-milliwatt = 300 per IPQ4019 reference design spec.
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*/
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ethernet-phy-package@8 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,qca8075-package";
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reg = <8>;
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qcom,tx-drive-strength-milliwatt = <300>;
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ethphy8: ethernet-phy@8 { reg = <8>; }; /* WAN1 */
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ethphy9: ethernet-phy@9 { reg = <9>; }; /* WAN2 */
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ethphy10: ethernet-phy@10 { reg = <10>; }; /* LAN1 */
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ethphy11: ethernet-phy@11 { reg = <11>; }; /* LAN2 */
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ethphy12: ethernet-phy@12 { reg = <12>; }; /* LAN3 / combo */
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};
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qca8337: switch@10 {
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compatible = "qca,qca8337";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x10>;
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dsa,member = <1 0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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qca8337_phy0: ethernet-phy@0 { reg = <0>; };
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qca8337_phy1: ethernet-phy@1 { reg = <1>; };
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qca8337_phy2: ethernet-phy@2 { reg = <2>; };
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qca8337_phy3: ethernet-phy@3 { reg = <3>; };
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qca8337_phy4: ethernet-phy@4 { reg = <4>; };
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "cpu";
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phy-mode = "rgmii";
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ethernet = <&swport5>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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phy-handle = <&qca8337_phy0>;
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};
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port@2 {
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reg = <2>;
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label = "lan5";
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phy-handle = <&qca8337_phy1>;
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};
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port@3 {
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reg = <3>;
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label = "lan6";
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phy-handle = <&qca8337_phy2>;
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};
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port@4 {
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reg = <4>;
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label = "lan7";
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phy-handle = <&qca8337_phy3>;
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};
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port@5 {
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reg = <5>;
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label = "lan8";
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phy-handle = <&qca8337_phy4>;
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};
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};
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};
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/* QCA8075 (TOP SWITCH) — ESS built-in switch block */
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&switch {
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status = "okay";
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dsa,member = <0 0>;
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mdio-bus = <&mdio>;
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//qca,mdio = <&mdio>; //alternative if above not work
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/*
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* psgmii-ethphy points to the last PHY in the QCA8075 package (ethphy12).
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* This is the combo port and serves as the PSGMII calibration PHY.
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* The qca8075-package driver uses this for SerDes bring-up sequencing.
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* psgmii-ethphy points to ethphy12 (LAN3/combo port).
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* This is the PSGMII calibration PHY for SerDes bring-up sequencing.
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*/
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psgmii-ethphy = <ðphy12>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -225,16 +123,126 @@ qca8337: switch@10 {
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};
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/*
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* NO port@6 — valid ESS indices are 0-5 only (num_ports=6).
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* QCA8337 is NOT cascaded here. (?It lives on gmac1 independently?)
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* QCA8337 cascades from swport5 via RGMII, not as a child port here.
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*/
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};
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};
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/* end of &switch (QCA8075) */
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&mdio {
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status = "okay";
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pinctrl-0 = <&mdio_pins>;
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pinctrl-names = "default";
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/*
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* DELETE the upstream qca8075-package@0 node.
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* Upstream qcom-ipq4019.dtsi defines the package at reg=<0> (addresses 0-4).
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* Our board hardware-straps QCA8075 to MDIO addresses 8-12.
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* Without this delete, the driver probes addresses 0-5 and panics on missing addr 5.
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*/
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/delete-node/ ethernet-phy-package@0;
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/*
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* QCA8075: 5-port PHY package. TOP SWITCH.
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* Board hardware-straps the MDIO base address to 8.
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* PHYs at addresses 8-12, PSGMII calibration PHY implicit at base+5=13.
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* The qcom,qca8075-package driver handles PSGMII bring-up internally.
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* tx-drive-strength-milliwatt = 300 per IPQ4019 reference design spec.
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*/
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ethernet-phy-package@8 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,qca8075-package";
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reg = <8>;
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qcom,tx-drive-strength-milliwatt = <300>;
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ethphy8: ethernet-phy@8 { reg = <8>; }; /* WAN1 */
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ethphy9: ethernet-phy@9 { reg = <9>; }; /* WAN2 */
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ethphy10: ethernet-phy@10 { reg = <10>; }; /* LAN1 */
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ethphy11: ethernet-phy@11 { reg = <11>; }; /* LAN2 */
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ethphy12: ethernet-phy@12 { reg = <12>; }; /* LAN3 / PSGMII cal PHY */
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};
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/*
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* QCA8337: DSA switch. BOTTOM SWITCH, cascaded from QCA8075 swport5.
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* Connected via RGMII fixed-link to ESS swport5 (the cascade port).
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* MDIO address 0x10 on the shared bus for management access.
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* Internal MDIO bus manages PHYs 0-4 (LAN4-LAN8).
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*/
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qca8337: switch@10 {
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compatible = "qca,qca8337";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x10>;
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dsa,member = <1 0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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qca8337_phy0: ethernet-phy@0 { reg = <0>; }; /* LAN4 */
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qca8337_phy1: ethernet-phy@1 { reg = <1>; }; /* LAN5 */
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qca8337_phy2: ethernet-phy@2 { reg = <2>; }; /* LAN6 */
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qca8337_phy3: ethernet-phy@3 { reg = <3>; }; /* LAN7 */
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qca8337_phy4: ethernet-phy@4 { reg = <4>; }; /* LAN8 */
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "cpu";
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phy-mode = "rgmii";
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ethernet = <&swport5>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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phy-handle = <&qca8337_phy0>;
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};
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port@2 {
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reg = <2>;
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label = "lan5";
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phy-handle = <&qca8337_phy1>;
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};
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port@3 {
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reg = <3>;
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label = "lan6";
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phy-handle = <&qca8337_phy2>;
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};
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port@4 {
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reg = <4>;
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label = "lan7";
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phy-handle = <&qca8337_phy3>;
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};
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port@5 {
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reg = <5>;
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label = "lan8";
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phy-handle = <&qca8337_phy4>;
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};
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};
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};
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/* end of QCA8337 */
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};
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/* end of &mdio */
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/* 8MB FLASH CHIP (Macronix MX25L6433F SPI NOR 8MB) */
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&blsp1_spi1 {
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/* 8MB FLASH CHIP (Macronix MX25L6433F SPI NOR 8MB) */
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status = "okay";
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pinctrl-0 = <&spi_0_pinmux>;
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@ -583,19 +591,19 @@ qca8337: switch@10 {
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/*
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// TODO:
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NAND TODO:
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- FIX NAND - fucking nand is impossible, memory address conflicts with qcom-ipq4019.dtsi
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- DO NOT MIX SPI/NAND PARTITIONS!
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- NAND IS DIFFERENT GPIOS, GPIO53 IS IN USE - FIND CORRECT NAND GPIO
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/* CHANGE 1: ADD NAND - fucking nand is impossible, memory address conflicts with qcom-ipq4019.dtsi */
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/* DO NOT MIX SPI/NAND PARTITIONS! */
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LED TODO:
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- Probe GPIOs
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- Add DTS config for LEDs
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*/
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/* CHANGE 2: Add Switch Configuration if not present in the .dtsi */
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/* The AP-DK04.1.dtsi might not have the specific QCA8337 setup for the TEW-829DRU */
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/* If the SDK .dtsi already has the switch defined correctly, you can skip this. */
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/* If not, append the &gmac1 and &mdio blocks here (from previous steps). */
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/* CHANGE 3: Add wifi from existing/old DTS config attempts, and copy board*.bin (CALDATA) files */
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