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598
target/linux/ipq40xx/dts/qcom-ipq4019-tew-829dru.dts
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598
target/linux/ipq40xx/dts/qcom-ipq4019-tew-829dru.dts
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@ -0,0 +1,598 @@
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/dts-v1/;
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#include "qcom-ipq4019.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/soc/qcom,tcsr.h>
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/ {
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model = "TRENDnet TEW-829DRU v1.0R";
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//model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK04.1-C1"; /* OEM line */
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compatible = "trendnet,tew-829dru", "qcom,ipq4019";
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aliases {
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label-mac-device = &gmac;
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led-boot = &led_wps;
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led-failsafe = &led_wps;
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led-running = &led_wps;
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led-upgrade = &led_wps;
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serial0 = &blsp1_uart2;
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ethernet0 = &gmac; /* Critical for MAC address inheritance on IPQ40xx */
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};
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chosen {
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bootargs = "console=ttyMSM0,115200n8 clk_ignore_unused";
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stdout-path = "serial0:115200n8";
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256MB */
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};
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cpus {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,arm-cortex-acc";
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reg = <0x00>;
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clocks = <0x02 0x09>;
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clock-frequency = <0x00>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,arm-cortex-acc";
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reg = <0x01>;
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clocks = <0x02 0x09>;
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clock-frequency = <0x00>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,arm-cortex-acc";
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reg = <0x02>;
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clocks = <0x02 0x09>;
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clock-frequency = <0x00>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,arm-cortex-acc";
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reg = <0x03>;
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clocks = <0x02 0x09>;
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clock-frequency = <0x00>;
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};
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ess_psgmii: psgmii@98000 {
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compatible = "qcom,ess-psgmii";
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reg = <0x98000 0x800>;
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psgmii_access_mode = "local bus";
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resets = <&gcc ESS_PSGMII_ARES>;
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reset-names = "psgmii_rst";
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};
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};
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/* --- Standard OpenWrt Method: Modify existing nodes from .dtsi --- */
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soc {
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mdio: mdio@90000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,ipq4019-mdio";
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reg = <0x90000 0x64>;
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status = "okay";
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};
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ess-switch@c000000 {
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compatible = "qcom,ipq4019-qca8337n";
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reg = <0xc000000 0x80000>, <0x98000 0x800>;
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reg-names = "base", "psgmii_phy";
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resets = <&gcc ESS_RESET>;
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reset-names = "ess_rst";
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clocks = <&gcc GCC_ESS_CLK>;
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clock-names = "ess_clk";
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switch_cpu_bmp = <0x1>;
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switch_lan_bmp = <0x1fe>;
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switch_mac_mode = <0>;
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psgmii-ethphy = <&psgmiiphy>;
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mdio = <&mdio>; /* ADD THIS LINE */
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status = "okay";
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};
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ess-psgmii@98000 {
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compatible = "qcom,ess-psgmii";
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reg = <0x98000 0x800>;
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status = "okay";
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};
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gmac: ethernet@c080000 {
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compatible = "qcom,ess-edma";
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reg = <0xc080000 0x8000>;
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qcom,mdio_supported;
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qcom,num_gmac = <2>;
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interrupts = <0 65 IRQ_TYPE_EDGE_RISING>, <0 66 IRQ_TYPE_EDGE_RISING>, <0 67 IRQ_TYPE_EDGE_RISING>, <0 68 IRQ_TYPE_EDGE_RISING>, <0 69 IRQ_TYPE_EDGE_RISING>, <0 70 IRQ_TYPE_EDGE_RISING>, <0 71 IRQ_TYPE_EDGE_RISING>, <0 72 IRQ_TYPE_EDGE_RISING>, <0 73 IRQ_TYPE_EDGE_RISING>, <0 74 IRQ_TYPE_EDGE_RISING>, <0 75 IRQ_TYPE_EDGE_RISING>, <0 76 IRQ_TYPE_EDGE_RISING>, <0 77 IRQ_TYPE_EDGE_RISING>, <0 78 IRQ_TYPE_EDGE_RISING>, <0 79 IRQ_TYPE_EDGE_RISING>, <0 80 IRQ_TYPE_EDGE_RISING>, <0 240 IRQ_TYPE_EDGE_RISING>, <0 241 IRQ_TYPE_EDGE_RISING>, <0 242 IRQ_TYPE_EDGE_RISING>, <0 243 IRQ_TYPE_EDGE_RISING>, <0 244 IRQ_TYPE_EDGE_RISING>, <0 245 IRQ_TYPE_EDGE_RISING>, <0 246 IRQ_TYPE_EDGE_RISING>, <0 247 IRQ_TYPE_EDGE_RISING>, <0 248 IRQ_TYPE_EDGE_RISING>, <0 249 IRQ_TYPE_EDGE_RISING>, <0 250 IRQ_TYPE_EDGE_RISING>, <0 251 IRQ_TYPE_EDGE_RISING>, <0 252 IRQ_TYPE_EDGE_RISING>, <0 253 IRQ_TYPE_EDGE_RISING>, <0 254 IRQ_TYPE_EDGE_RISING>, <0 255 IRQ_TYPE_EDGE_RISING>;
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status = "okay";
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gmac0: gmac0 {
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local-mac-address = [00 00 00 00 00 00];
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vlan_tag = <1 0x1fe>;
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};
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gmac1: gmac1 {
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local-mac-address = [00 00 00 00 00 00];
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vlan_tag = <2 0x20>;
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};
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};
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/* Wi-Fi Global Control */
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wifi_glb_tcsr: tcsr@1949000 {
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compatible = "qcom,tcsr";
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reg = <0x1949000 0x100>;
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qcom,wifi_glb_cfg = <0x41000000>; /* Add this line from OEM */
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};
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/* Wi-Fi NOC Memory Type */
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wifi_noc_memtype_m0_m2_tcsr: tcsr@1957000 {
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compatible = "qcom,tcsr";
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reg = <0x1957000 0x100>;
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qcom,wifi_noc_memtype_m0_m2 = <0x2222222>; /* Add this line from OEM */
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};
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/* Wi-Fi 0 (2.4GHz and 5GHz Low) */
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wifi0: wifi@a000000 {
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compatible = "qca,wifi-ipq40xx";
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reg = <0xa000000 0x200000>;
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core-id = <0>;
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/* Use symbolic references from ipq4019.dtsi */
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resets = <&gcc WIFI0_CPU_INIT_RESET>,
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<&gcc WIFI0_RADIO_SRIF_RESET>,
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<&gcc WIFI0_RADIO_WARM_RESET>,
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<&gcc WIFI0_RADIO_COLD_RESET>,
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<&gcc WIFI0_CORE_WARM_RESET>,
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<&gcc WIFI0_CORE_COLD_RESET>;
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reset-names = "wifi_cpu_init",
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"wifi_radio_srif",
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"wifi_radio_warm",
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"wifi_radio_cold",
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"wifi_core_warm",
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"wifi_core_cold";
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clocks = <&gcc GCC_WCSS2G_CLK>,
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<&gcc GCC_WCSS2G_REF_CLK>,
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<&gcc GCC_WCSS2G_RTC_CLK>;
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clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", "wifi_wcss_rtc";
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interrupts = <0 0x20 0x1>,
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<0 0x21 0x1>,
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<0 0x22 0x1>,
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<0 0x23 0x1>,
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<0 0x24 0x1>,
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<0 0x25 0x1>,
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<0 0x26 0x1>,
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<0 0x27 0x1>,
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<0 0x28 0x1>,
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<0 0x29 0x1>,
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<0 0x2a 0x1>,
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<0 0x2b 0x1>,
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<0 0x2c 0x1>,
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<0 0x2d 0x1>,
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<0 0x2e 0x1>,
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<0 0x2f 0x1>,
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<0 0xa8 0x0>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6",
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"msi7", "msi8", "msi9", "msi10", "msi11", "msi12", "msi13",
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"msi14", "msi15", "legacy";
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status = "okay";
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qca,msi_addr = <0xb006040>;
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qca,msi_base = <0x40>;
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wifi_led_num = <2>;
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wifi_led_source = <0>;
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};
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/* Wi-Fi 1 (5GHz High - QCA9984) */
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wifi1: wifi@a800000 {
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compatible = "qca,wifi-ipq40xx";
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reg = <0xa800000 0x200000>;
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core-id = <1>;
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resets = <&gcc WIFI1_CPU_INIT_RESET>,
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<&gcc WIFI1_RADIO_SRIF_RESET>,
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<&gcc WIFI1_RADIO_WARM_RESET>,
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<&gcc WIFI1_RADIO_COLD_RESET>,
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<&gcc WIFI1_CORE_WARM_RESET>,
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<&gcc WIFI1_CORE_COLD_RESET>;
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reset-names = "wifi_cpu_init",
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"wifi_radio_srif",
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"wifi_radio_warm",
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"wifi_radio_cold",
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"wifi_core_warm",
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"wifi_core_cold";
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clocks = <&gcc GCC_WCSS5G_CLK>,
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<&gcc GCC_WCSS5G_REF_CLK>,
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<&gcc GCC_WCSS5G_RTC_CLK>;
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clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", "wifi_wcss_rtc";
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interrupts = <0 0x30 0x1>,
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<0 0x31 0x1>,
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<0 0x32 0x1>,
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<0 0x33 0x1>,
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<0 0x34 0x1>,
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<0 0x35 0x1>,
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<0 0x36 0x1>,
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<0 0x37 0x1>,
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<0 0x38 0x1>,
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<0 0x39 0x1>,
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<0 0x3a 0x1>,
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<0 0x3b 0x1>,
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<0 0x3c 0x1>,
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<0 0x3d 0x1>,
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<0 0x3e 0x1>,
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<0 0x3f 0x1>,
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<0 0xa9 0x0>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6",
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"msi7", "msi8", "msi9", "msi10", "msi11", "msi12", "msi13",
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"msi14", "msi15", "legacy";
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status = "okay";
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qca,msi_addr = <0xb006040>;
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qca,msi_base = <0x50>;
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wifi_led_num = <1>;
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wifi_led_source = <2>;
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};
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};
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/* GPIO LEDs */
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leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&led_pins>;
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pinctrl-names = "default";
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led_wps: led-wps {
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label = "green:wps";
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gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "default-on";
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};
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led_2g: led-2g {
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label = "green:wlan2g";
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gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0tpt";
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};
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led_5g1: led-5g1 {
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label = "green:wlan5g1";
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gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1tpt";
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};
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led_5g2: led-5g2 {
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label = "green:wlan5g2";
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gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy2tpt";
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};
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};
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/* GPIO Buttons */
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keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&button_pins>;
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pinctrl-names = "default";
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button_reset: button-reset {
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label = "reset";
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gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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/* NAND Flash */
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&nand {
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status = "okay";
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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nandcs@0 {
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reg = <0>; /* Chip-select number */
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};
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* This is the single MTD partition that holds the entire UBI container */
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partition@800000 {
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label = "ubi";
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reg = <0x00800000 0x07800000>; /* Start after bootloader, use remaining space */
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};
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};
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};
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// QPIC BAM - req'd for nand
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&qpic_bam {
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status = "okay";
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qcom,ee = <0>;
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};
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/* PCIe for QCA9984 */
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&pcie0 {
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status = "okay";
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pinctrl-0 = <&pcie0_pins>;
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pinctrl-names = "default";
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reset-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
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};
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&blsp1_spi1 {
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status = "okay";
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <24000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition-art {
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label = "0:ART";
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_gmac0: macaddr@0 {
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reg = <0x0 0x6>;
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};
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macaddr_gmac1: macaddr@6 {
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reg = <0x6 0x6>;
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};
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precal_art_1000: precal@1000 {
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reg = <0x1000 0x2f20>;
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};
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precal_art_5000: precal@5000 {
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reg = <0x5000 0x2f20>;
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};
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precal_art_9000: precal@9000 {
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reg = <0x9000 0x2f20>;
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};
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};
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};
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};
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};
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};
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/* Serial Console */
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&blsp1_uart1 {
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pinctrl-0 = <&serial_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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/*&blsp1_uart2 {
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status = "okay";
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pinctrl-0 = <&serial_pins>;
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pinctrl-names = "default";
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>;
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clock-names = "core";
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resets = <&gcc GCC_BLSP1_UART2_BCR>;
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reset-names = "m";
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};*/
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/* Pinmux */
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&tlmm {
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/* SPI 0 Pinmux (from OEM) */
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spi_0_pins: spi_0_pinmux {
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mux {
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pins = "gpio12", "gpio13", "gpio14", "gpio15";
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function = "blsp_spi0";
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bias-disable;
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};
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};
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/* NAND Pinmux (standard for IPQ4019) */
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nand_pins: nand_pins {
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mux {
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pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
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"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15";
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function = "nand";
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drive-strength = <2>;
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bias-pull-up;
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};
|
||||
};
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||||
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/* PCIe 0 Pinmux (standard for IPQ4019) */
|
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pcie0_pins: pcie0_pins {
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mux {
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pins = "gpio61";
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function = "gpio";
|
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drive-strength = <2>;
|
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bias-pull-up;
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};
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||||
};
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||||
|
||||
/* MDIO pins - mind the wrapper (not the rapper) */
|
||||
mdio_pins: mdio-pinmux {
|
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mdc-pins {
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pins = "gpio52";
|
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function = "mdc";
|
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bias-pull-up;
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};
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mdio-pins {
|
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pins = "gpio53";
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function = "mdio";
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bias-pull-up;
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||||
};
|
||||
};
|
||||
|
||||
/* PSGMII pins */
|
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psgmii_pins: psgmii_pins {
|
||||
mux {
|
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pins = "gpio28", "gpio29", "gpio30", "gpio31",
|
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"gpio32", "gpio33", "gpio34", "gpio35",
|
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"gpio36", "gpio37", "gpio38", "gpio39";
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||||
function = "psgmii";
|
||||
};
|
||||
};
|
||||
|
||||
/* RGMII Pinmux for GMAC1 (QCA8337 Switch) */
|
||||
rgmii_pins: rgmii_pins {
|
||||
mux {
|
||||
pins = "gpio40", "gpio41", "gpio42", "gpio43",
|
||||
"gpio44", "gpio45", "gpio46", "gpio47",
|
||||
"gpio48", "gpio49", "gpio50", "gpio51";
|
||||
function = "rgmii";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
/* SGMII Pinmux for GMAC2 (LAN) */
|
||||
sgmii_pins: sgmii_pins {
|
||||
mux {
|
||||
pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45";
|
||||
function = "sgmii";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
/* UART Pinmux (from OEM) */
|
||||
serial_pins: serial0_pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
};
|
||||
|
||||
button_pins: button_pins {
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// LAN Ports (8) + WAN Ports (2) - Handled by IPQ4019 Internal GMACs
|
||||
&gmac {
|
||||
status = "okay";
|
||||
phy-mode = "internal";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
/* IPQ40xx typically requires specific delays for RGMII */
|
||||
tx-internal-delay-ps = <1000>;
|
||||
rx-internal-delay-ps = <1000>;
|
||||
|
||||
/* Connect to the first port of the switch node defined below */
|
||||
//nvmem-cells = <&macaddr_config_0>; /* Optional: if using nvmem for MAC */
|
||||
//nvmem-cell-names = "mac-address";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
// Ensure GMAC1 is enabled for RGMII
|
||||
&gmac1 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
tx-internal-delay-ps = <1000>;
|
||||
rx-internal-delay-ps = <1000>;
|
||||
/* Ensure clocks are enabled if your SoC DTSI doesn't do it by default */
|
||||
/* clocks = <&gcc GCC_GPSS0_CFG_AHB_CLK>, <&gcc GCC_GPSS0_CFG_M_CLK>, <&gcc GCC_GPSS0_CFG_SLAVE_M_CLK>; */
|
||||
|
||||
/* Do NOT put fixed-link here if the switch port defines it */
|
||||
};
|
||||
|
||||
// This node is OUTSIDE the 'soc' block
|
||||
// LAN Ports (8) - Handled by QCA8337
|
||||
// Enable the internal switch fabric
|
||||
// Define the primary QCA8337 switch
|
||||
&switch {
|
||||
status = "okay";
|
||||
compatible = "qca,qca8337";
|
||||
reset-gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* CPU Port: Connects to GMAC1 */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac1>;
|
||||
fixed-link { speed = <1000>; full-duplex; pause; };
|
||||
};
|
||||
|
||||
/* WAN and LAN Ports on QCA8337 */
|
||||
port@1 { reg = <1>; label = "wan2"; };
|
||||
port@2 { reg = <2>; label = "wan1"; };
|
||||
port@3 { reg = <3>; label = "lan1"; };
|
||||
port@4 { reg = <4>; label = "lan2"; };
|
||||
port@5 { reg = <5>; label = "lan3"; };
|
||||
|
||||
/* Port 6: Connects to the QCA8075 switch */
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac0>; /* Uses the second GMAC */
|
||||
fixed-link { speed = <1000>; full-duplex; pause; };
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
// Define the secondary QCA8075 switch
|
||||
&qca8075 {
|
||||
status = "okay";
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* CPU Port: Connects to QCA8337 port 6 */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac0>;
|
||||
fixed-link { speed = <1000>; full-duplex; pause; };
|
||||
};
|
||||
|
||||
/* LAN Ports on QCA8075 */
|
||||
port@1 { reg = <1>; label = "lan4"; };
|
||||
port@2 { reg = <2>; label = "lan5"; };
|
||||
port@3 { reg = <3>; label = "lan6"; };
|
||||
port@4 { reg = <4>; label = "lan7"; };
|
||||
port@5 { reg = <5>; label = "lan8"; };
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
||||
// Ensure the external MDIO bus is enabled for the QCA8075 WAN PHY (if present)
|
||||
&mdio {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
// Define the QCA8075 WAN PHY here if your board has one
|
||||
// phy0: ethernet-phy@0 { reg = <0>; compatible = "ethernet-phy-id004d.d0b1"; };
|
||||
// Ensure the external MDIO bus is enabled
|
||||
//psgmiiphy: psgmii-phy@5 {
|
||||
// reg = <5>;
|
||||
//};
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user