Backport a patch fixing the error return check when loading PSE PIs from
the DT tree in case the pairset property isn't specified.
This patch might be backported upstream in stable.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23449
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the patch version accepted upstream and move it to backports dir.
Signed-off-by: Qingfang Deng <dqfext@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23438
Signed-off-by: Robert Marko <robimarko@gmail.com>
While implementing standalone PCS support for DSA, it was found that making
the MAC driver passing the available_pcs array is limiting and problematic
for memory handling and allocation. To better handle this, change the logic
and make phylink allocate the struct and make the MAC driver implement a
function in phylink_config .fill_available_pcs to fill the PCS array.
Update the Airoha and Mediatek driver to reflect this new implementation.
Link: https://github.com/openwrt/openwrt/pull/23413
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The name “aes-lib” is used since kernel 7.0. In kernels 6.12 and 6.18,
the name “aes-generic” is used. This change makes it possible to run
comparative selftests of the generic and hardware implementations.
This will help identify any potential differences in the results.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/23392
Signed-off-by: Robert Marko <robimarko@gmail.com>
Replace patch with upstream version.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/23392
Signed-off-by: Robert Marko <robimarko@gmail.com>
The current code permits support of the standalone PCS feature only for
in-tree kernel module but doesn't correctly support PCS from external
kernel module.
This is caused by the fact that the FWNODE_PCS config flag is internally
selected by any PCS driver and can't be selected directly. This is
problematic for any external kernel module that wants to use the standalone
PCS feature and needs the OPs provided by the generic PCS code.
Moreover compiling the standalone PCS code as a module is problematic and
would cause link error caused by the late PCS code that introduce a
notifier where phylink code depends on.
To address both problem, permit to select the FWNODE_PCS and change it to a
simple bool preventing it to compile as a module.
Link: https://github.com/openwrt/openwrt/pull/23349
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK macro was shifting
the 4-bit mask (0xF) by only (_extint % 2) bits instead of
(_extint % 2) * 4. This caused the mask to overlap with the adjacent
nibble when configuring odd-numbered external interfaces, selecting
the wrong bits entirely.
Align the shift calculation with the existing ...MODE_OFFSET macro.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/23285
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add chip info entry for the Realtek RTL8367SB switch. This device has
chip ID 0x6367 and version 0x0010. It exposes two external interfaces:
port 6 supports MII, TMII, RMII, RGMII, SGMII and HSGMII, while port 7
supports MII, TMII, RMII and RGMII. Use the existing 8365MB-VC jam table
for initialization.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/23345
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport pending PCS standalone feature for kernel 6.12 and all the
required dependency patch.
All affected patch automatically refreshed.
Link: https://github.com/openwrt/openwrt/pull/23271
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport phylink_replay_link() API patch from upstream kernel. This is
mostly needed for force_major_config bool in phylink struct needed for new
standalone PCS series.
While at it also rename the current 703 patch to 703-01 as it's part of the
same series merged upstream.
All patch automatically refreshed.
Link: https://github.com/openwrt/openwrt/pull/23271
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Enable static key (jump label) on all supported architectures. This
lowers overhead and stress on the branch prediction of the CPU and
generally makes the kernel faster.
Signed-off-by: Qingfang Deng <dqfext@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23073
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
These are all unused by the current targets, clean up and stop
irritating the user with irrelevant grep results.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23240
Signed-off-by: Robert Marko <robimarko@gmail.com>
The Kconfig symbol help text prompts:
Disable this to get a possibly more secure configuration, but that
might not be backward compatible with previous kernels.
If backward compatibility is not an issue, then it is safe and
recommended to say N here.
For OpenWrt, when updating firmware, we always update the kernel and
recreate the overlay partition. Therefore, compatibility is not a
problem.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/23126
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
FIPS 140-3 recommends that all crypto implementations should be tested
before first use. Testmanager performs initial tests based on existing
test vectors. Not all algorithms have defined test vectors, so to improve
this situation, this commit backports recently added test vectors for
some cipher suites.
These vectors were calculated using a software implementation and then
double-checked on Mediatek MT7981 (safexcel) and NXP P2020 (talitos).
Both platforms passed self-tests.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/23012
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add patches to improve support for using 3rd-party DSA switches
like MaxLinear MxL862xx with MediaTek's mtk_eth_soc being the
conduit. This involves reorganizing hardware queues to avoid
overlap (currently dp->index is used -- if there is more than one
DSA switch this is problematic), and correctly programming flows
of the non-MTK DSA users ports in the PPE offloading engine.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
LINK_INBAND_ENABLE isn't valid for 5GBase-R/10GBase-R modes which
by definition don't support any in-band an. Correctly report
LINK_INBAND_DISABLE to fix 10G fiber SFP modules no longer working.
While at it also get rid of downstream pn-swap properties in favor
of using the upstream schema.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Currently, the DesignWare PCIe driver cannot configure interrupts on
SoC that do not support MSIX. All MSI interrupts are handled by CPU0.
Backport MSI affinity support for the PCI dwc driver from linux-next,
so now we can adjust MSI interrupts to other CPU cores.
Tested on HINLINK H28K (RK3528) and OrangePi R2S (Ky X1).
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/21770
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport support for the RTL8157. The RTL8157 is a low-cost chipset
designed for USB to 5Gb Ethernet adapters.
Tested on Sabrent NT-C5GA (RTL8157), Wavlink WL-NWU340G (RTL8157) and
UGREEN CM648 (RTL8156BG) adapters.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/23088
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
At least the XikeStor SKT-2.5G-100M SFP module seems to internally use
MDIO address 0 to access the PHY. This module allows accessing PHY
registers using Rollball protocol on address 0x51, and also provides
read-only C22 access on address 0x56. However, after disabling the
PHYAD0 configuration bit, only 0xffff can be read via both methods
(except for MMD device 30 which can still be accessed).
Since having MDIO address 0 enabled shouldn't do any harm on SFP modules
just leave the configuration bit alone in that case.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/23065
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
After the RTL8261N asserts a reset, the MDIO bus becomes temporarily
unavailable during the chip's reinitialization sequence. Any subsequent
read or write issued before the PHY has stabilized will fail.
Add a 30ms delay after triggering the reset to ensure the chip is reachable
via MDIO before resuming communication.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/23076
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
In the past, all the configuration of SerDes and PHYs on the realtek
switches were done using u-boot (`rtk init`). But since RTL930x switched
to SerDes configuration under Linux, the SoC side is no longer using the
Realtek-proprietary variant of USXGMII. The communication to the RTL8261N
PHYs on those switches broke because of this incompatibility.
Enabling the full initialization on `CONFIG_MACH_REALTEK_RTL` converts also
the PHY side to the standard USXGMII and therefore ensures that both sides
speak the same dialect.
Co-authored-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/23076
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The PHY register patch in question is gated by `CONFIG_MACH_REALTEK_RTL`,
has no documented/expected behavior, and is in practice unreachable:
`phy_patch()` is only called from `rtkphy_config_init()`, which is exits
(too) early for `CONFIG_MACH_REALTEK_RTL` builds.
Remove it as a cleanup step before enabling standard USXGMII configuration
for these PHYs.
Fixes: b77fa45d12 ("kernel: fix rtl8261n driver for realtek")
Co-authored-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/23076
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
