// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

&mdio_bus0 {
	PHY_C22(0, 0)
	PHY_C22(1, 1)
	PHY_C22(2, 2)
	PHY_C22(3, 3)
	PHY_C22(4, 4)
	PHY_C22(5, 5)
	PHY_C22(6, 6)
	PHY_C22(7, 7)

	PHY_C22(8, 8)
	PHY_C22(9, 9)
	PHY_C22(10, 10)
	PHY_C22(11, 11)
	PHY_C22(12, 12)
	PHY_C22(13, 13)
	PHY_C22(14, 14)
	PHY_C22(15, 15)

	PHY_C22(16, 16)
	PHY_C22(17, 17)
	PHY_C22(18, 18)
	PHY_C22(19, 19)
	PHY_C22(20, 20)
	PHY_C22(21, 21)
	PHY_C22(22, 22)
	PHY_C22(23, 23)

	/* External phy RTL8214FC */
	PHY_C22_SFP(24, 24, 0)
	PHY_C22_SFP(25, 25, 1)
	PHY_C22_SFP(26, 26, 2)
	PHY_C22_SFP(27, 27, 3)
};

&switch0 {
	ethernet-ports {
		#address-cells = <1>;
		#size-cells = <0>;

		SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
		SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
		SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
		SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
		SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
		SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
		SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
		SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)

		SWITCH_PORT(8, 9, internal)
		SWITCH_PORT(9, 10, internal)
		SWITCH_PORT(10, 11, internal)
		SWITCH_PORT(11, 12, internal)
		SWITCH_PORT(12, 13, internal)
		SWITCH_PORT(13, 14, internal)
		SWITCH_PORT(14, 15, internal)
		SWITCH_PORT(15, 16, internal)

		SWITCH_PORT_SDS(16, 17, 2, 0, qsgmii)
		SWITCH_PORT_SDS(17, 18, 2, 1, qsgmii)
		SWITCH_PORT_SDS(18, 19, 2, 2, qsgmii)
		SWITCH_PORT_SDS(19, 20, 2, 3, qsgmii)
		SWITCH_PORT_SDS(20, 21, 3, 0, qsgmii)
		SWITCH_PORT_SDS(21, 22, 3, 1, qsgmii)
		SWITCH_PORT_SDS(22, 23, 3, 2, qsgmii)
		SWITCH_PORT_SDS(23, 24, 3, 3, qsgmii)

		SWITCH_PORT_SDS(24, 25, 4, 0, qsgmii)
		SWITCH_PORT_SDS(25, 26, 4, 1, qsgmii)
		SWITCH_PORT_SDS(26, 27, 4, 2, qsgmii)
		SWITCH_PORT_SDS(27, 28, 4, 3, qsgmii)

		port@28 {
			ethernet = <&ethernet0>;
			reg = <28>;
			phy-mode = "internal";
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};