// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include "rtl838x.dtsi"

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	compatible = "inaba,aml2-17gp", "realtek,rtl838x-soc";
	model = "INABA Abaniact AML2-17GP";

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x8000000>;
	};

	keys {
		pinctrl-names = "default";
		pinctrl-0 = <&pinmux_disable_sys_led>;

		compatible = "gpio-keys";

		reset {
			label = "reset";
			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x80000>;
				read-only;
			};

			partition@80000 {
				label = "u-boot-env";
				reg = <0x80000 0x10000>;
				read-only;
			};

			partition@90000 {
				label = "u-boot-env2";
				reg = <0x90000 0x10000>;
			};

			partition@a0000 {
				label = "jffs2_cfg";
				reg = <0xa0000 0x400000>;
				read-only;
			};

			partition@4a0000 {
				label = "jffs2_log";
				reg = <0x4a0000 0x100000>;
				read-only;
			};

			partition@5a0000 {
				compatible = "openwrt,uimage", "denx,uimage";
				label = "firmware";
				reg = <0x5a0000 0xd30000>;
				openwrt,ih-magic = <0x83800000>;
			};

			partition@12d0000 {
				label = "runtime2";
				reg = <0x12d0000 0xd30000>;
			};
		};
	};
};

&mdio_bus0 {
	PHY_C22(8, 8)
	PHY_C22(9, 9)
	PHY_C22(10, 10)
	PHY_C22(11, 11)
	PHY_C22(12, 12)
	PHY_C22(13, 13)
	PHY_C22(14, 14)
	PHY_C22(15, 15)

	PHY_C22(16, 16)
	PHY_C22(17, 17)
	PHY_C22(18, 18)
	PHY_C22(19, 19)
	PHY_C22(20, 20)
	PHY_C22(21, 21)
	PHY_C22(22, 22)
	PHY_C22(23, 23)

	PHY_C22(24, 24)
};

&switch0 {
	ethernet-ports {
		#address-cells = <1>;
		#size-cells = <0>;

		SWITCH_PORT(8, 1, internal)
		SWITCH_PORT(9, 2, internal)
		SWITCH_PORT(10, 3, internal)
		SWITCH_PORT(11, 4, internal)
		SWITCH_PORT(12, 5, internal)
		SWITCH_PORT(13, 6, internal)
		SWITCH_PORT(14, 7, internal)
		SWITCH_PORT(15, 8, internal)

		SWITCH_PORT_SDS(16, 9, 2, 0, qsgmii)
		SWITCH_PORT_SDS(17, 10, 2, 1, qsgmii)
		SWITCH_PORT_SDS(18, 11, 2, 2, qsgmii)
		SWITCH_PORT_SDS(19, 12, 2, 3, qsgmii)
		SWITCH_PORT_SDS(20, 13, 3, 0, qsgmii)
		SWITCH_PORT_SDS(21, 14, 3, 1, qsgmii)
		SWITCH_PORT_SDS(22, 15, 3, 2, qsgmii)
		SWITCH_PORT_SDS(23, 16, 3, 3, qsgmii)

		port@24 {
			reg = <24>;
			label = "wan";
			phy-handle = <&phy24>;
			phy-mode = "qsgmii";
		};

		port@28 {
			ethernet = <&ethernet0>;
			reg = <28>;
			phy-mode = "internal";

			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};