// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include "rtl838x.dtsi"

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>

/ {
	compatible = "tplink,t1600g-28ts-v3", "realtek,rtl838x-soc";
	model = "TP-Link T1600G-28TS v3";

	aliases {
		led-boot = &led_sys;
		led-failsafe = &led_sys;
		led-running = &led_sys;
		led-upgrade = &led_sys;
		label-mac-device = &ethernet0;
	};

	chosen {
		stdout-path = "serial0:38400n8";
	};

	leds {
		pinctrl-names = "default";
		compatible = "gpio-leds";

		led_sys: led-0 {
			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_GREEN>;
			function = LED_FUNCTION_STATUS;
		};
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x10000000>;
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0xe0000>;
				read-only;
			};
			partition@e0000 {
				label = "u-boot-env";
				reg = <0xe0000 0x20000>;
			};
			partition@100000 {
				compatible = "denx,uimage";
				label = "firmware";
				reg = <0x100000 0x1a00000>;
			};
			partition@1b00000 {
				label = "usrappfs";
				reg = <0x1b00000 0x400000>;
			};
			partition@1f00000 {
				label = "para";
				reg = <0x1f00000 0x100000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					factory_macaddr: macaddr@fdff4 {
						reg = <0xfdff4 0x6>;
					};
				};
			};
		};
	};
};

&ethernet0 {
	nvmem-cells = <&factory_macaddr>;
	nvmem-cell-names = "mac-address";
};

&mdio_bus0 {
	PHY_C22(0, 0)
	PHY_C22(1, 1)
	PHY_C22(2, 2)
	PHY_C22(3, 3)
	PHY_C22(4, 4)
	PHY_C22(5, 5)
	PHY_C22(6, 6)
	PHY_C22(7, 7)

	PHY_C22(8, 8)
	PHY_C22(9, 9)
	PHY_C22(10, 10)
	PHY_C22(11, 11)
	PHY_C22(12, 12)
	PHY_C22(13, 13)
	PHY_C22(14, 14)
	PHY_C22(15, 15)

	PHY_C22(16, 16)
	PHY_C22(17, 17)
	PHY_C22(18, 18)
	PHY_C22(19, 19)
	PHY_C22(20, 20)
	PHY_C22(21, 21)
	PHY_C22(22, 22)
	PHY_C22(23, 23)
};

&switch0 {
	ethernet-ports {
		#address-cells = <1>;
		#size-cells = <0>;

		SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
		SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
		SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
		SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
		SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
		SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
		SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
		SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)

		SWITCH_PORT(8, 9, internal)
		SWITCH_PORT(9, 10, internal)
		SWITCH_PORT(10, 11, internal)
		SWITCH_PORT(11, 12, internal)
		SWITCH_PORT(12, 13, internal)
		SWITCH_PORT(13, 14, internal)
		SWITCH_PORT(14, 15, internal)
		SWITCH_PORT(15, 16, internal)

		SWITCH_PORT_SDS(16, 17, 2, 0, qsgmii)
		SWITCH_PORT_SDS(17, 18, 2, 1, qsgmii)
		SWITCH_PORT_SDS(18, 19, 2, 2, qsgmii)
		SWITCH_PORT_SDS(19, 20, 2, 3, qsgmii)
		SWITCH_PORT_SDS(20, 21, 3, 0, qsgmii)
		SWITCH_PORT_SDS(21, 22, 3, 1, qsgmii)
		SWITCH_PORT_SDS(22, 23, 3, 2, qsgmii)
		SWITCH_PORT_SDS(23, 24, 3, 3, qsgmii)

		port@28 {
			ethernet = <&ethernet0>;
			reg = <28>;
			phy-mode = "internal";

			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};