// SPDX-License-Identifier: GPL-2.0-or-later

#include "rtl8380_zyxel_gs1900.dtsi"
#include "rtl8380_zyxel_gs1900_gpio.dtsi"

/ {
	compatible = "zyxel,gs1900-24e-a1", "realtek,rtl838x-soc";
	model = "Zyxel GS1900-24E A1";
};

&gpio0 {
	/* Shared between the main and aux MDIO busses */
	mdio_reset {
		gpio-hog;
		gpios = <1 GPIO_ACTIVE_LOW>;
		output-low;
		line-name = "mdio-reset";
	};
};

&mdio_bus0 {
	PHY_C22(0, 0)
	PHY_C22(1, 1)
	PHY_C22(2, 2)
	PHY_C22(3, 3)
	PHY_C22(4, 4)
	PHY_C22(5, 5)
	PHY_C22(6, 6)
	PHY_C22(7, 7)

	PHY_C22(16, 16)
	PHY_C22(17, 17)
	PHY_C22(18, 18)
	PHY_C22(19, 19)
	PHY_C22(20, 20)
	PHY_C22(21, 21)
	PHY_C22(22, 22)
	PHY_C22(23, 23)
};

&switch0 {
	ethernet-ports {
		SWITCH_PORT_SDS(1, 1, 0, 1, qsgmii)
		SWITCH_PORT_SDS(0, 2, 0, 0, qsgmii)
		SWITCH_PORT_SDS(3, 3, 0, 3, qsgmii)
		SWITCH_PORT_SDS(2, 4, 0, 2, qsgmii)
		SWITCH_PORT_SDS(5, 5, 1, 1, qsgmii)
		SWITCH_PORT_SDS(4, 6, 1, 0, qsgmii)
		SWITCH_PORT_SDS(7, 7, 1, 3, qsgmii)
		SWITCH_PORT_SDS(6, 8, 1, 2, qsgmii)

		SWITCH_PORT(9, 9, internal)
		SWITCH_PORT(8, 10, internal)
		SWITCH_PORT(11, 11, internal)
		SWITCH_PORT(10, 12, internal)
		SWITCH_PORT(13, 13, internal)
		SWITCH_PORT(12, 14, internal)
		SWITCH_PORT(15, 15, internal)
		SWITCH_PORT(14, 16, internal)

		SWITCH_PORT_SDS(17, 17, 2, 1, qsgmii)
		SWITCH_PORT_SDS(16, 18, 2, 0, qsgmii)
		SWITCH_PORT_SDS(19, 19, 2, 3, qsgmii)
		SWITCH_PORT_SDS(18, 20, 2, 2, qsgmii)
		SWITCH_PORT_SDS(21, 21, 3, 1, qsgmii)
		SWITCH_PORT_SDS(20, 22, 3, 0, qsgmii)
		SWITCH_PORT_SDS(23, 23, 3, 3, qsgmii)
		SWITCH_PORT_SDS(22, 24, 3, 2, qsgmii)
	};
};

&gpio1 {
	/delete-node/ poe_enable;
};