/dts-v1/;

#include "rtl839x.dtsi"

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>

/ {
	aliases {
		led-boot = &led_sys;
		led-failsafe = &led_sys;
		led-running = &led_sys;
		led-upgrade = &led_sys;
	};

	leds {
		pinctrl-names = "default";
		pinctrl-0 = <&pinmux_disable_sys_led>;
		compatible = "gpio-leds";

		led_sys: sys {
			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
		};

		locator {
			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
			function = LED_FUNCTION_INDICATOR;
			color = <LED_COLOR_ID_BLUE>;
		};
	};

	/* i2c of port 25 SFP cage */
	i2c0: i2c-gpio-0 {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		i2c-gpio,delay-us = <2>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	sfp0: sfp-p25 {
		compatible = "sff,sfp";
		i2c-bus = <&i2c0>;
		los-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&gpio0 23 GPIO_ACTIVE_LOW>;
		tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
	};

	/* i2c of port 26 SFP cage */
	i2c1: i2c-gpio-1 {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio1 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio1 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		i2c-gpio,delay-us = <2>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	sfp1: sfp-p26 {
		compatible = "sff,sfp";
		i2c-bus = <&i2c1>;
		los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&gpio0 17 GPIO_ACTIVE_LOW>;
		tx-fault-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
	};

	/* i2c of port 27 SFP cage */
	i2c2: i2c-gpio-2 {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		i2c-gpio,delay-us = <2>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	sfp2: sfp-p27 {
		compatible = "sff,sfp";
		i2c-bus = <&i2c2>;
		los-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&gpio0 13 GPIO_ACTIVE_LOW>;
		tx-fault-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
	};

	/* i2c of port 28 SFP cage */
	i2c3: i2c-gpio-3 {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		i2c-gpio,delay-us = <2>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	sfp3: sfp-p28 {
		compatible = "sff,sfp";
		i2c-bus = <&i2c3>;
		los-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&gpio0 20 GPIO_ACTIVE_LOW>;
		tx-fault-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
	};

	/* i2c for hwmon/PoE */
	i2c4: i2c-gpio-4 {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio0 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		i2c-gpio,delay-us = <2>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
};

&spi0 {
	status = "okay";
	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		flash_partitions: partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "bootbase";
				reg = <0x0 0x20000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					factory_macaddr: macaddr@1fff8 {
						reg = <0x1fff8 0x6>;
					};
				};
			};
		};
	};
};

&ethernet0 {
	nvmem-cells = <&factory_macaddr>;
	nvmem-cell-names = "mac-address";
};

&mdio_bus0 {
	/* External phy RTL8218B #1 */
	PHY_C22(0, 0)
	PHY_C22(1, 1)
	PHY_C22(2, 2)
	PHY_C22(3, 3)
	PHY_C22(4, 4)
	PHY_C22(5, 5)
	PHY_C22(6, 6)
	PHY_C22(7, 7)

	/* External phy RTL8218B #2 */
	PHY_C22(8, 8)
	PHY_C22(9, 9)
	PHY_C22(10, 10)
	PHY_C22(11, 11)
	PHY_C22(12, 12)
	PHY_C22(13, 13)
	PHY_C22(14, 14)
	PHY_C22(15, 15)

	/* External phy RTL8218B #3 */
	PHY_C22(16, 16)
	PHY_C22(17, 17)
	PHY_C22(18, 18)
	PHY_C22(19, 19)
	PHY_C22(20, 20)
	PHY_C22(21, 21)
	PHY_C22(22, 22)
	PHY_C22(23, 23)
};

&switch0 {
	ethernet-ports {
		#address-cells = <1>;
		#size-cells = <0>;

		SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
		SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
		SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
		SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
		SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
		SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
		SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
		SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)

		SWITCH_PORT_SDS(8, 9, 2, 0, qsgmii)
		SWITCH_PORT_SDS(9, 10, 2, 1, qsgmii)
		SWITCH_PORT_SDS(10, 11, 2, 2, qsgmii)
		SWITCH_PORT_SDS(11, 12, 2, 3, qsgmii)
		SWITCH_PORT_SDS(12, 13, 3, 0, qsgmii)
		SWITCH_PORT_SDS(13, 14, 3, 1, qsgmii)
		SWITCH_PORT_SDS(14, 15, 3, 2, qsgmii)
		SWITCH_PORT_SDS(15, 16, 3, 3, qsgmii)

		SWITCH_PORT_SDS(16, 17, 4, 0, qsgmii)
		SWITCH_PORT_SDS(17, 18, 4, 1, qsgmii)
		SWITCH_PORT_SDS(18, 19, 4, 2, qsgmii)
		SWITCH_PORT_SDS(19, 20, 4, 3, qsgmii)
		SWITCH_PORT_SDS(20, 21, 5, 0, qsgmii)
		SWITCH_PORT_SDS(21, 22, 5, 1, qsgmii)
		SWITCH_PORT_SDS(22, 23, 5, 2, qsgmii)
		SWITCH_PORT_SDS(23, 24, 5, 3, qsgmii)

		/* CPU-Port */
		port@52 {
			ethernet = <&ethernet0>;
			reg = <52>;
			phy-mode = "internal";
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};

&mdio_aux {
	status = "okay";

	gpio1: expander@3 {
		compatible = "realtek,rtl8231";
		reg = <3>;

		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&gpio1 0 0 37>;

		led-controller {
			compatible = "realtek,rtl8231-leds";
			status = "disabled";
		};
	};
};