From 112c6ea7ac356dab16e11084f2183e653a289e91 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Tue, 28 Oct 2025 12:35:41 +0100 Subject: [PATCH 10/10] PCI: mediatek-gen3: set PHY mode for Airoha EN7581 For the Airoha EN7581 SoC, the 3rd PCIe line is attached to a special PHY that can be both used for USB 3.0 operation or PCIe. Configure the PHY for PCIe operation before init it to correctly configure the SCU Serdes register. This permits correct functionality and enumeration of PCIe devices on the 3rd PCIe line present on the SoC. Signed-off-by: Christian Marangi --- drivers/pci/controller/pcie-mediatek-gen3.c | 6 ++++++ 1 file changed, 6 insertions(+) --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -969,6 +969,12 @@ static int mtk_pcie_en7581_power_up(stru size = lower_32_bits(resource_size(entry->res)); regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); + err = phy_set_mode(pcie->phy, PHY_MODE_PCIE); + if (err) { + dev_err(dev, "failed to set PHY mode\n"); + return err; + } + /* * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 * requires PHY initialization and power-on before PHY reset deassert.