3e7aa18a4e
Manually refresh patches: - 0004-spi-spl022-Get-and-deassert-reset-in-probe.patch - 0007-driver-mailbox-Add-mailbox-driver.patch - 0009-uart-8250-Add-dw-auto-flow-ctrl-support.patch - 0013-drivers-nvme-Add-precheck-and-delay-for-CQE-pending-.patch - 0014-riscv-Optimize-memcpy-with-aligned-version.patch Signed-off-by: Zhihao Xu <ngc7331@outlook.com>
99 lines
3.1 KiB
Diff
99 lines
3.1 KiB
Diff
From 20c14bbdff9e3be2ddbeffa266f08bae04216e63 Mon Sep 17 00:00:00 2001
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From: Minda Chen <minda.chen@starfivetech.com>
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Date: Sun, 25 Jun 2023 09:40:29 +0800
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Subject: [PATCH 09/55] uart: 8250: Add dw auto flow ctrl support
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Add designeware 8250 auto flow ctrl support. Enable
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it by add auto-flow-control in dts.
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Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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---
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drivers/tty/serial/8250/8250_core.c | 2 ++
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drivers/tty/serial/8250/8250_dw.c | 3 +++
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drivers/tty/serial/8250/8250_port.c | 14 +++++++++++++-
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include/linux/serial_8250.h | 1 +
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include/uapi/linux/serial_core.h | 2 ++
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5 files changed, 21 insertions(+), 1 deletion(-)
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--- a/drivers/tty/serial/8250/8250_core.c
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+++ b/drivers/tty/serial/8250/8250_core.c
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@@ -804,6 +804,8 @@ int serial8250_register_8250_port(const
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uart->dl_read = up->dl_read;
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if (up->dl_write)
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uart->dl_write = up->dl_write;
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+ if (up->probe)
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+ uart->probe = up->probe;
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/* Check the type (again)! It might have changed by the port.type assignment above. */
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if (uart->port.type != PORT_8250_CIR) {
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--- a/drivers/tty/serial/8250/8250_dw.c
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+++ b/drivers/tty/serial/8250/8250_dw.c
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@@ -775,6 +775,9 @@ static int dw8250_probe(struct platform_
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data->msr_mask_off |= UART_MSR_TERI;
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}
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+ if (device_property_read_bool(dev, "auto-flow-control"))
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+ up->probe |= UART_PROBE_AFE;
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+
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/* If there is separate baudclk, get the rate from it. */
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data->clk = devm_clk_get_optional_enabled(dev, "baudclk");
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if (data->clk == NULL)
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--- a/drivers/tty/serial/8250/8250_port.c
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+++ b/drivers/tty/serial/8250/8250_port.c
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@@ -311,6 +311,14 @@ static const struct serial8250_config ua
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.rxtrig_bytes = {1, 8, 16, 30},
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.flags = UART_CAP_FIFO | UART_CAP_AFE,
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},
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+ [PORT_16550A_AFE] = {
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+ .name = "16550A_AFE",
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+ .fifo_size = 16,
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+ .tx_loadsz = 16,
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+ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
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+ .rxtrig_bytes = {1, 4, 8, 14},
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+ .flags = UART_CAP_FIFO | UART_CAP_AFE,
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+ },
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};
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/* Uart divisor latch read */
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@@ -1057,6 +1065,11 @@ static void autoconfig_16550a(struct uar
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up->port.type = PORT_U6_16550A;
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up->capabilities |= UART_CAP_AFE;
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}
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+
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+ if ((up->port.type == PORT_16550A) && (up->probe & UART_PROBE_AFE)) {
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+ up->port.type = PORT_16550A_AFE;
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+ up->capabilities |= UART_CAP_AFE;
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+ }
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}
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/*
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@@ -2565,7 +2578,6 @@ static unsigned int serial8250_get_baud_
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min = port->uartclk / 16 / UART_DIV_MAX;
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max = (port->uartclk + tolerance) / 16;
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}
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-
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/*
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* Ask the core to calculate the divisor for us.
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* Allow 1% tolerance at the upper limit so uart clks marginally
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--- a/include/linux/serial_8250.h
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+++ b/include/linux/serial_8250.h
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@@ -141,6 +141,7 @@ struct uart_8250_port {
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unsigned char probe;
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struct mctrl_gpios *gpios;
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#define UART_PROBE_RSA (1 << 0)
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+#define UART_PROBE_AFE (1 << 1)
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/*
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* Some bits in registers are cleared on a read, so they must
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--- a/include/uapi/linux/serial_core.h
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+++ b/include/uapi/linux/serial_core.h
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@@ -231,6 +231,8 @@
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/* Sunplus UART */
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#define PORT_SUNPLUS 123
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+#define PORT_16550A_AFE 124
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+
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/* Generic type identifier for ports which type is not important to userspace. */
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#define PORT_GENERIC (-1)
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