0c50884201
XS1930-10 and XS1930-12HP share most of their layout: the same 8-port AQR813 Base-T block, the same SFP+ GPIO mux, identical I2C master config and serdes polarity. Carve those shared pieces out into a new intermediate rtl9313_zyxel_xs1930-aqr813.dtsi and have both device DTS files include it, leaving only their device-specific differences (LED-set masks, extra PoE bits on -12HP, extra AQR113C PHYs on -12HP) in the per-device files. XS1930-12F continues to include the common DTSI directly since its layout differs too much to share usefully. Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/23428 Signed-off-by: Robert Marko <robimarko@gmail.com>
92 lines
1.8 KiB
Plaintext
92 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl9313_zyxel_xs1930-aqr813.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/mux/mux.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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compatible = "zyxel,xs1930-12hp", "realtek,rtl9313-soc";
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model = "Zyxel XS1930-12HP";
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};
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&led_set {
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/* Phantom port chain padding (2 LEDs) */
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led_set1 = <RTL93XX_LED_SET_NONE
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RTL93XX_LED_SET_NONE>;
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/* The LED PCB has two daisy-chained RTL8231 in scan mode.
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* Net LEDs for P3-P12 are on the first RTL8231, P1/P2
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* net LEDs are on the second. The 12 real ports provide
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* 36 LED bits but the chain requires 65 bits to correctly
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* span both chips. Phantom ports 1-7, 9-10 (set0, 3 LEDs
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* each) and port 11 (set1, 2 LEDs) pad the chain with
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* the remaining 29 bits.
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*/
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realtek,led-set0-force-port-mask = <0x00000000 0x000006FE>;
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realtek,led-set1-force-port-mask = <0x00000000 0x00000800>;
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};
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&gpio0 {
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poe_enable_hog {
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gpio-hog;
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gpios = <10 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "poe-enable";
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};
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};
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&i2c_mst1 {
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/* PoE management MCU sits here */
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i2c3: i2c@3 {
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reg = <3>;
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};
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};
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&mdio_ctrl {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_enable_mdc_mdio_0>,
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<&pinmux_enable_mdc_mdio_1>,
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<&pinmux_enable_mdc_mdio_2>;
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};
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&mdio_bus1 {
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PHY_C45(52, 0) /* AQR113C */
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};
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&mdio_bus2 {
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PHY_C45(53, 8) /* AQR113C */
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};
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&switch0 {
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ethernet-ports {
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/* Copper ports behind AQR113C */
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SWITCH_PORT_LED(52, 9, 10, 0, usxgmii)
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SWITCH_PORT_LED(53, 10, 11, 0, usxgmii)
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SWITCH_PORT_SFP(54, 11, 12, 0, 1)
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SWITCH_PORT_SFP(55, 12, 13, 0, 2)
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};
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};
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&port52 {
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managed = "in-band-status";
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};
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&port53 {
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managed = "in-band-status";
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};
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&serdes10 {
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tx-polarity = <PHY_POL_INVERT>;
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};
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&serdes11 {
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tx-polarity = <PHY_POL_INVERT>;
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};
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