0efbee297a
Create the config and relevant patches for 6.18 from 6.12. The "standard" openwrt devel process seems to be to move the files and restore the old ones. I find this process confusing, and I don't see any git benefits for doing things this way. So just copy the files. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21506 Signed-off-by: Robert Marko <robimarko@gmail.com>
45 lines
1.9 KiB
Diff
45 lines
1.9 KiB
Diff
From 2f2f5ae4d52ea882ba58f6b2fa6373a3d3db2bce Mon Sep 17 00:00:00 2001
|
|
From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
|
|
Date: Thu, 13 Mar 2025 12:44:22 +0530
|
|
Subject: [PATCH] arm64: dts: qcom: ipq9574: fix the msi interrupt numbers of
|
|
pcie3
|
|
|
|
The MSI interrupt numbers of the PCIe3 controller are incorrect. Due
|
|
to this, the functional bring up of the QDSP6 processor on the PCIe
|
|
endpoint has failed. Correct the MSI interrupt numbers to properly
|
|
bring up the QDSP6 processor on the PCIe endpoint.
|
|
|
|
Fixes: d80c7fbfa908 ("arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes")
|
|
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
|
|
Link: https://lore.kernel.org/r/20250313071422.510-1-quic_mmanikan@quicinc.com
|
|
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
---
|
|
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 16 ++++++++--------
|
|
1 file changed, 8 insertions(+), 8 deletions(-)
|
|
|
|
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
|
|
@@ -974,14 +974,14 @@
|
|
ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>;
|
|
|
|
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0",
|
|
"msi1",
|
|
"msi2",
|