0efbee297a
Create the config and relevant patches for 6.18 from 6.12. The "standard" openwrt devel process seems to be to move the files and restore the old ones. I find this process confusing, and I don't see any git benefits for doing things this way. So just copy the files. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21506 Signed-off-by: Robert Marko <robimarko@gmail.com>
433 lines
17 KiB
Diff
433 lines
17 KiB
Diff
From 48dc6d2fe28865a5c3d271aeb966b984a8085e7c Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Sun, 9 Feb 2025 22:29:35 +0800
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Subject: [PATCH] dt-bindings: net: Add PPE for Qualcomm IPQ9574 SoC
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The PPE (packet process engine) hardware block is available in Qualcomm
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IPQ chipsets that support PPE architecture, such as IPQ9574. The PPE in
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the IPQ9574 SoC includes six ethernet ports (6 GMAC and 6 XGMAC), which
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are used to connect with external PHY devices by PCS. It includes an L2
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switch function for bridging packets among the 6 ethernet ports and the
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CPU port. The CPU port enables packet transfer between the ethernet
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ports and the ARM cores in the SoC, using the ethernet DMA.
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The PPE also includes packet processing offload capabilities for various
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networking functions such as route and bridge flows, VLANs, different
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tunnel protocols and VPN.
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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.../bindings/net/qcom,ipq9574-ppe.yaml | 406 ++++++++++++++++++
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1 file changed, 406 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml
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@@ -0,0 +1,406 @@
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+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/net/qcom,ipq9574-ppe.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Qualcomm IPQ packet process engine (PPE)
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+
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+maintainers:
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+ - Luo Jie <quic_luoj@quicinc.com>
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+ - Lei Wei <quic_leiwei@quicinc.com>
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+ - Suruchi Agarwal <quic_suruchia@quicinc.com>
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+ - Pavithra R <quic_pavir@quicinc.com>>
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+
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+description:
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+ The Ethernet functionality in the PPE (Packet Process Engine) is comprised
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+ of three components, the switch core, port wrapper and Ethernet DMA.
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+
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+ The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and
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+ two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet
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+ port to host CPU communication using Ethernet DMA. The other is used
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+ communicating to the EIP engine which is used for IPsec offload. On the
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+ IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external
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+ Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue
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+ Management) and SCH (Scheduler) modules for supporting the packet processing.
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+
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+ The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS)
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+ supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There
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+ are 3 UNIPHY (PCS) instances supported on the IPQ9574.
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+
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+ Ethernet DMA is used to transmit and receive packets between the six Ethernet
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+ ports and ARM host CPU.
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+
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+ The follow diagram shows the PPE hardware block along with its connectivity
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+ to the external hardware blocks such clock hardware blocks (CMNPLL, GCC,
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+ NSS clock controller) and ethernet PCS/PHY blocks. For depicting the PHY
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+ connectivity, one 4x1 Gbps PHY (QCA8075) and two 10 GBps PHYs are used as an
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+ example.
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+ - |
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+ +---------+
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+ | 48 MHZ |
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+ +----+----+
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+ |(clock)
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+ v
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+ +----+----+
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+ +------| CMN PLL |
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+ | +----+----+
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+ | |(clock)
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+ | v
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+ | +----+----+ +----+----+ (clock) +----+----+
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+ | +---| NSSCC | | GCC |--------->| MDIO |
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+ | | +----+----+ +----+----+ +----+----+
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+ | | |(clock & reset) |(clock)
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+ | | v v
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+ | | +-----------------------------+----------+----------+---------+
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+ | | | +-----+ |EDMA FIFO | | EIP FIFO|
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+ | | | | SCH | +----------+ +---------+
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+ | | | +-----+ | | |
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+ | | | +------+ +------+ +-------------------+ |
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+ | | | | BM | | QM | IPQ9574-PPE | L2/L3 Process | |
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+ | | | +------+ +------+ +-------------------+ |
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+ | | | | |
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+ | | | +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ |
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+ | | | | MAC0 | | MAC1 | | MAC2 | | MAC3 | | XGMAC4| |XGMAC5 | |
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+ | | | +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ |
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+ | | | | | | | | | |
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+ | | +-----+---------+---------+---------+---------+---------+-----+
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+ | | | | | | | |
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+ | | +---+---------+---------+---------+---+ +---+---+ +---+---+
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+ +--+---->| PCS0 | | PCS1 | | PCS2 |
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+ |(clock) +---+---------+---------+---------+---+ +---+---+ +---+---+
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+ | | | | | | |
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+ | +---+---------+---------+---------+---+ +---+---+ +---+---+
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+ +------->| QCA8075 PHY | | PHY4 | | PHY5 |
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+ (clock) +-------------------------------------+ +-------+ +-------+
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+
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+properties:
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+ compatible:
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+ enum:
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+ - qcom,ipq9574-ppe
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ items:
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+ - description: PPE core clock from NSS clock controller
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+ - description: PPE APB (Advanced Peripheral Bus) clock from NSS clock controller
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+ - description: PPE ingress process engine clock from NSS clock controller
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+ - description: PPE BM, QM and scheduler clock from NSS clock controller
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+
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+ clock-names:
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+ items:
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+ - const: ppe
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+ - const: apb
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+ - const: ipe
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+ - const: btq
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+
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+ resets:
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+ maxItems: 1
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+ description: PPE reset, which is necessary before configuring PPE hardware
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+
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+ interconnects:
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+ items:
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+ - description: Clock path leading to PPE switch core function
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+ - description: Clock path leading to PPE register access
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+ - description: Clock path leading to QoS generation
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+ - description: Clock path leading to timeout reference
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+ - description: Clock path leading to NSS NOC from memory NOC
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+ - description: Clock path leading to memory NOC from NSS NOC
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+ - description: Clock path leading to enhanced memory NOC from NSS NOC
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+
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+ interconnect-names:
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+ items:
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+ - const: ppe
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+ - const: ppe_cfg
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+ - const: qos_gen
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+ - const: timeout_ref
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+ - const: nssnoc_memnoc
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+ - const: memnoc_nssnoc
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+ - const: memnoc_nssnoc_1
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+
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+ ethernet-dma:
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+ type: object
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+ additionalProperties: false
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+ description:
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+ EDMA (Ethernet DMA) is used to transmit packets between PPE and ARM
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+ host CPU. There are 32 TX descriptor rings, 32 TX completion rings,
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+ 24 RX descriptor rings and 8 RX fill rings supported.
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+
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+ properties:
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+ clocks:
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+ items:
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+ - description: EDMA system clock from NSS Clock Controller
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+ - description: EDMA APB (Advanced Peripheral Bus) clock from
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+ NSS Clock Controller
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+
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+ clock-names:
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+ items:
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+ - const: sys
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+ - const: apb
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+
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+ resets:
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+ maxItems: 1
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+ description: EDMA reset from NSS clock controller
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+
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+ interrupts:
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+ minItems: 29
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+ maxItems: 57
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+
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+ interrupt-names:
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+ minItems: 29
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+ maxItems: 57
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+ items:
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+ pattern: '^(txcmpl_([0-9]|[1-2][0-9]|3[0-1])|rxdesc_([0-9]|1[0-9]|2[0-3])|misc)$'
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+ description:
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+ Interrupts "txcmpl_[0-31]" are the Ethernet DMA Tx completion ring interrupts.
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+ Interrupts "rxdesc_[0-23]" are the Ethernet DMA Rx Descriptor ring interrupts.
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+ Interrupt "misc" is the Ethernet DMA miscellaneous error interrupt.
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+
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+ required:
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+ - clocks
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+ - clock-names
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+ - resets
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+ - interrupts
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+ - interrupt-names
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - resets
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+ - interconnects
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+ - interconnect-names
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+ - ethernet-dma
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+
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+allOf:
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+ - $ref: ethernet-switch.yaml
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+
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+unevaluatedProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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+ #include <dt-bindings/interconnect/qcom,ipq9574.h>
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+ #include <dt-bindings/interrupt-controller/arm-gic.h>
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+
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+ ethernet-switch@3a000000 {
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+ compatible = "qcom,ipq9574-ppe";
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+ reg = <0x3a000000 0xbef800>;
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+ clocks = <&nsscc 80>,
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+ <&nsscc 79>,
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+ <&nsscc 81>,
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+ <&nsscc 78>;
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+ clock-names = "ppe",
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+ "apb",
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+ "ipe",
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+ "btq";
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+ resets = <&nsscc 108>;
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+ interconnects = <&nsscc MASTER_NSSNOC_PPE &nsscc SLAVE_NSSNOC_PPE>,
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+ <&nsscc MASTER_NSSNOC_PPE_CFG &nsscc SLAVE_NSSNOC_PPE_CFG>,
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+ <&gcc MASTER_NSSNOC_QOSGEN_REF &gcc SLAVE_NSSNOC_QOSGEN_REF>,
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+ <&gcc MASTER_NSSNOC_TIMEOUT_REF &gcc SLAVE_NSSNOC_TIMEOUT_REF>,
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+ <&gcc MASTER_MEM_NOC_NSSNOC &gcc SLAVE_MEM_NOC_NSSNOC>,
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+ <&gcc MASTER_NSSNOC_MEMNOC &gcc SLAVE_NSSNOC_MEMNOC>,
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+ <&gcc MASTER_NSSNOC_MEM_NOC_1 &gcc SLAVE_NSSNOC_MEM_NOC_1>;
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+ interconnect-names = "ppe",
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+ "ppe_cfg",
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+ "qos_gen",
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+ "timeout_ref",
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+ "nssnoc_memnoc",
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+ "memnoc_nssnoc",
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+ "memnoc_nssnoc_1";
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+
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+ ethernet-dma {
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+ clocks = <&nsscc 77>,
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+ <&nsscc 76>;
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+ clock-names = "sys",
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+ "apb";
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+ resets = <&nsscc 0>;
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+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "txcmpl_8",
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+ "txcmpl_9",
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+ "txcmpl_10",
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+ "txcmpl_11",
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+ "txcmpl_12",
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+ "txcmpl_13",
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+ "txcmpl_14",
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+ "txcmpl_15",
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+ "txcmpl_16",
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+ "txcmpl_17",
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+ "txcmpl_18",
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+ "txcmpl_19",
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+ "txcmpl_20",
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+ "txcmpl_21",
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+ "txcmpl_22",
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+ "txcmpl_23",
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+ "txcmpl_24",
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+ "txcmpl_25",
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+ "txcmpl_26",
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+ "txcmpl_27",
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+ "txcmpl_28",
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+ "txcmpl_29",
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+ "txcmpl_30",
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+ "txcmpl_31",
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+ "rxdesc_20",
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+ "rxdesc_21",
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+ "rxdesc_22",
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+ "rxdesc_23",
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+ "misc";
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+ };
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+
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+ ethernet-ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@1 {
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+ reg = <1>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy0>;
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+ pcs-handle = <&pcs0_mii0>;
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+ clocks = <&nsscc 33>,
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+ <&nsscc 34>,
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+ <&nsscc 37>;
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+ clock-names = "mac",
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+ "rx",
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+ "tx";
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+ resets = <&nsscc 29>,
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+ <&nsscc 96>,
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+ <&nsscc 97>;
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+ reset-names = "mac",
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+ "rx",
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+ "tx";
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy1>;
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+ pcs-handle = <&pcs0_mii1>;
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+ clocks = <&nsscc 40>,
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+ <&nsscc 41>,
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+ <&nsscc 44>;
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+ clock-names = "mac",
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+ "rx",
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+ "tx";
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+ resets = <&nsscc 30>,
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+ <&nsscc 98>,
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+ <&nsscc 99>;
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+ reset-names = "mac",
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+ "rx",
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+ "tx";
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy2>;
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+ pcs-handle = <&pcs0_mii2>;
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+ clocks = <&nsscc 47>,
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+ <&nsscc 48>,
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+ <&nsscc 51>;
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+ clock-names = "mac",
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+ "rx",
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+ "tx";
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+ resets = <&nsscc 31>,
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+ <&nsscc 100>,
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+ <&nsscc 101>;
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+ reset-names = "mac",
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+ "rx",
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+ "tx";
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy3>;
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+ pcs-handle = <&pcs0_mii3>;
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+ clocks = <&nsscc 54>,
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+ <&nsscc 55>,
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+ <&nsscc 58>;
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+ clock-names = "mac",
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+ "rx",
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+ "tx";
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+ resets = <&nsscc 32>,
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+ <&nsscc 102>,
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+ <&nsscc 103>;
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+ reset-names = "mac",
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+ "rx",
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+ "tx";
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+ };
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+
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+ port@5 {
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+ reg = <5>;
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+ phy-mode = "usxgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy4>;
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+ pcs-handle = <&pcs1_mii0>;
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+ clocks = <&nsscc 61>,
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+ <&nsscc 62>,
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+ <&nsscc 65>;
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+ clock-names = "mac",
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+ "rx",
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+ "tx";
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+ resets = <&nsscc 33>,
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+ <&nsscc 104>,
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+ <&nsscc 105>;
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+ reset-names = "mac",
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+ "rx",
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+ "tx";
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+ };
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+
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+ port@6 {
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+ reg = <6>;
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+ phy-mode = "usxgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy5>;
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+ pcs-handle = <&pcs2_mii0>;
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+ clocks = <&nsscc 68>,
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+ <&nsscc 69>,
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+ <&nsscc 72>;
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+ clock-names = "mac",
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+ "rx",
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+ "tx";
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+ resets = <&nsscc 34>,
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+ <&nsscc 106>,
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+ <&nsscc 107>;
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+ reset-names = "mac",
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+ "rx",
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+ "tx";
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+ };
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+ };
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+ };
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