4c2be83d5d
This version supports boards with 1.5GB or 3GB of RAM. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://github.com/openwrt/openwrt/pull/23360 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
26 lines
708 B
Diff
26 lines
708 B
Diff
From 1be7791f220325b0d6f42c3f2c383d8423936942 Mon Sep 17 00:00:00 2001
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From: Zoltan HERPAI <wigyori@uid0.hu>
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Date: Sat, 3 Jun 2023 00:52:04 +0200
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Subject: [PATCH 4005/4018] sunxi: add uart0_pins on Port E PE2/PE3 on D1s/T133
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Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
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---
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arch/riscv/dts/sunxi-d1s-t113.dtsi | 6 ++++++
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1 file changed, 6 insertions(+)
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--- a/dts/upstream/src/riscv/allwinner/sunxi-d1s-t113.dtsi
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+++ b/dts/upstream/src/riscv/allwinner/sunxi-d1s-t113.dtsi
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@@ -191,6 +191,12 @@
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pins = "PB6", "PB7";
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function = "uart3";
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};
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+
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+ /omit-if-no-ref/
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+ uart0_pins: uart0-pins {
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+ pins = "PE2", "PE3";
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+ function = "uart0";
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+ };
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};
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ccu: clock-controller@2001000 {
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