4c2be83d5d
This version supports boards with 1.5GB or 3GB of RAM. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://github.com/openwrt/openwrt/pull/23360 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
90 lines
3.2 KiB
Diff
90 lines
3.2 KiB
Diff
From e50a38fcd689bb3bc1e6cf191f482dbc179420b3 Mon Sep 17 00:00:00 2001
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From: Zoltan HERPAI <wigyori@uid0.hu>
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Date: Sat, 3 Jun 2023 23:57:46 +0200
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Subject: [PATCH 4009/4018] sunxi: add support for UART3 on PE pins
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Some boards use Port E pins for muxing the UART3 as console. Add a new
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Kconfig option allowing to select this (mimicking MMC_PINS_PH).
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Pinmux taken from https://bbs.aw-ol.com/assets/uploads/files/1648883311844-t113-s3_datasheet_v1.2.pdf
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Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
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---
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arch/arm/mach-sunxi/Kconfig | 6 ++++++
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arch/arm/mach-sunxi/board.c | 10 ++++++++--
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arch/riscv/dts/sunxi-d1s-t113.dtsi | 6 ++++++
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drivers/pinctrl/sunxi/pinctrl-sunxi.c | 4 ++++
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4 files changed, 24 insertions(+), 2 deletions(-)
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--- a/arch/arm/mach-sunxi/Kconfig
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+++ b/arch/arm/mach-sunxi/Kconfig
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@@ -899,6 +899,12 @@ config UART0_PORT_F
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at the same time, the system can be only booted in the FEL mode.
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Only enable this if you really know what you are doing.
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+config UART3_PINS_PE
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+ bool "Pins for uart3 are on Port E"
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+ ---help---
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+ Select this option for boards where uart3 uses the Port E pinmux.
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+ (Some T113-S3 boards use uart3 as console.)
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+
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config OLD_SUNXI_KERNEL_COMPAT
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bool "Enable workarounds for booting old kernels"
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---help---
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--- a/arch/arm/mach-sunxi/board.c
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+++ b/arch/arm/mach-sunxi/board.c
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@@ -178,16 +178,22 @@ static int gpio_init(void)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
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sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_R528)
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+#if defined(CONFIG_UART3_PINS_PE)
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+ sunxi_gpio_set_cfgpin(SUNXI_GPE(8), 5);
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+ sunxi_gpio_set_cfgpin(SUNXI_GPE(9), 5);
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+ sunxi_gpio_set_pull(SUNXI_GPE(9), SUNXI_GPIO_PULL_UP);
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+#else
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sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7);
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sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP);
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+#endif
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#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
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sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
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sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 6 && defined(CONFIG_MACH_SUN8I_R528)
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- sunxi_gpio_set_cfgpin(SUNXI_GPE(6), 9);
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- sunxi_gpio_set_cfgpin(SUNXI_GPE(7), 9);
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+ sunxi_gpio_set_cfgpin(SUNXI_GPE(6), 3);
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+ sunxi_gpio_set_cfgpin(SUNXI_GPE(7), 3);
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sunxi_gpio_set_pull(SUNXI_GPE(7), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \
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!defined(CONFIG_MACH_SUN8I_R40)
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--- a/dts/upstream/src/riscv/allwinner/sunxi-d1s-t113.dtsi
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+++ b/dts/upstream/src/riscv/allwinner/sunxi-d1s-t113.dtsi
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@@ -193,6 +193,12 @@
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};
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/omit-if-no-ref/
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+ uart3_pe_pins: uart3-pe-pins {
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+ pins = "PE8", "PE9";
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+ function = "uart3";
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+ };
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+
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+ /omit-if-no-ref/
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uart0_pins: uart0-pins {
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pins = "PE2", "PE3";
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function = "uart0";
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--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
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+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
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@@ -614,7 +614,11 @@ static const struct sunxi_pinctrl_functi
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#endif
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{ "uart1", 2 }, /* PG6-PG7 */
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{ "uart2", 7 }, /* PB0-PB1 */
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+#if IS_ENABLED(CONFIG_UART3_PINS_PE)
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+ { "uart3", 5 }, /* PE8-PE9 */
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+#else
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{ "uart3", 7 }, /* PB6-PB7 */
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+#endif
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{ "uart5", 3 }, /* PE6-PE7 */
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};
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