5b69e6a4a6
Update driver to be ready for the upcoming firmware release. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
135 lines
5.4 KiB
Diff
135 lines
5.4 KiB
Diff
From 8120b9b88ec47ee41b8350e3e4341839f5fdc28e Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 24 Mar 2026 18:17:49 +0000
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Subject: [PATCH 17/19] DO NOT SUBMIT: net: dsa: mxl862xx: re-introduce PCE
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workaround for old firmware
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Re-introduce the legacy PCE rule paths needed for firmware versions
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older than 1.0.83.
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Firmware >= 1.0.83 exposes the new GSW_TFLOW_PCERULELOGICWRITE API
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which selects the per-CTP block via @region/@logicalportid and grows
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the hardware block on demand. Older firmware lacks that command and
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exposes only the legacy GSW_TFLOW_PCERULEWRITE call, where the rule
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index is a direct offset into a fixed-size pre-allocated CTP block.
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Add MXL862XX_TFLOW_PCERULEWRITE back to mxl862xx-cmd.h and make
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mxl862xx_pce_rule_write() pick the right command at runtime based on
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the cached firmware version.
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In addition, firmware older than 1.0.80 still installs global PCE
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rules at boot that redirect link-local frames (BPDUs, LLDP, LACP) to
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port 0 (the on-chip microcontroller) instead of the DSA CPU port.
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With port 0 disabled under DSA these rules silently drop matching
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traffic. Re-introduce mxl862xx_disable_fw_global_rules() to clear
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them out during setup. The upstream submission replaced that call
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with a dev_warn() since firmware >= 1.0.80 no longer installs the
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problematic rules.
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This commit is for downstream use only and must not be submitted
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upstream.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/dsa/mxl862xx/mxl862xx-cmd.h | 1 +
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drivers/net/dsa/mxl862xx/mxl862xx.c | 61 +++++++++++++++++++++----
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2 files changed, 53 insertions(+), 9 deletions(-)
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--- a/drivers/net/dsa/mxl862xx/mxl862xx-cmd.h
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+++ b/drivers/net/dsa/mxl862xx/mxl862xx-cmd.h
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@@ -32,6 +32,7 @@
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#define MXL862XX_COMMON_MONITORPORTCFGSET (MXL862XX_COMMON_MAGIC + 0xe)
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#define MXL862XX_COMMON_REGISTERMOD (MXL862XX_COMMON_MAGIC + 0x11)
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+#define MXL862XX_TFLOW_PCERULEWRITE (MXL862XX_TFLOW_MAGIC + 0x2)
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#define MXL862XX_TFLOW_PCERULEALLOC (MXL862XX_TFLOW_MAGIC + 0x4)
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#define MXL862XX_TFLOW_PCERULEFREE (MXL862XX_TFLOW_MAGIC + 0x5)
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#define MXL862XX_TFLOW_PCERULELOGICWRITE \
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--- a/drivers/net/dsa/mxl862xx/mxl862xx.c
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+++ b/drivers/net/dsa/mxl862xx/mxl862xx.c
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@@ -449,6 +449,43 @@ static int mxl862xx_setup_drop_meter(str
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return MXL862XX_API_WRITE(priv, MXL862XX_COMMON_REGISTERMOD, reg);
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}
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+/* Disable firmware global PCE rules that trap various protocols to the
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+ * on-die microcontroller (port 0) via PORTMAP_CPU. Under DSA, these
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+ * frames must either reach the host CPU via per-port rules (link-local)
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+ * or through the normal bridge forwarding path (ARP broadcast), so the
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+ * global firmware rules are not needed. With the microcontroller port
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+ * disabled they would silently drop matching traffic.
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+ *
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+ * Global rules have lower indices than CTP rules, hence higher priority
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+ * in the PCE pipeline -- they must be explicitly disabled or they will
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+ * shadow the per-CTP traps.
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+ *
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+ * Indices from gsw_flow_index.h:
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+ * 1 -- BPDU (STP/RSTP, dst 01:80:c2:00:00:00)
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+ * 3 -- LLDP (EtherType 0x88cc)
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+ * 4 -- OAM/LACP (EtherType 0x8809)
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+ * 6 -- System MAC (dst 02:e0:92:00:00:01, vendor management MAC)
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+ * 7 -- ARP Request (broadcast + EtherType 0x0806 + TPA 192.0.2.1)
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+ */
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+static int mxl862xx_disable_fw_global_rules(struct dsa_switch *ds)
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+{
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+ static const u16 indices[] = { 1, 3, 4, 6, 7 };
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+ struct mxl862xx_pce_rule rule;
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+ int i, ret;
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+
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+ for (i = 0; i < ARRAY_SIZE(indices); i++) {
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+ memset(&rule, 0, sizeof(rule));
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+ rule.pattern.index = cpu_to_le16(indices[i]);
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+ /* pattern.enable == 0 -> rule is disabled */
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+
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+ ret = MXL862XX_API_WRITE(ds->priv,
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+ MXL862XX_TFLOW_PCERULEWRITE, rule);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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/* Per-CTP logical indices for protocol trap rules.
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*
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@@ -463,16 +500,20 @@ static int mxl862xx_setup_drop_meter(str
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#define MXL862XX_MLDV1_CTP_INDEX 3
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#define MXL862XX_MLDV2_CTP_INDEX 4
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-/* Install (or overwrite) a PCE rule via the firmware's logical-index
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- * API. The firmware translates the logical index in @rule->pattern.index
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- * to a physical position within the block selected by @rule->region and
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- * @rule->logicalportid, and expands the hardware block size as needed.
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+/* Install (or overwrite) a PCE rule. On firmware >= 1.0.83 use the
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+ * logical-index API (PCERULELOGICWRITE), which grows the per-CTP block
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+ * on demand. On older firmware that API does not exist, so fall back
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+ * to the legacy PCERULEWRITE call which uses the rule index as a
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+ * direct offset into a fixed-size pre-allocated CTP block.
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*/
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static int mxl862xx_pce_rule_write(struct mxl862xx_priv *priv,
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struct mxl862xx_pce_rule *rule)
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{
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- return MXL862XX_API_WRITE(priv, MXL862XX_TFLOW_PCERULELOGICWRITE,
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- *rule);
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+ u16 cmd = MXL862XX_FW_VER_MIN(priv, 1, 0, 83) ?
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+ MXL862XX_TFLOW_PCERULELOGICWRITE :
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+ MXL862XX_TFLOW_PCERULEWRITE;
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+
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+ return MXL862XX_API_WRITE(priv, cmd, *rule);
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}
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/**
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@@ -1130,9 +1171,11 @@ static int mxl862xx_setup(struct dsa_swi
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if (ret)
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return ret;
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- if (!MXL862XX_FW_VER_MIN(priv, 1, 0, 80))
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- dev_warn(ds->dev, "firmware < 1.0.80 installs global PCE rules "
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- "that interfere with DSA operation, please update\n");
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+ if (!MXL862XX_FW_VER_MIN(priv, 1, 0, 80)) {
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+ ret = mxl862xx_disable_fw_global_rules(ds);
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+ if (ret)
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+ return ret;
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+ }
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/* Pre-allocate firmware resources for all ports. The DSA core
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* calls change_tag_protocol() between setup() and port_setup(),
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