6369c9e5c7
The functionality/support for 5G and 10G PHYs was extracted from the realtek-phy driver and ported to the upstream Linux realtek PHY driver. These PHY chips need a sequence of register writes (and similar operations) for initialization. These sequences are provided as firmware files which are interpreted/applied by a new register patch engine. By switching to the upstream driver, it should be possible to get rid of a large chunk of (from OpenWrt perspective) unmaintained code from Realtek. The actual Linux phy-core infrastructure from Linux can be mostly used and only the Realtek specific quirks need to be handled. The files which need to be provided are depending on the PHY: * rtl8261n.bin (package "rtl8261n-firmware" or "rtl8261n-lp-firmware") - RTL8251L 5Gbps PHY - RTL8261BE 10Gbps PHY - RTL8261N 10Gbps PHY * rtl8264b.bin (package "rtl8264b-firmware") - RTL8254B 5Gbps PHY - RTL8264 10Gbps PHY - RTL8264B 10Gbps PHY Files which are affected by this change (DEVICE_PACKAGES dependencies, hwmon paths, default kernel configurations, refresh of patches, ...) are updated at the same times. Signed-off-by: Balázs Triszka <info@balika011.hu> Co-authored-by: Semih Baskan <strst.gs@gmail.com> Co-authored-by: Jonas Jelonek <jelonek.jonas@gmail.com> Co-authored-by: Gilly1970 <gilroyscott@hotmail.com> Co-authored-by: Aleksander Jan Bajkowski <olek2@wp.pl> Co-authored-by: Carlo Szelinsky <github@szelinsky.de> [sven: rebase, integrate suggestions from PR, add device packages, split] Signed-off-by: Sven Eckelmann <sven@narfation.org> [daniel: stripped to Linux 6.18 only, dropped unrelated changes] Signed-off-by: Daniel Golle <daniel@makrotopia.org>
133 lines
3.8 KiB
Diff
133 lines
3.8 KiB
Diff
From 330296ea9e158758aa65631f5ec64aa74806b7e2 Mon Sep 17 00:00:00 2001
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From: Damien Dejean <dam.dejean@gmail.com>
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Date: Wed, 18 Mar 2026 22:54:59 +0100
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Subject: [PATCH 2/4] net: phy: realtek: add RTL8224 pair order support
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The RTL8224 has a register to configure a pair swap (from ABCD order to
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DCBA) providing PCB designers more flexbility when wiring the chip. The
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swap parameter has to be set correctly for each of the 4 ports before
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the chip can detect a link.
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After a reset, this register is (unfortunately) left in a random state,
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thus it has to be initialized. On most of the devices the bootloader
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does it once for all and we can rely on the value set, on some other it
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is not and the kernel has to do it.
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The MDI pair swap can be set in the device tree using the property
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enet-phy-pair-order. The property is set to 0 to keep the default order
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(ABCD), or 1 to reverse the pairs (DCBA).
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Signed-off-by: Damien Dejean <dam.dejean@gmail.com>
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Link: https://patch.msgid.link/20260318215502.106528-3-dam.dejean@gmail.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/phy/realtek/Kconfig | 1 +
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drivers/net/phy/realtek/realtek_main.c | 64 ++++++++++++++++++++++++++
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2 files changed, 65 insertions(+)
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--- a/drivers/net/phy/realtek/Kconfig
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+++ b/drivers/net/phy/realtek/Kconfig
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@@ -2,6 +2,7 @@
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config REALTEK_PHY
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tristate "Realtek PHYs"
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select PHY_COMMON_PROPS
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+ select PHY_PACKAGE
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help
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Currently supports RTL821x/RTL822x and fast ethernet PHYs
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--- a/drivers/net/phy/realtek/realtek_main.c
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+++ b/drivers/net/phy/realtek/realtek_main.c
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@@ -21,6 +21,7 @@
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#include <linux/string_choices.h>
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#include <net/phy/realtek_phy.h>
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+#include "../phylib.h"
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#include "realtek.h"
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#define RTL8201F_IER 0x13
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@@ -177,6 +178,8 @@
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#define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN BIT(12)
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#define RTL8221B_PHYCR1_PHYAD_0_EN BIT(13)
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+#define RTL8224_VND1_MDI_PAIR_SWAP 0xa90
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+
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#define RTL8366RB_POWER_SAVE 0x15
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#define RTL8366RB_POWER_SAVE_ON BIT(12)
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@@ -1889,6 +1892,66 @@ static int rtl8224_cable_test_get_status
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return rtl8224_cable_test_report(phydev, finished);
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}
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+static int rtl8224_package_modify_mmd(struct phy_device *phydev, int devad,
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+ u32 regnum, u16 mask, u16 set)
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+{
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+ int val, ret;
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+
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+ phy_lock_mdio_bus(phydev);
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+
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+ val = __phy_package_read_mmd(phydev, 0, devad, regnum);
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+ if (val < 0) {
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+ ret = val;
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+ goto exit;
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+ }
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+
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+ val &= ~mask;
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+ val |= set;
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+
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+ ret = __phy_package_write_mmd(phydev, 0, devad, regnum, val);
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+
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+exit:
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+ phy_unlock_mdio_bus(phydev);
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+ return ret;
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+}
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+
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+static int rtl8224_mdi_config_order(struct phy_device *phydev)
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+{
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+ struct device_node *np = phydev->mdio.dev.of_node;
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+ u8 port_offset = phydev->mdio.addr & 3;
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+ u32 order = 0;
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+ int ret;
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+
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+ ret = of_property_read_u32(np, "enet-phy-pair-order", &order);
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+
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+ /* Do nothing in case the property is not present */
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+ if (ret == -EINVAL || ret == -ENOSYS)
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+ return 0;
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+
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+ if (ret)
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+ return ret;
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+
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+ if (order & ~1)
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+ return -EINVAL;
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+
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+ return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1,
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+ RTL8224_VND1_MDI_PAIR_SWAP,
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+ BIT(port_offset),
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+ order ? BIT(port_offset) : 0);
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+}
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+
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+static int rtl8224_config_init(struct phy_device *phydev)
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+{
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+ return rtl8224_mdi_config_order(phydev);
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+}
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+
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+static int rtl8224_probe(struct phy_device *phydev)
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+{
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+ /* Chip exposes 4 ports, join all of them in the same package */
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+ return devm_phy_package_join(&phydev->mdio.dev, phydev,
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+ phydev->mdio.addr & ~3, 0);
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+}
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+
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static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
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{
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int val;
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@@ -3096,6 +3159,8 @@ static struct phy_driver realtek_drvs[]
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PHY_ID_MATCH_EXACT(0x001ccad0),
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.name = "RTL8224 2.5Gbps PHY",
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.flags = PHY_POLL_CABLE_TEST,
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+ .probe = rtl8224_probe,
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+ .config_init = rtl8224_config_init,
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.get_features = rtl822x_c45_get_features,
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.config_aneg = rtl822x_c45_config_aneg,
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.read_status = rtl822x_c45_read_status,
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