6369c9e5c7
The functionality/support for 5G and 10G PHYs was extracted from the realtek-phy driver and ported to the upstream Linux realtek PHY driver. These PHY chips need a sequence of register writes (and similar operations) for initialization. These sequences are provided as firmware files which are interpreted/applied by a new register patch engine. By switching to the upstream driver, it should be possible to get rid of a large chunk of (from OpenWrt perspective) unmaintained code from Realtek. The actual Linux phy-core infrastructure from Linux can be mostly used and only the Realtek specific quirks need to be handled. The files which need to be provided are depending on the PHY: * rtl8261n.bin (package "rtl8261n-firmware" or "rtl8261n-lp-firmware") - RTL8251L 5Gbps PHY - RTL8261BE 10Gbps PHY - RTL8261N 10Gbps PHY * rtl8264b.bin (package "rtl8264b-firmware") - RTL8254B 5Gbps PHY - RTL8264 10Gbps PHY - RTL8264B 10Gbps PHY Files which are affected by this change (DEVICE_PACKAGES dependencies, hwmon paths, default kernel configurations, refresh of patches, ...) are updated at the same times. Signed-off-by: Balázs Triszka <info@balika011.hu> Co-authored-by: Semih Baskan <strst.gs@gmail.com> Co-authored-by: Jonas Jelonek <jelonek.jonas@gmail.com> Co-authored-by: Gilly1970 <gilroyscott@hotmail.com> Co-authored-by: Aleksander Jan Bajkowski <olek2@wp.pl> Co-authored-by: Carlo Szelinsky <github@szelinsky.de> [sven: rebase, integrate suggestions from PR, add device packages, split] Signed-off-by: Sven Eckelmann <sven@narfation.org> [daniel: stripped to Linux 6.18 only, dropped unrelated changes] Signed-off-by: Daniel Golle <daniel@makrotopia.org>
191 lines
4.7 KiB
Diff
191 lines
4.7 KiB
Diff
From 672a9bfb2e01ecaf40e5b92e9cc564589ffc251d Mon Sep 17 00:00:00 2001
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From: Jan Hoffmann <jan@3e8.eu>
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Date: Tue, 23 Dec 2025 20:07:53 +0100
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Subject: [PATCH] net: phy: realtek: support MDI swapping for RTL8226
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Add support for configuring swapping of MDI pairs (ABCD->DCBA) when the
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property "enet-phy-pair-order" is specified.
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Unfortunately, no documentation about this feature is available, so the
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configuration involves magic values. Only enabling MDI swapping is
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supported, as it is unknown whether the patching step can be safely
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reversed.
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For now, only implement it for RTL8226, where it is needed to make the
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PHYs in Zyxel XGS1010-12 rev A1 work. However, parts of this code might
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also be useful for other PHYs in the future:
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RTL8221B also allows to configure MDI swapping via the same register,
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but does not need the additional patching step. Since it also supports
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configuration via strapping pins, there might not be any need for driver
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support on that PHY, though.
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The patching step itself seems to be the same which is also used by the
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integrated PHY of some Realtek PCIe/USB NICs.
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Signed-off-by: Jan Hoffmann <jan@3e8.eu>
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---
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drivers/net/phy/realtek/realtek_main.c | 159 ++++++++++++++++++++++++-
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1 file changed, 158 insertions(+), 1 deletion(-)
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--- a/drivers/net/phy/realtek/realtek_main.c
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+++ b/drivers/net/phy/realtek/realtek_main.c
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@@ -1514,6 +1514,148 @@ static unsigned int rtl822x_inband_caps(
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}
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}
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+static int rtl8226_set_mdi_swap(struct phy_device *phydev, bool swap_enable)
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+{
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+ u16 val = swap_enable ? BIT(5) : 0;
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+
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+ return phy_modify_mmd(phydev, MDIO_MMD_VEND1, 0x6a21, BIT(5), val);
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+}
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+
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+static int rtl8226_patch_mdi_swap(struct phy_device *phydev)
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+{
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+ int ret;
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+ u16 vals[4];
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+
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+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xd068);
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+ if (ret < 0)
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+ return ret;
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+
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+ if (!(ret & BIT(1))) {
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+ /* already swapped */
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+ return 0;
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+ }
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+
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+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xd068, 0x7, 0x1);
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+ if (ret < 0)
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+ return ret;
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+
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+ /* swap adccal_offset */
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+
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+ for (int i = 0; i < 4; i++) {
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+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xd068, 0x3 << 3, i << 3);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xd06a);
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+ if (ret < 0)
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+ return ret;
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+
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+ vals[i] = ret;
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+ }
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+
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+ for (int i = 0; i < 4; i++) {
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+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xd068, 0x3 << 3, i << 3);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xd06a, vals[3 - i]);
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ /* swap rg_lpf_cap_xg */
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+
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+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xbd5a);
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+ if (ret < 0)
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+ return ret;
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+
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+ vals[0] = ret & 0x1f;
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+ vals[1] = (ret >> 8) & 0x1f;
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+
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+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xbd5c);
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+ if (ret < 0)
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+ return ret;
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+
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+ vals[2] = ret & 0x1f;
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+ vals[3] = (ret >> 8) & 0x1f;
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+
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+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xbd5a, 0x1f1f,
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+ vals[3] | (vals[2] << 8));
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xbd5c, 0x1f1f,
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+ vals[1] | (vals[0] << 8));
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+ if (ret < 0)
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+ return ret;
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+
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+ /* swap rg_lpf_cap */
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+
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+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xbc18);
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+ if (ret < 0)
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+ return ret;
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+
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+ vals[0] = ret & 0x1f;
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+ vals[1] = (ret >> 8) & 0x1f;
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+
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+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xbc1a);
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+ if (ret < 0)
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+ return ret;
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+
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+ vals[2] = ret & 0x1f;
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+ vals[3] = (ret >> 8) & 0x1f;
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+
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+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xbc18, 0x1f1f,
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+ vals[3] | (vals[2] << 8));
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xbc1a, 0x1f1f,
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+ vals[1] | (vals[0] << 8));
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+ if (ret < 0)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static int rtl8226_config_mdi_order(struct phy_device *phydev)
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+{
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+ u32 order;
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+ int ret;
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+
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+ ret = of_property_read_u32(phydev->mdio.dev.of_node, "enet-phy-pair-order", &order);
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+
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+ /* Property not present, nothing to do */
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+ if (ret == -EINVAL)
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+ return 0;
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+
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+ if (ret)
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+ return ret;
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+
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+ /* Only enabling MDI swapping is supported */
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+ if (order != 1)
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+ return -EINVAL;
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+
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+ ret = rtl8226_set_mdi_swap(phydev, true);
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+ if (ret)
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+ return ret;
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+
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+ ret = rtl8226_patch_mdi_swap(phydev);
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+ return ret;
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+}
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+
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+static int rtl8226_config_init(struct phy_device *phydev)
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+{
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+ int ret;
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+
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+ ret = rtl8226_config_mdi_order(phydev);
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+ if (ret)
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+ return ret;
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+
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+ return rtl822x_config_init(phydev);
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+}
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+
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+
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static int rtl822xb_get_rate_matching(struct phy_device *phydev,
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phy_interface_t iface)
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{
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@@ -3083,7 +3225,7 @@ static struct phy_driver realtek_drvs[]
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.soft_reset = rtl822x_c45_soft_reset,
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.get_features = rtl822x_c45_get_features,
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.config_aneg = rtl822x_c45_config_aneg,
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- .config_init = rtl822x_config_init,
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+ .config_init = rtl8226_config_init,
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.inband_caps = rtl822x_inband_caps,
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.config_inband = rtl822x_config_inband,
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.read_status = rtl822xb_c45_read_status,
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