716661d562
The Allwinner T113-s3 (sun8i) SoC features a dual-core Cortex-A7 ARM CPU and 128MB of DDR3 memory in the same physical package. It supports industrial temperature ranges. Most of the IP blocks are shared with the D1/D1s core. There are multiple variants of the SoC, which may vary in the included memory size, with some of them including a C906 RISC-V co-processor. Boards supported: - MangoPi MQDual T113 - wireless-only (RTL8723DS) - MYIR MYD-YT113 eMMC - 1Gbit ethernet (Motorcomm YT8531 PHY) - 4GByte eMMC - M.2-type slot for 4G/5G cards, plus 2x SIM slot - USB 2.0 ports - GPIO/I2C/SPI/CAN ports - FNLink 6131 (rtl8733bu) wifi module - MYIR MYD-YT113 SPI - Same as above but with 256Mbyte SPI-NAND flash instead of eMMC - Rongpin RP-T113 - 100Mbit ethernet (ICplus IP101GR PHY) - miniPCIe slot for 4G cards, plus 1x SIM slot - 3x USB 2.0 ports - RTL8723BS wireless - HYM8563 RTC - GPIO/I2C/SPI/CAN ports - Olimex T113-Olinuxino - 100Mbit ethernet (ICplus IP101GR) - UEXT connector (GPIO/I2C/SPI ports) - 1x USB 2.0 - audio jack, LEDC Installation: Use the standard sunxi installation to an SD-card. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
130 lines
4.0 KiB
Diff
130 lines
4.0 KiB
Diff
From 13339996e5ffd1cf9e276e6403aa14948f27c56a Mon Sep 17 00:00:00 2001
|
|
From: Yegor Yefremov <yegorslists@googlemail.com>
|
|
Date: Wed, 28 Nov 2012 11:15:18 +0100
|
|
Subject: [PATCH 4001/4018] net: add ICPlus PHY driver
|
|
|
|
The driver code was taken from Linux kernel source:
|
|
drivers/net/phy/icplus.c
|
|
|
|
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
|
|
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
|
|
---
|
|
drivers/net/phy/Kconfig | 3 ++
|
|
drivers/net/phy/Makefile | 1 +
|
|
drivers/net/phy/icplus.c | 87 ++++++++++++++++++++++++++++++++++++++++
|
|
3 files changed, 91 insertions(+)
|
|
create mode 100644 drivers/net/phy/icplus.c
|
|
|
|
--- a/drivers/net/phy/Kconfig
|
|
+++ b/drivers/net/phy/Kconfig
|
|
@@ -173,6 +173,9 @@ config PHY_DAVICOM
|
|
config PHY_ET1011C
|
|
bool "LSI TruePHY ET1011C support"
|
|
|
|
+config PHY_ICPLUS
|
|
+ bool "IC+ IP101 Ethernet PHY support"
|
|
+
|
|
config PHY_LXT
|
|
bool "LXT971 Ethernet PHY support"
|
|
|
|
--- a/drivers/net/phy/Makefile
|
|
+++ b/drivers/net/phy/Makefile
|
|
@@ -18,6 +18,7 @@ obj-$(CONFIG_PHY_CORTINA) += cortina.o
|
|
obj-$(CONFIG_PHY_CORTINA_ACCESS) += ca_phy.o
|
|
obj-$(CONFIG_PHY_DAVICOM) += davicom.o
|
|
obj-$(CONFIG_PHY_ET1011C) += et1011c.o
|
|
+obj-$(CONFIG_PHY_ICPLUS) += icplus.o
|
|
obj-$(CONFIG_PHY_LXT) += lxt.o
|
|
obj-$(CONFIG_PHY_MARVELL) += marvell.o
|
|
obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o
|
|
--- /dev/null
|
|
+++ b/drivers/net/phy/icplus.c
|
|
@@ -0,0 +1,87 @@
|
|
+/*
|
|
+ * ICPlus PHY drivers
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or
|
|
+ * modify it under the terms of the GNU General Public License as
|
|
+ * published by the Free Software Foundation; either version 2 of
|
|
+ * the License, or (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
+ * MA 02111-1307 USA
|
|
+ *
|
|
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
|
|
+ *
|
|
+ */
|
|
+#include <phy.h>
|
|
+
|
|
+/* IP101A/G - IP1001 */
|
|
+#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
|
|
+#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
|
|
+#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
|
|
+#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
|
|
+#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
|
|
+#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
|
|
+#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */
|
|
+#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED
|
|
+
|
|
+static int ip1001_config(struct phy_device *phydev)
|
|
+{
|
|
+ int c;
|
|
+
|
|
+ /* Enable Auto Power Saving mode */
|
|
+ c = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2);
|
|
+ if (c < 0)
|
|
+ return c;
|
|
+ c |= IP1001_APS_ON;
|
|
+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c);
|
|
+ if (c < 0)
|
|
+ return c;
|
|
+
|
|
+ /* INTR pin used: speed/link/duplex will cause an interrupt */
|
|
+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS,
|
|
+ IP101A_G_IRQ_DEFAULT);
|
|
+ if (c < 0)
|
|
+ return c;
|
|
+
|
|
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
|
|
+ /*
|
|
+ * Additional delay (2ns) used to adjust RX clock phase
|
|
+ * at RGMII interface
|
|
+ */
|
|
+ c = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS);
|
|
+ if (c < 0)
|
|
+ return c;
|
|
+
|
|
+ c |= IP1001_PHASE_SEL_MASK;
|
|
+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS,
|
|
+ c);
|
|
+ if (c < 0)
|
|
+ return c;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int ip1001_startup(struct phy_device *phydev)
|
|
+{
|
|
+ genphy_update_link(phydev);
|
|
+ genphy_parse_link(phydev);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+U_BOOT_PHY_DRIVER(lxt971) = {
|
|
+ .name = "ICPlus IP1001",
|
|
+ .uid = 0x02430d90,
|
|
+ .mask = 0x0ffffff0,
|
|
+ .features = PHY_GBIT_FEATURES,
|
|
+ .config = &ip1001_config,
|
|
+ .startup = &ip1001_startup,
|
|
+ .shutdown = &genphy_shutdown,
|
|
+};
|