716661d562
The Allwinner T113-s3 (sun8i) SoC features a dual-core Cortex-A7 ARM CPU and 128MB of DDR3 memory in the same physical package. It supports industrial temperature ranges. Most of the IP blocks are shared with the D1/D1s core. There are multiple variants of the SoC, which may vary in the included memory size, with some of them including a C906 RISC-V co-processor. Boards supported: - MangoPi MQDual T113 - wireless-only (RTL8723DS) - MYIR MYD-YT113 eMMC - 1Gbit ethernet (Motorcomm YT8531 PHY) - 4GByte eMMC - M.2-type slot for 4G/5G cards, plus 2x SIM slot - USB 2.0 ports - GPIO/I2C/SPI/CAN ports - FNLink 6131 (rtl8733bu) wifi module - MYIR MYD-YT113 SPI - Same as above but with 256Mbyte SPI-NAND flash instead of eMMC - Rongpin RP-T113 - 100Mbit ethernet (ICplus IP101GR PHY) - miniPCIe slot for 4G cards, plus 1x SIM slot - 3x USB 2.0 ports - RTL8723BS wireless - HYM8563 RTC - GPIO/I2C/SPI/CAN ports - Olimex T113-Olinuxino - 100Mbit ethernet (ICplus IP101GR) - UEXT connector (GPIO/I2C/SPI ports) - 1x USB 2.0 - audio jack, LEDC Installation: Use the standard sunxi installation to an SD-card. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
39 lines
1.2 KiB
Diff
39 lines
1.2 KiB
Diff
--- a/arch/arm/mach-sunxi/board.c
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+++ b/arch/arm/mach-sunxi/board.c
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@@ -191,6 +191,10 @@ static int gpio_init(void)
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sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
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sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
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sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
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+#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I_R528)
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+ sunxi_gpio_set_cfgpin(SUNXI_GPD(7), 5);
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+ sunxi_gpio_set_cfgpin(SUNXI_GPD(8), 5);
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+ sunxi_gpio_set_pull(SUNXI_GPD(8), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 6 && defined(CONFIG_MACH_SUN8I_R528)
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sunxi_gpio_set_cfgpin(SUNXI_GPE(6), 3);
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sunxi_gpio_set_cfgpin(SUNXI_GPE(7), 3);
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--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
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+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
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@@ -619,6 +619,7 @@ static const struct sunxi_pinctrl_functi
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#else
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{ "uart3", 7 }, /* PB6-PB7 */
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#endif
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+ { "uart4", 5 }, /* PD7-PD8 */
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{ "uart5", 3 }, /* PE6-PE7 */
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};
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--- a/arch/riscv/dts/sunxi-d1s-t113.dtsi
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+++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi
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@@ -163,6 +163,12 @@
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pins = "PE2", "PE3";
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function = "uart0";
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};
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+
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+ /omit-if-no-ref/
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+ uart4_pd_pins: uart4-pd-pins {
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+ pins = "PD7", "PD8";
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+ function = "uart4";
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+ };
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};
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ccu: clock-controller@2001000 {
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