716661d562
The Allwinner T113-s3 (sun8i) SoC features a dual-core Cortex-A7 ARM CPU and 128MB of DDR3 memory in the same physical package. It supports industrial temperature ranges. Most of the IP blocks are shared with the D1/D1s core. There are multiple variants of the SoC, which may vary in the included memory size, with some of them including a C906 RISC-V co-processor. Boards supported: - MangoPi MQDual T113 - wireless-only (RTL8723DS) - MYIR MYD-YT113 eMMC - 1Gbit ethernet (Motorcomm YT8531 PHY) - 4GByte eMMC - M.2-type slot for 4G/5G cards, plus 2x SIM slot - USB 2.0 ports - GPIO/I2C/SPI/CAN ports - FNLink 6131 (rtl8733bu) wifi module - MYIR MYD-YT113 SPI - Same as above but with 256Mbyte SPI-NAND flash instead of eMMC - Rongpin RP-T113 - 100Mbit ethernet (ICplus IP101GR PHY) - miniPCIe slot for 4G cards, plus 1x SIM slot - 3x USB 2.0 ports - RTL8723BS wireless - HYM8563 RTC - GPIO/I2C/SPI/CAN ports - Olimex T113-Olinuxino - 100Mbit ethernet (ICplus IP101GR) - UEXT connector (GPIO/I2C/SPI ports) - 1x USB 2.0 - audio jack, LEDC Installation: Use the standard sunxi installation to an SD-card. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
26 lines
700 B
Diff
26 lines
700 B
Diff
From 0208e409b80562ad8e9d2de31f123cdeed37d88e Mon Sep 17 00:00:00 2001
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From: Zoltan HERPAI <wigyori@uid0.hu>
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Date: Sun, 4 Jun 2023 16:46:05 +0200
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Subject: [PATCH 15/25] ARM: dts: riscv: add uart0_pins on Port E pins
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Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
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---
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arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 6 ++++++
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1 file changed, 6 insertions(+)
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--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
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+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
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@@ -198,6 +198,12 @@
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"PC7";
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function = "spi0";
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};
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+
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+ /omit-if-no-ref/
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+ uart0_pins: uart0-pins {
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+ pins = "PE2", "PE3";
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+ function = "uart0";
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+ };
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};
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ccu: clock-controller@2001000 {
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