fc61e795ee
The kernel has two helper defines that guide about hardware characteristics. MIPS_L1_CACHE_SHIFT defines the cache line sizes (1<<x) of the target. It defaults to 5 - so it is assumed that the device has a cache line size of 32 bytes. This is not true for MIPS 4KEc cores that are driving the RTL838x SOCs. These cores have 16 byte cache line sizes. Adapt the CONFIG properties for this target to match the hardware. ARCH_DMA_MINALIGN definies the alignment for memory allocations. Other than its name suggests on MIPS devices that have non coherent DMA kmalloc() respects this configuration. This ensures that no normal memory is corrupted by DMA blocks that share the same cache line. The default for this is 128 bytes. And kernel states itself "Total overkill for most systems but need as a safe default. Set this one if any device in the system might do non-coherent DMA". Realtek devices use non coherent DMA so they are affected by the setting of ARCH_DMA_MINALIGN. Set this to cache line size for all devices to reduce memory waste. Link: https://github.com/openwrt/openwrt/pull/23492 Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> |
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| imagebuilder | ||
| linux | ||
| llvm-bpf | ||
| sdk | ||
| toolchain | ||
| Config.in | ||
| Makefile | ||