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openwrt/target/linux/realtek/dts/rtl9312_plasmacloud_common.dtsi
Markus Stockhausen 7bfa1fa83b realtek: rename smi-address dts property 
The rtl9300,smi-address property was first developed for the RTL930x
targets. So it got a device specific prefix. Nowadays it is used for
RTL931x targets too. Convert it to our gerneric realtek prefix.

find ./realtek -type f -exec sed -i 's/rtl9300,smi-address/realtek,smi-address/g' {} +

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21343
Signed-off-by: Robert Marko <robimarko@gmail.com>
2026-01-02 18:05:02 +01:00

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// SPDX-License-Identifier: GPL-2.0-or-later
#include "rtl931x.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
chosen {
/* get active mtdparts from u-boot */
/delete-property/ bootargs;
};
aliases {
led-boot = &led_status;
led-running = &led_status;
led-failsafe = &led_status;
led-upgrade = &led_status;
label-mac-device = &ethernet0;
};
memory@0 {
reg = <0x00000000 0x10000000>, /* low mem 256 MiB */
<0x90000000 0x10000000>; /* high mem 256 MiB */
};
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
};
keys {
compatible = "gpio-keys-polled";
poll-interval = <20>;
mode {
label = "reset";
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
sfp0: sfp-lan25 {
compatible = "sff,sfp";
pinctrl-names = "default";
pinctrl-0 = <&pinmux_disable_spi0>;
i2c-bus = <&i2c0>;
los-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 9 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
};
sfp1: sfp-lan26 {
compatible = "sff,sfp";
pinctrl-names = "default";
pinctrl-0 = <&pinmux_disable_spi0_cs0>,
<&pinmux_disable_spi0_cs1>;
i2c-bus = <&i2c1>;
los-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
};
sfp2: sfp-lan27 {
compatible = "sff,sfp";
i2c-bus = <&i2c2>;
los-gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio0 23 GPIO_ACTIVE_HIGH>;
};
sfp3: sfp-lan28 {
compatible = "sff,sfp";
i2c-bus = <&i2c3>;
los-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinmux_disable_sys_led>;
led_status: led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
};
led-1 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_ALARM;
gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
};
};
led_set@0 {
compatible = "realtek,rtl9300-leds";
active-low;
led_set0 = <(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)
(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_100M |
RTL93XX_LED_SET_10M | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)>;
led_set1 = <(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)
(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)>;
};
};
&i2c_mst1 {
status = "okay";
/* i2c of the SFP+ cage on port 24 */
i2c0: i2c@0 {
reg = <0>;
};
/* i2c of the SFP+ cage on port 25 */
i2c1: i2c@1 {
reg = <1>;
};
/* i2c of the SFP+ cage on port 26 */
i2c2: i2c@2 {
reg = <2>;
};
/* i2c of the SFP+ cage on port 27 */
i2c3: i2c@3 {
reg = <3>;
};
/* i2c of adt7476 hwmonitor */
i2c@4 {
reg = <4>;
adt7476@2e {
compatible = "adi,adt7476";
reg = <0x2e>;
};
};
};
&mdio_aux {
status = "okay";
gpio1: expander@24 {
compatible = "realtek,rtl8231";
reg = <24>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio1 0 0 37>;
led-controller {
compatible = "realtek,rtl8231-leds";
status = "disabled";
};
};
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0xc0000>;
read-only;
};
partition@c0000 {
label = "u-boot-env";
reg = <0xc0000 0x10000>;
nvmem-layout {
compatible = "u-boot,env";
macaddr_ubootenv_ethaddr: ethaddr {
#nvmem-cell-cells = <1>;
};
};
};
partition@d0000 {
label = "u-boot-env2";
reg = <0xd0000 0x10000>;
};
partition@e0000 {
label = "reserved";
reg = <0xe0000 0x500000>;
};
partition@5e0000 {
label = "firmware1";
reg = <0x5e0000 0xd10000>;
compatible = "openwrt,uimage", "denx,uimage";
openwrt,ih-magic = <0x93100000>;
};
partition@12f0000 {
label = "firmware2";
reg = <0x12f0000 0xd10000>;
compatible = "openwrt,uimage", "denx,uimage";
openwrt,ih-magic = <0x93100000>;
};
};
};
};
&ethernet0 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 0>;
nvmem-cell-names = "mac-address";
};
&mdio_ctrl {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_enable_mdc_mdio_0>,
<&pinmux_enable_mdc_mdio_1>;
};
&mdio_bus0 {
/* External RTL8224 PHY */
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <0 0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <0 1>;
};
phy4: ethernet-phy@4 {
reg = <4>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <0 2>;
};
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <0 3>;
};
phy8: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <0 4>;
};
phy9: ethernet-phy@9 {
reg = <9>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <0 5>;
};
phy12: ethernet-phy@12 {
reg = <12>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <0 6>;
};
phy13: ethernet-phy@13 {
reg = <13>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <0 7>;
};
phy16: ethernet-phy@16 {
reg = <16>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <0 8>;
};
phy17: ethernet-phy@17 {
reg = <17>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <0 9>;
};
phy20: ethernet-phy@20 {
reg = <20>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <0 10>;
};
phy21: ethernet-phy@21 {
reg = <21>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <0 11>;
};
phy24: ethernet-phy@24 {
reg = <24>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <1 12>;
};
phy25: ethernet-phy@25 {
reg = <25>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <1 13>;
};
phy28: ethernet-phy@28 {
reg = <28>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <1 14>;
};
phy29: ethernet-phy@29 {
reg = <29>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <1 15>;
};
phy32: ethernet-phy@32 {
reg = <32>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <1 16>;
};
phy33: ethernet-phy@33 {
reg = <33>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <1 17>;
};
phy36: ethernet-phy@36 {
reg = <36>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <1 18>;
};
phy37: ethernet-phy@37 {
reg = <37>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <1 19>;
};
phy40: ethernet-phy@40 {
reg = <40>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <1 20>;
};
phy41: ethernet-phy@41 {
reg = <41>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <1 21>;
};
phy44: ethernet-phy@44 {
reg = <44>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <1 22>;
};
phy45: ethernet-phy@45 {
reg = <45>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <1 23>;
};
};
&switch0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
/* copper ethernet */
SWITCH_PORT_SDS(0, 1, 2, 10g-qxgmii)
SWITCH_PORT_SDS(1, 2, 2, 10g-qxgmii)
SWITCH_PORT_SDS(4, 3, 2, 10g-qxgmii)
SWITCH_PORT_SDS(5, 4, 2, 10g-qxgmii)
SWITCH_PORT_SDS(8, 5, 3, 10g-qxgmii)
SWITCH_PORT_SDS(9, 6, 3, 10g-qxgmii)
SWITCH_PORT_SDS(12, 7, 3, 10g-qxgmii)
SWITCH_PORT_SDS(13, 8, 3, 10g-qxgmii)
SWITCH_PORT_SDS(16, 9, 4, 10g-qxgmii)
SWITCH_PORT_SDS(17, 10, 4, 10g-qxgmii)
SWITCH_PORT_SDS(20, 11, 4, 10g-qxgmii)
SWITCH_PORT_SDS(21, 12, 4, 10g-qxgmii)
SWITCH_PORT_SDS(24, 13, 5, 10g-qxgmii)
SWITCH_PORT_SDS(25, 14, 5, 10g-qxgmii)
SWITCH_PORT_SDS(28, 15, 5, 10g-qxgmii)
SWITCH_PORT_SDS(29, 16, 5, 10g-qxgmii)
SWITCH_PORT_SDS(32, 17, 6, 10g-qxgmii)
SWITCH_PORT_SDS(33, 18, 6, 10g-qxgmii)
SWITCH_PORT_SDS(36, 19, 6, 10g-qxgmii)
SWITCH_PORT_SDS(37, 20, 6, 10g-qxgmii)
SWITCH_PORT_SDS(40, 21, 7, 10g-qxgmii)
SWITCH_PORT_SDS(41, 22, 7, 10g-qxgmii)
SWITCH_PORT_SDS(44, 23, 7, 10g-qxgmii)
SWITCH_PORT_SDS(45, 24, 7, 10g-qxgmii)
port@48 {
reg = <48>;
label = "lan25";
pcs-handle = <&serdes8>;
phy-mode = "1000base-x";
sfp = <&sfp0>;
led-set = <1>;
managed = "in-band-status";
nvmem-cells = <&macaddr_ubootenv_ethaddr 25>;
nvmem-cell-names = "mac-address";
};
port@50 {
reg = <50>;
label = "lan26";
pcs-handle = <&serdes9>;
phy-mode = "1000base-x";
sfp = <&sfp1>;
led-set = <1>;
managed = "in-band-status";
nvmem-cells = <&macaddr_ubootenv_ethaddr 26>;
nvmem-cell-names = "mac-address";
};
port@52 {
reg = <52>;
label = "lan27";
pcs-handle = <&serdes10>;
phy-mode = "1000base-x";
sfp = <&sfp2>;
led-set = <1>;
managed = "in-band-status";
nvmem-cells = <&macaddr_ubootenv_ethaddr 27>;
nvmem-cell-names = "mac-address";
};
port@53 {
reg = <53>;
label = "lan28";
pcs-handle = <&serdes11>;
phy-mode = "1000base-x";
sfp = <&sfp3>;
led-set = <1>;
managed = "in-band-status";
nvmem-cells = <&macaddr_ubootenv_ethaddr 28>;
nvmem-cell-names = "mac-address";
};
/* cpu */
port@56 {
ethernet = <&ethernet0>;
reg = <56>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
&port0 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 1>;
nvmem-cell-names = "mac-address";
};
&port1 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 2>;
nvmem-cell-names = "mac-address";
};
&port4 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 3>;
nvmem-cell-names = "mac-address";
};
&port5 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 4>;
nvmem-cell-names = "mac-address";
};
&port8 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 5>;
nvmem-cell-names = "mac-address";
};
&port9 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 6>;
nvmem-cell-names = "mac-address";
};
&port12 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 7>;
nvmem-cell-names = "mac-address";
};
&port13 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 8>;
nvmem-cell-names = "mac-address";
};
&port16 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 9>;
nvmem-cell-names = "mac-address";
};
&port17 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 10>;
nvmem-cell-names = "mac-address";
};
&port20 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 11>;
nvmem-cell-names = "mac-address";
};
&port21 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 12>;
nvmem-cell-names = "mac-address";
};
&port24 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 13>;
nvmem-cell-names = "mac-address";
};
&port25 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 14>;
nvmem-cell-names = "mac-address";
};
&port28 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 15>;
nvmem-cell-names = "mac-address";
};
&port29 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 16>;
nvmem-cell-names = "mac-address";
};
&port32 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 17>;
nvmem-cell-names = "mac-address";
};
&port33 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 18>;
nvmem-cell-names = "mac-address";
};
&port36 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 19>;
nvmem-cell-names = "mac-address";
};
&port37 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 20>;
nvmem-cell-names = "mac-address";
};
&port40 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 21>;
nvmem-cell-names = "mac-address";
};
&port41 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 22>;
nvmem-cell-names = "mac-address";
};
&port44 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 23>;
nvmem-cell-names = "mac-address";
};
&port45 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 24>;
nvmem-cell-names = "mac-address";
};
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