7ea10c7015
I generate patches form git, so maintaining an old numbering scheme does not integrate well with my workflow. renumber the pacthes here so that the commit shows only the changes to the patches. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21506 Signed-off-by: Robert Marko <robimarko@gmail.com>
198 lines
4.7 KiB
Diff
198 lines
4.7 KiB
Diff
From 001b663ecc5f838dac143623badae0e472749d8a Mon Sep 17 00:00:00 2001
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From: Lei Wei <quic_leiwei@quicinc.com>
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Date: Tue, 14 May 2024 10:53:27 +0800
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Subject: [PATCH] arm64: dts: qcom: Add IPQ9574 RDP433 port node
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There are 6 PPE MAC ports available on RDP433. The port1-port4 are
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connected with QCA8075 QUAD PHYs through UNIPHY0 PCS channel0-channel3.
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The port5 is connected with Aquantia PHY through UNIPHY1 PCS channel0
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and the port6 is connected with Aquantia PHY through UNIPHY2 PCS
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channel0.
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Change-Id: Ic16efdef2fe2cff7b1e80245619c0f82afb24cb9
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Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
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---
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arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 167 ++++++++++++++++++++
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1 file changed, 167 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
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@@ -55,6 +55,46 @@
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status = "okay";
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};
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+&mdio {
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+ reset-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>;
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+ clock-frequency = <6250000>;
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+ status = "okay";
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+
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+ ethernet-phy-package@0 {
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+ compatible = "qcom,qca8075-package";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x10>;
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+ qcom,package-mode = "qsgmii";
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+
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+ phy0: ethernet-phy@10 {
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+ reg = <0x10>;
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+ };
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+
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+ phy1: ethernet-phy@11 {
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+ reg = <0x11>;
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+ };
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+
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+ phy2: ethernet-phy@12 {
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+ reg = <0x12>;
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+ };
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+
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+ phy3: ethernet-phy@13 {
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+ reg = <0x13>;
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+ };
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+ };
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+
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+ phy4: ethernet-phy@8 {
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+ compatible ="ethernet-phy-ieee802.3-c45";
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+ reg = <8>;
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+ };
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+
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+ phy5: ethernet-phy@0 {
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+ compatible ="ethernet-phy-ieee802.3-c45";
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+ reg = <0>;
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+ };
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+};
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+
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&tlmm {
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pcie1_default: pcie1-default-state {
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@@ -161,3 +201,130 @@
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};
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};
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};
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+
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+&qcom_ppe {
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+ ethernet-ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@1 {
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+ reg = <1>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy0>;
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+ pcs-handle = <&pcs0_ch0>;
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+ clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT1_RX_CLK>,
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+ <&nsscc NSS_CC_PORT1_TX_CLK>;
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+ clock-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ resets = <&nsscc PORT1_MAC_ARES>,
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+ <&nsscc PORT1_RX_ARES>,
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+ <&nsscc PORT1_TX_ARES>;
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+ reset-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy1>;
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+ pcs-handle = <&pcs0_ch1>;
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+ clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT2_RX_CLK>,
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+ <&nsscc NSS_CC_PORT2_TX_CLK>;
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+ clock-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ resets = <&nsscc PORT2_MAC_ARES>,
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+ <&nsscc PORT2_RX_ARES>,
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+ <&nsscc PORT2_TX_ARES>;
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+ reset-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy2>;
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+ pcs-handle = <&pcs0_ch2>;
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+ clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT3_RX_CLK>,
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+ <&nsscc NSS_CC_PORT3_TX_CLK>;
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+ clock-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ resets = <&nsscc PORT3_MAC_ARES>,
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+ <&nsscc PORT3_RX_ARES>,
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+ <&nsscc PORT3_TX_ARES>;
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+ reset-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy3>;
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+ pcs-handle = <&pcs0_ch3>;
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+ clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT4_RX_CLK>,
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+ <&nsscc NSS_CC_PORT4_TX_CLK>;
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+ clock-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ resets = <&nsscc PORT4_MAC_ARES>,
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+ <&nsscc PORT4_RX_ARES>,
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+ <&nsscc PORT4_TX_ARES>;
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+ reset-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ };
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+
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+ port@5 {
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+ reg = <5>;
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+ phy-mode = "usxgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy4>;
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+ pcs-handle = <&pcs1_ch0>;
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+ clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT5_RX_CLK>,
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+ <&nsscc NSS_CC_PORT5_TX_CLK>;
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+ clock-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ resets = <&nsscc PORT5_MAC_ARES>,
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+ <&nsscc PORT5_RX_ARES>,
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+ <&nsscc PORT5_TX_ARES>;
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+ reset-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ };
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+
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+ port@6 {
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+ reg = <6>;
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+ phy-mode = "usxgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy5>;
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+ pcs-handle = <&pcs2_ch0>;
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+ clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT6_RX_CLK>,
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+ <&nsscc NSS_CC_PORT6_TX_CLK>;
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+ clock-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ resets = <&nsscc PORT6_MAC_ARES>,
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+ <&nsscc PORT6_RX_ARES>,
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+ <&nsscc PORT6_TX_ARES>;
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+ reset-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ };
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+ };
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+};
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