82ddc472d7
There is currently a difference how upstream and downstream define
the switch in the dts. Downstream holds the switch as a member
node below a root switchcore parent. Upstream uses the switch as
the parent.
Upstream:
ethernet-switch@1b000000 {
mdio-controller@ca00 { };
ethernet { };
ethernet-ports { };
}
Downstream:
switchcore@1b000000 {
ethernet-switch {
ethernet-ports { };
};
mdio-controller@ca00 { };
ethernet { };
}
Align downstream to upstream and merge the ethernet-switch into
the parent node. For this to work adapt the port lookup in the MDIO
and PCS driver.
Remark! With this commit the boot process will give the spurious
error message "rtl838x_eth 1b000000.ethernet-switch:ethernet eth0:
Failed to create a device link to DSA switch 1b000000.ethernet-switch"
This comes from the fact that the switch is the parent of the ethernet
device. Thus a link back from ethernet device to the switch is no
longer possible. Testing shows that the error is just cosmetic.
Link: https://github.com/openwrt/openwrt/pull/23599
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
440 lines
8.9 KiB
Plaintext
440 lines
8.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "macros.dtsi"
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "realtek,rtl838x-soc";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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frequency = <1000000000>;
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cpu@0 {
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compatible = "mti,interaptive";
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reg = <0>;
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};
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cpu@1 {
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compatible = "mti,interaptive";
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reg = <1>;
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};
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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lx_clk: lx_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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cpc: cpc@1bde0000 {
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compatible = "mti,mips-cpc";
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reg = <0x1bde0000 0x8000>;
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};
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cpuclock: cpuclock@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* FIXME: there should be way to detect this */
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clock-frequency = <1000000000>;
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};
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cpuintc: cpuintc {
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compatible = "mti,cpu-interrupt-controller";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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gic: interrupt-controller@1ddc0000 {
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compatible = "mti,gic";
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reg = <0x1ddc0000 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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/*
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* Declare the interrupt-parent even though the mti,gic
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* binding doesn't require it, such that the kernel can
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* figure out that cpu_intc is the root interrupt
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* controller & should be probed first.
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*/
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interrupt-parent = <&cpuintc>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x18000000 0x20000>;
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ecc0: ecc@1a600 {
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compatible = "realtek,rtl9301-ecc";
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reg = <0x1a600 0x54>;
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status = "disabled";
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};
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spi0: spi@1200 {
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status = "okay";
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compatible = "realtek,rtl8380-spi";
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reg = <0x1200 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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snand: spi@1a400 {
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compatible = "realtek,rtl9301-snand";
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reg = <0x1a400 0x44>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&lx_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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watchdog0: watchdog@3260 {
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compatible = "realtek,rtl9310-wdt";
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reg = <0x3260 0xc>;
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realtek,reset-mode = "soc";
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clocks = <&lx_clk>;
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timeout-sec = <30>;
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interrupt-parent = <&gic>;
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interrupt-names = "phase1", "phase2";
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interrupts = <GIC_SHARED 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpio0: gpio-controller@3300 {
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compatible = "realtek,rtl9310-gpio", "realtek,otto-gpio";
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reg = <0x3300 0x1c>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer0: timer@3200 {
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compatible = "realtek,rtl931x-timer", "realtek,otto-timer";
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reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
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<0x3230 0x10>, <0x3240 0x10>, <0x3250 0x10>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&lx_clk>;
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};
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uart0: uart@2000 {
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compatible = "ns16550a";
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reg = <0x2000 0x100>;
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clock-frequency = <200000000>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <3>;
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interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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};
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uart1: uart@2100 {
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compatible = "ns16550a";
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reg = <0x2100 0x100>;
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clock-frequency = <200000000>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <3>;
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interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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status = "disabled";
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};
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};
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switch0: ethernet-switch@1b000000 {
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compatible = "realtek,rtl9311-switch", "realtek,otto-switch", "syscon", "simple-mfd";
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reg = <0x1b000000 0x10000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 15 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ethernet0: ethernet {
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compatible = "realtek,rtl9311-eth";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <3>;
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phy-mode = "internal";
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pinctrl-0 = <&pinmux_disable_ext_cpu>;
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pinctrl-names = "default";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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i2c_mst1: i2c@100c {
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compatible = "realtek,rtl9310-i2c";
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reg = <0x100c 0x18>;
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#address-cells = <1>;
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#size-cells = <0>;
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realtek,scl = <0>;
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status = "disabled";
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};
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i2c_mst2: i2c@1024 {
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compatible = "realtek,rtl9310-i2c";
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reg = <0x1024 0x18>;
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#address-cells = <1>;
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#size-cells = <0>;
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realtek,scl = <1>;
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status = "disabled";
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};
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mdio_ctrl: mdio-controller {
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compatible = "realtek,rtl9311-mdio", "realtek,otto-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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mdio_bus0: mdio-bus@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mdio_bus1: mdio-bus@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mdio_bus2: mdio-bus@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mdio_bus3: mdio-bus@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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mdio_aux: mdio-aux {
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compatible = "realtek,rtl9310-aux-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&pinmux_gpio_mdio_en>;
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pinctrl-names = "default";
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status = "disabled";
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};
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mdio_serdes: mdio-serdes {
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compatible = "realtek,rtl9311-serdes-mdio", "realtek,otto-serdes-mdio";
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};
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pcs {
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compatible = "realtek,rtl9311-pcs", "realtek,otto-pcs";
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#address-cells = <1>;
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#size-cells = <0>;
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serdes0: serdes@0 {
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reg = <0>;
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#pcs-cells = <1>;
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};
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serdes1: serdes@1 {
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reg = <1>;
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#pcs-cells = <1>;
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};
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serdes2: serdes@2 {
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reg = <2>;
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#pcs-cells = <1>;
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};
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serdes3: serdes@3 {
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reg = <3>;
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#pcs-cells = <1>;
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};
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serdes4: serdes@4 {
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reg = <4>;
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#pcs-cells = <1>;
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};
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serdes5: serdes@5 {
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reg = <5>;
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#pcs-cells = <1>;
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};
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serdes6: serdes@6 {
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reg = <6>;
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#pcs-cells = <1>;
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};
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serdes7: serdes@7 {
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reg = <7>;
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#pcs-cells = <1>;
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};
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serdes8: serdes@8 {
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reg = <8>;
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#pcs-cells = <1>;
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};
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serdes9: serdes@9 {
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reg = <9>;
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#pcs-cells = <1>;
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};
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serdes10: serdes@10 {
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reg = <10>;
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#pcs-cells = <1>;
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};
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serdes11: serdes@11 {
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reg = <11>;
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#pcs-cells = <1>;
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};
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serdes12: serdes@12 {
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reg = <12>;
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#pcs-cells = <1>;
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};
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serdes13: serdes@13 {
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reg = <13>;
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#pcs-cells = <1>;
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};
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};
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};
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pinmux@1b00103c {
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compatible = "pinctrl-single";
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reg = <0x1b00103c 0x4>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x1>;
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#pinctrl-cells = <2>;
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/* 31.25 MHz SPI master clock */
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pinmux_spi0_31mhz: spi0-31mhz {
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pinctrl-single,bits = <0x0 0x1800 0x3800>;
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};
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/* Enable GPIO 8, 9, 10 */
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pinmux_disable_spi0: disable-spi0 {
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pinctrl-single,bits = <0x0 0x0 0x400>;
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};
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/* Enable GPIO 12 */
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pinmux_disable_spi0_cs1: disable-spi-cs1 {
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pinctrl-single,bits = <0x0 0x0 0x200>;
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};
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/* Enable GPIO 11 */
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pinmux_disable_spi0_cs0: disable-spi-cs0 {
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pinctrl-single,bits = <0x0 0x0 0x100>;
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};
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};
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pinmux@1b001358 {
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compatible = "pinctrl-single";
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reg = <0x1b001358 0x4>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x1>;
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#pinctrl-cells = <2>;
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/* Enable GPIO 31 */
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pinmux_disable_led_sync: disable-led-sync {
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pinctrl-single,bits = <0x0 0x0 0x10000>;
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};
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pinmux_enable_led_sync: enable-led-sync {
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pinctrl-single,bits = <0x0 0x10000 0x10000>;
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};
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pinmux_enable_mdc_mdio_3: enable-mdc-mdio-3 {
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pinctrl-single,bits = <0x0 0x1000 0x1000>;
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};
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pinmux_enable_mdc_mdio_2: enable-mdc-mdio-2 {
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pinctrl-single,bits = <0x0 0x800 0x800>;
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};
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pinmux_enable_mdc_mdio_1: enable-mdc-mdio-1 {
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pinctrl-single,bits = <0x0 0x400 0x400>;
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};
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pinmux_enable_mdc_mdio_0: enable-mdc-mdio-0 {
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pinctrl-single,bits = <0x0 0x200 0x200>;
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};
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/* Enable GPIOs 3-7 */
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pinmux_disable_jtag: disable_jtag {
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pinctrl-single,bits = <0x0 0x0 0x8000>;
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};
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/* Controls GPIO0 */
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pinmux_disable_sys_led: disable_sys_led {
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pinctrl-single,bits = <0x0 0x0 0x100>;
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};
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pinmux_disable_ext_cpu: disable-ext-cpu {
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pinctrl-single,bits = <0x0 0x0 0x4>;
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};
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};
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pinmux@1b0007d4 {
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compatible = "pinctrl-single";
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reg = <0x1b0007d4 0x4>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x1>;
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#pinctrl-cells = <2>;
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pinmux_gpio_mdio_en: gpio-mdio-en {
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pinctrl-single,bits = <0x0 0x100 0x100>;
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};
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};
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};
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