8f21d26411
Refreshed automatically with `make target/linux/refresh V=s`. Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me> Link: https://github.com/openwrt/openwrt/pull/21019 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
208 lines
7.1 KiB
Diff
208 lines
7.1 KiB
Diff
From fde8e40b0bf72436ce75d21e8778049368ea200f Mon Sep 17 00:00:00 2001
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From: Kenneth Kasilag <kenneth@kasilag.me>
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Date: Mon, 6 Apr 2026 23:04:38 +0000
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Subject: [PATCH] airoha: fix PERST deassert in PCIe driver
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Due to hardware bugs, the PCIE Gen3 IP in Airoha AN7581 requires a
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special reset procedure:
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> MAC reset asserted thru the SCU block
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> PERST asserted thru the SCU for the desired PCIE lane
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> PHY initialization runs, clocks enabled
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> MAC reset deasserted
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> EQ config (if needed) written
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> PERST deasserted
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The existing code currently toggles PERST for all three PCIE
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ports every time mtk_pcie_en7581_power_up is called, resulting
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in PCIE link down issues.
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This issue was discovered during porting of the 6.18 kernel to
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AN7581. It is not entirely clear how the hardware seemed to
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function under kernel 6.12 with similar driver code, it is
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presumed that differences in assert/deassert times for PERST in
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6.18 changed which exposed the bug.
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Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
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---
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drivers/pci/controller/pcie-mediatek-gen3.c | 124 ++++++++-------
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1 file changed, 86 insertions(+), 38 deletions(-)
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--- a/drivers/pci/controller/pcie-mediatek-gen3.c
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+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
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@@ -72,8 +72,21 @@
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/* EN7581 NP_SCU register offsets for x2 link init */
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#define NP_SCU_LANE_CFG0 0x830
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+#define NP_SCU_XSI_MAC_RST BIT(7)
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+#define NP_SCU_XSI_PHY_RST BIT(8)
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+#define NP_SCU_PCIE2_RST BIT(27)
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#define NP_SCU_LANE_CFG1 0x834
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+#define NP_SCU_PCIE0_RST BIT(26)
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+#define NP_SCU_PCIE1_RST BIT(27)
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#define NP_SCU_CTRL_REG 0x88
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+#define NP_SCU_PERSTOUT BIT(29)
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+#define NP_SCU_PERSTOUT1 BIT(26)
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+#define NP_SCU_PERSTOUT2 BIT(16)
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+#define NP_SCU_PERST_ALL (NP_SCU_PERSTOUT | \
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+ NP_SCU_PERSTOUT1 | \
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+ NP_SCU_PERSTOUT2)
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+#define NP_SCU_SERDES_MUX_MASK GENMASK(1, 0)
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+#define NP_SCU_SERDES_MUX_X2 2
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#define PCIE_LINK_STATUS_REG 0x154
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#define PCIE_PORT_LINKUP BIT(8)
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@@ -1004,6 +1017,23 @@ static int mtk_pcie_en7581_power_up(stru
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dev_info(dev, "x2 mode: sister MAC mapped\n");
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}
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+ /* Select the correct reset for each PCIe port */
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+ u32 perst_mask = NP_SCU_PERST_ALL;
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+ if (pcie->x2_mode)
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+ perst_mask = NP_SCU_PERSTOUT | NP_SCU_PERSTOUT1;
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+ else if (pcie->reg_base == 0x1fc00000)
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+ perst_mask = NP_SCU_PERSTOUT;
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+ else if (pcie->reg_base == 0x1fc20000)
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+ perst_mask = NP_SCU_PERSTOUT1;
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+ else if (pcie->reg_base == 0x1fc40000)
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+ perst_mask = NP_SCU_PERSTOUT2;
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+
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+ /* Assert selected PERST prior to PHY init */
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+ if (pcie->np_scu) {
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+ regmap_update_bits(pcie->np_scu, NP_SCU_CTRL_REG, perst_mask, 0);
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+ msleep(1);
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+ }
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+
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err = phy_set_mode(pcie->phy, PHY_MODE_PCIE);
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if (err) {
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dev_err(dev, "failed to set PHY mode\n");
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@@ -1043,26 +1073,22 @@ static int mtk_pcie_en7581_power_up(stru
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pm_runtime_get_sync(dev);
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/*
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- * EN7581 x2: Assert PERST and serdes reset before enabling clocks
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- * so that MAC registers can be configured while devices are held
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- * in reset, ensuring link trains with the correct x2 settings.
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+ * EN7581 x2: Do serdes reset before enabling clocks so that MAC
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+ * registers can be configured while devices are held in reset,
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+ * ensuring link trains with the correct x2 settings.
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*/
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if (pcie->x2_mode && pcie->np_scu) {
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- /* Assert serdes reset on all lanes */
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+ /* Assert serdes reset on lanes 0 and 1 */
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regmap_update_bits(pcie->np_scu, NP_SCU_LANE_CFG1,
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- BIT(26) | BIT(27), BIT(26) | BIT(27));
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- regmap_update_bits(pcie->np_scu, NP_SCU_LANE_CFG0,
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- BIT(27), BIT(27));
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+ NP_SCU_PCIE0_RST | NP_SCU_PCIE1_RST,
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+ NP_SCU_PCIE0_RST | NP_SCU_PCIE1_RST);
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msleep(100);
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- /* Assert PERST on all ports */
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- regmap_update_bits(pcie->np_scu, NP_SCU_CTRL_REG,
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- BIT(16) | BIT(26) | BIT(29), 0);
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-
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/* Set serdes mux for 2-lane mode (bits[1:0] = 2) */
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regmap_update_bits(pcie->np_scu, NP_SCU_CTRL_REG,
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- BIT(0) | BIT(1), BIT(1));
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- mdelay(1);
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+ NP_SCU_SERDES_MUX_MASK,
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+ NP_SCU_SERDES_MUX_X2);
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+ msleep(1);
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}
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err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
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@@ -1085,11 +1111,9 @@ static int mtk_pcie_en7581_power_up(stru
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*/
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msleep(30);
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- /* Deassert serdes reset on all lanes */
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+ /* Deassert serdes reset on lanes 0 and 1 */
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regmap_update_bits(pcie->np_scu, NP_SCU_LANE_CFG1,
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- BIT(26) | BIT(27), 0);
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- regmap_update_bits(pcie->np_scu, NP_SCU_LANE_CFG0,
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- BIT(27), 0);
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+ NP_SCU_PCIE0_RST | NP_SCU_PCIE1_RST, 0);
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/* Clear SETTING_REG bit 13 for x2 mode on both MACs */
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val = readl_relaxed(pcie->base + PCIE_SETTING_REG);
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@@ -1109,59 +1133,16 @@ static int mtk_pcie_en7581_power_up(stru
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if (pcie->sister_base)
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writel_relaxed(0x1018020f, pcie->sister_base + 0x338);
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- /* Deassert PERST for all ports - link training starts */
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+ /* Deassert PERST on selected port - link training starts */
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msleep(10);
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regmap_update_bits(pcie->np_scu, NP_SCU_CTRL_REG,
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- BIT(16) | BIT(26) | BIT(29),
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- BIT(16) | BIT(26) | BIT(29));
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+ perst_mask,
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+ perst_mask);
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/* Wait for link training to complete */
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- msleep(800);
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-
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- /*
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- * Check if link trained at Gen3. If not, toggle serdes
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- * reset to force MAC to re-discover PHY Gen3 capability.
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- * Without this, MAC only advertises Gen1-Gen2 in LnkCap2.
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- */
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- val = readl_relaxed(pcie->base + PCIE_LINK_STATUS_REG);
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- if (val & PCIE_PORT_LINKUP) {
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- void __iomem *cfg = pcie->base + PCIE_CFG_OFFSET_ADDR;
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- u8 cap_ptr;
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- int speed = 0;
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-
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- /* Walk PCI cap list to find PCIe cap (ID=0x10) */
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- cap_ptr = readl_relaxed(cfg + PCI_CAPABILITY_LIST) & 0xFF;
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- while (cap_ptr >= 0x40) {
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- u32 hdr = readl_relaxed(cfg + cap_ptr);
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- if ((hdr & 0xFF) == PCI_CAP_ID_EXP) {
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- u32 lnk = readl_relaxed(cfg + cap_ptr + PCI_EXP_LNKCTL);
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- speed = (lnk >> 16) & PCI_EXP_LNKSTA_CLS;
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- break;
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- }
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- cap_ptr = (hdr >> 8) & 0xFF;
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- }
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-
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- if (speed > 0 && speed < 3) {
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- dev_info(dev, "x2: link at Gen%d, toggling serdes for Gen3\n", speed);
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- regmap_update_bits(pcie->np_scu, NP_SCU_LANE_CFG0,
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- BIT(7) | BIT(8), BIT(7) | BIT(8));
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- regmap_update_bits(pcie->np_scu, NP_SCU_LANE_CFG1,
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- BIT(26) | BIT(27), BIT(26) | BIT(27));
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- msleep(1000);
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- regmap_update_bits(pcie->np_scu, NP_SCU_LANE_CFG0,
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- BIT(7) | BIT(8), 0);
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- regmap_update_bits(pcie->np_scu, NP_SCU_LANE_CFG1,
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- BIT(26) | BIT(27), 0);
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- msleep(2000);
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- dev_info(dev, "x2: serdes toggle done, link retraining\n");
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- } else {
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- dev_info(dev, "x2: link at Gen%d, no toggle needed\n", speed);
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- }
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- } else {
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- dev_info(dev, "x2: link not up after init, skipping speed check\n");
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- }
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+ msleep(1000);
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- dev_info(dev, "x2: init complete, PERST deasserted\n");
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+ dev_info(dev, "x2: init complete\n");
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} else {
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/*
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* Non-x2 mode: standard EQ config then deassert PERST.
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@@ -1178,11 +1159,11 @@ static int mtk_pcie_en7581_power_up(stru
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FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf);
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writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG);
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- /* Deassert PERST for all ports */
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+ /* Deassert PERST on selected port */
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if (pcie->np_scu) {
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regmap_update_bits(pcie->np_scu, NP_SCU_CTRL_REG,
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- BIT(16) | BIT(26) | BIT(29),
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- BIT(16) | BIT(26) | BIT(29));
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+ perst_mask,
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+ perst_mask);
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msleep(100);
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}
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}
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