86e3c31bcc
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/23139 Signed-off-by: Nick Hainke <vincent@systemli.org>
445 lines
11 KiB
Diff
445 lines
11 KiB
Diff
From 4294e32111781b3de4d73b944cbd1bc1662a9a7a Mon Sep 17 00:00:00 2001
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From: Sam Edwards <cfsworks@gmail.com>
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Date: Wed, 11 Sep 2024 19:50:30 -0700
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Subject: arm64: dts: rockchip: Split up RK3588's PCIe pinctrls
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These pinctrls manage the low-speed PCIe signals:
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- CLKREQ#: An output on the RK3588 (both RC or EP modes), used to
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request that external clock-generation circuitry provide a clock.
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- PERST#: An input on the RK3588 in EP mode, used to detect a reset
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signal from the RC. In RC mode, the hardware does not use this signal:
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Linux itself generates it by putting the pin in GPIO mode.
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- WAKE#: In EP mode, this is an output; in RC mode, this is an input.
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Each of these signals serves a distinct purpose, and more importantly,
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PERST# should not be muxed when the RK3588 is in the RC role. Bundling
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them together in pinctrl groups prevents proper use: indeed, almost none
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of the current board-specific .dts files make any use of them.
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(Exception: Rock 5A recently had a patch land that misuses _pins; this
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patch corrects that.)
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However, on some RK3588 boards, the PCIe 3 controller will indefinitely
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stall the boot if CLKREQ# is not muxed (details in the next patch).
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This patch unbundles the signals to allow them to be used.
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Signed-off-by: Sam Edwards <CFSworks@gmail.com>
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Link: https://lore.kernel.org/r/20240912025034.180233-2-CFSworks@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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--- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
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@@ -1612,23 +1612,43 @@
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pcie20x1 {
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/omit-if-no-ref/
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- pcie20x1m0_pins: pcie20x1m0-pins {
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+ pcie20x1m0_clkreqn: pcie20x1m0-clkreqn {
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rockchip,pins =
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/* pcie20x1_2_clkreqn_m0 */
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- <3 RK_PC7 4 &pcfg_pull_none>,
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+ <3 RK_PC7 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie20x1m0_perstn: pcie20x1m0-perstn {
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+ rockchip,pins =
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/* pcie20x1_2_perstn_m0 */
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- <3 RK_PD1 4 &pcfg_pull_none>,
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+ <3 RK_PD1 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie20x1m0_waken: pcie20x1m0-waken {
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+ rockchip,pins =
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/* pcie20x1_2_waken_m0 */
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<3 RK_PD0 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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- pcie20x1m1_pins: pcie20x1m1-pins {
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+ pcie20x1m1_clkreqn: pcie20x1m1-clkreqn {
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rockchip,pins =
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/* pcie20x1_2_clkreqn_m1 */
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- <4 RK_PB7 4 &pcfg_pull_none>,
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+ <4 RK_PB7 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie20x1m1_perstn: pcie20x1m1-perstn {
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+ rockchip,pins =
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/* pcie20x1_2_perstn_m1 */
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- <4 RK_PC1 4 &pcfg_pull_none>,
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+ <4 RK_PC1 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie20x1m1_waken: pcie20x1m1-waken {
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+ rockchip,pins =
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/* pcie20x1_2_waken_m1 */
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<4 RK_PC0 4 &pcfg_pull_none>;
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};
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@@ -1654,52 +1674,127 @@
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pcie30x1 {
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/omit-if-no-ref/
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- pcie30x1m0_pins: pcie30x1m0-pins {
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+ pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn {
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rockchip,pins =
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/* pcie30x1_0_clkreqn_m0 */
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- <0 RK_PC0 12 &pcfg_pull_none>,
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+ <0 RK_PC0 12 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m0_0_perstn: pcie30x1m0-0-perstn {
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+ rockchip,pins =
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/* pcie30x1_0_perstn_m0 */
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- <0 RK_PC5 12 &pcfg_pull_none>,
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+ <0 RK_PC5 12 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m0_0_waken: pcie30x1m0-0-waken {
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+ rockchip,pins =
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/* pcie30x1_0_waken_m0 */
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- <0 RK_PC4 12 &pcfg_pull_none>,
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+ <0 RK_PC4 12 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn {
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+ rockchip,pins =
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/* pcie30x1_1_clkreqn_m0 */
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- <0 RK_PB5 12 &pcfg_pull_none>,
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+ <0 RK_PB5 12 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m0_1_perstn: pcie30x1m0-1-perstn {
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+ rockchip,pins =
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/* pcie30x1_1_perstn_m0 */
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- <0 RK_PB7 12 &pcfg_pull_none>,
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+ <0 RK_PB7 12 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m0_1_waken: pcie30x1m0-1-waken {
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+ rockchip,pins =
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/* pcie30x1_1_waken_m0 */
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<0 RK_PB6 12 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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- pcie30x1m1_pins: pcie30x1m1-pins {
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+ pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn {
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rockchip,pins =
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/* pcie30x1_0_clkreqn_m1 */
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- <4 RK_PA3 4 &pcfg_pull_none>,
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+ <4 RK_PA3 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m1_0_perstn: pcie30x1m1-0-perstn {
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+ rockchip,pins =
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/* pcie30x1_0_perstn_m1 */
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- <4 RK_PA5 4 &pcfg_pull_none>,
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+ <4 RK_PA5 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m1_0_waken: pcie30x1m1-0-waken {
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+ rockchip,pins =
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/* pcie30x1_0_waken_m1 */
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- <4 RK_PA4 4 &pcfg_pull_none>,
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+ <4 RK_PA4 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn {
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+ rockchip,pins =
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/* pcie30x1_1_clkreqn_m1 */
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- <4 RK_PA0 4 &pcfg_pull_none>,
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+ <4 RK_PA0 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m1_1_perstn: pcie30x1m1-1-perstn {
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+ rockchip,pins =
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/* pcie30x1_1_perstn_m1 */
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- <4 RK_PA2 4 &pcfg_pull_none>,
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+ <4 RK_PA2 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m1_1_waken: pcie30x1m1-1-waken {
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+ rockchip,pins =
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/* pcie30x1_1_waken_m1 */
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<4 RK_PA1 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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- pcie30x1m2_pins: pcie30x1m2-pins {
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+ pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn {
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rockchip,pins =
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/* pcie30x1_0_clkreqn_m2 */
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- <1 RK_PB5 4 &pcfg_pull_none>,
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+ <1 RK_PB5 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m2_0_perstn: pcie30x1m2-0-perstn {
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+ rockchip,pins =
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/* pcie30x1_0_perstn_m2 */
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- <1 RK_PB4 4 &pcfg_pull_none>,
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+ <1 RK_PB4 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m2_0_waken: pcie30x1m2-0-waken {
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+ rockchip,pins =
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/* pcie30x1_0_waken_m2 */
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- <1 RK_PB3 4 &pcfg_pull_none>,
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+ <1 RK_PB3 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn {
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+ rockchip,pins =
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/* pcie30x1_1_clkreqn_m2 */
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- <1 RK_PA0 4 &pcfg_pull_none>,
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+ <1 RK_PA0 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m2_1_perstn: pcie30x1m2-1-perstn {
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+ rockchip,pins =
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/* pcie30x1_1_perstn_m2 */
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- <1 RK_PA7 4 &pcfg_pull_none>,
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+ <1 RK_PA7 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x1m2_1_waken: pcie30x1m2-1-waken {
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+ rockchip,pins =
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/* pcie30x1_1_waken_m2 */
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<1 RK_PA1 4 &pcfg_pull_none>;
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};
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@@ -1721,45 +1816,85 @@
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pcie30x2 {
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/omit-if-no-ref/
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- pcie30x2m0_pins: pcie30x2m0-pins {
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+ pcie30x2m0_clkreqn: pcie30x2m0-clkreqn {
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rockchip,pins =
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/* pcie30x2_clkreqn_m0 */
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- <0 RK_PD1 12 &pcfg_pull_none>,
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+ <0 RK_PD1 12 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x2m0_perstn: pcie30x2m0-perstn {
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+ rockchip,pins =
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/* pcie30x2_perstn_m0 */
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- <0 RK_PD4 12 &pcfg_pull_none>,
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+ <0 RK_PD4 12 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x2m0_waken: pcie30x2m0-waken {
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+ rockchip,pins =
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/* pcie30x2_waken_m0 */
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<0 RK_PD2 12 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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- pcie30x2m1_pins: pcie30x2m1-pins {
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+ pcie30x2m1_clkreqn: pcie30x2m1-clkreqn {
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rockchip,pins =
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/* pcie30x2_clkreqn_m1 */
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- <4 RK_PA6 4 &pcfg_pull_none>,
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+ <4 RK_PA6 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x2m1_perstn: pcie30x2m1-perstn {
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+ rockchip,pins =
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/* pcie30x2_perstn_m1 */
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- <4 RK_PB0 4 &pcfg_pull_none>,
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+ <4 RK_PB0 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x2m1_waken: pcie30x2m1-waken {
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+ rockchip,pins =
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/* pcie30x2_waken_m1 */
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<4 RK_PA7 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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- pcie30x2m2_pins: pcie30x2m2-pins {
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+ pcie30x2m2_clkreqn: pcie30x2m2-clkreqn {
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rockchip,pins =
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/* pcie30x2_clkreqn_m2 */
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- <3 RK_PD2 4 &pcfg_pull_none>,
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+ <3 RK_PD2 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x2m2_perstn: pcie30x2m2-perstn {
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+ rockchip,pins =
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/* pcie30x2_perstn_m2 */
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- <3 RK_PD4 4 &pcfg_pull_none>,
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+ <3 RK_PD4 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x2m2_waken: pcie30x2m2-waken {
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+ rockchip,pins =
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/* pcie30x2_waken_m2 */
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<3 RK_PD3 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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- pcie30x2m3_pins: pcie30x2m3-pins {
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+ pcie30x2m3_clkreqn: pcie30x2m3-clkreqn {
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rockchip,pins =
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/* pcie30x2_clkreqn_m3 */
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- <1 RK_PD7 4 &pcfg_pull_none>,
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+ <1 RK_PD7 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x2m3_perstn: pcie30x2m3-perstn {
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+ rockchip,pins =
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/* pcie30x2_perstn_m3 */
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- <1 RK_PB7 4 &pcfg_pull_none>,
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+ <1 RK_PB7 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x2m3_waken: pcie30x2m3-waken {
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+ rockchip,pins =
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/* pcie30x2_waken_m3 */
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<1 RK_PB6 4 &pcfg_pull_none>;
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};
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@@ -1774,45 +1909,85 @@
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pcie30x4 {
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/omit-if-no-ref/
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- pcie30x4m0_pins: pcie30x4m0-pins {
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+ pcie30x4m0_clkreqn: pcie30x4m0-clkreqn {
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rockchip,pins =
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/* pcie30x4_clkreqn_m0 */
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- <0 RK_PC6 12 &pcfg_pull_none>,
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+ <0 RK_PC6 12 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x4m0_perstn: pcie30x4m0-perstn {
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+ rockchip,pins =
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/* pcie30x4_perstn_m0 */
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- <0 RK_PD0 12 &pcfg_pull_none>,
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+ <0 RK_PD0 12 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x4m0_waken: pcie30x4m0-waken {
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+ rockchip,pins =
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/* pcie30x4_waken_m0 */
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<0 RK_PC7 12 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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- pcie30x4m1_pins: pcie30x4m1-pins {
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+ pcie30x4m1_clkreqn: pcie30x4m1-clkreqn {
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rockchip,pins =
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/* pcie30x4_clkreqn_m1 */
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- <4 RK_PB4 4 &pcfg_pull_none>,
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+ <4 RK_PB4 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x4m1_perstn: pcie30x4m1-perstn {
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+ rockchip,pins =
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/* pcie30x4_perstn_m1 */
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- <4 RK_PB6 4 &pcfg_pull_none>,
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+ <4 RK_PB6 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x4m1_waken: pcie30x4m1-waken {
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+ rockchip,pins =
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/* pcie30x4_waken_m1 */
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<4 RK_PB5 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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- pcie30x4m2_pins: pcie30x4m2-pins {
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+ pcie30x4m2_clkreqn: pcie30x4m2-clkreqn {
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rockchip,pins =
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/* pcie30x4_clkreqn_m2 */
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- <3 RK_PC4 4 &pcfg_pull_none>,
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+ <3 RK_PC4 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x4m2_perstn: pcie30x4m2-perstn {
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+ rockchip,pins =
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/* pcie30x4_perstn_m2 */
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- <3 RK_PC6 4 &pcfg_pull_none>,
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+ <3 RK_PC6 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x4m2_waken: pcie30x4m2-waken {
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+ rockchip,pins =
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/* pcie30x4_waken_m2 */
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<3 RK_PC5 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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- pcie30x4m3_pins: pcie30x4m3-pins {
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+ pcie30x4m3_clkreqn: pcie30x4m3-clkreqn {
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rockchip,pins =
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/* pcie30x4_clkreqn_m3 */
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- <1 RK_PB0 4 &pcfg_pull_none>,
|
|
+ <1 RK_PB0 4 &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ pcie30x4m3_perstn: pcie30x4m3-perstn {
|
|
+ rockchip,pins =
|
|
/* pcie30x4_perstn_m3 */
|
|
- <1 RK_PB2 4 &pcfg_pull_none>,
|
|
+ <1 RK_PB2 4 &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ pcie30x4m3_waken: pcie30x4m3-waken {
|
|
+ rockchip,pins =
|
|
/* pcie30x4_waken_m3 */
|
|
<1 RK_PB1 4 &pcfg_pull_none>;
|
|
};
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
|
@@ -311,7 +311,7 @@
|
|
};
|
|
|
|
&pcie2x1l2 {
|
|
- pinctrl-0 = <&pcie20x1m0_pins>;
|
|
+ pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>;
|
|
pinctrl-names = "default";
|
|
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
|
|
vpcie3v3-supply = <&vcc3v3_wf>;
|
|
@@ -329,6 +329,10 @@
|
|
pow_en: pow-en {
|
|
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
+
|
|
+ pcie2_reset: pcie2-reset {
|
|
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
};
|
|
|
|
power {
|