86e3c31bcc
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/23139 Signed-off-by: Nick Hainke <vincent@systemli.org>
62 lines
1.9 KiB
Diff
62 lines
1.9 KiB
Diff
From d7bb71e69f58c1b3665a9f926bf8d3855111bf8e Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Sat, 19 Oct 2024 13:12:10 +0300
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Subject: arm64: dts: rockchip: Add HDMI0 node to rk3588
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Add support for the HDMI0 output port found on RK3588 SoC.
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-1-466cd80e8ff9@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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@@ -1369,6 +1369,47 @@
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status = "disabled";
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};
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+ hdmi0: hdmi@fde80000 {
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+ compatible = "rockchip,rk3588-dw-hdmi-qp";
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+ reg = <0x0 0xfde80000 0x0 0x20000>;
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+ clocks = <&cru PCLK_HDMITX0>,
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+ <&cru CLK_HDMITX0_EARC>,
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+ <&cru CLK_HDMITX0_REF>,
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+ <&cru MCLK_I2S5_8CH_TX>,
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+ <&cru CLK_HDMIHDP0>,
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+ <&cru HCLK_VO1>;
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+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
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+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
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+ interrupt-names = "avp", "cec", "earc", "main", "hpd";
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+ phys = <&hdptxphy_hdmi0>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
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+ &hdmim0_tx0_scl &hdmim0_tx0_sda>;
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+ power-domains = <&power RK3588_PD_VO1>;
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+ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
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+ reset-names = "ref", "hdp";
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+ rockchip,grf = <&sys_grf>;
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+ rockchip,vo-grf = <&vo1_grf>;
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ hdmi0_in: port@0 {
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+ reg = <0>;
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+ };
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+
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+ hdmi0_out: port@1 {
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+ reg = <1>;
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+ };
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+ };
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+ };
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+
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qos_gpu_m0: qos@fdf35000 {
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compatible = "rockchip,rk3588-qos", "syscon";
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reg = <0x0 0xfdf35000 0x0 0x20>;
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