86e3c31bcc
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/23139 Signed-off-by: Nick Hainke <vincent@systemli.org>
39 lines
1.3 KiB
Diff
39 lines
1.3 KiB
Diff
From eb4262203d7d85eb7b6f2696816db272e41f5464 Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Tue, 4 Feb 2025 14:40:08 +0200
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Subject: arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on
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RK3588
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VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
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more accurate pixel clock source to improve handling of display modes up
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to 4K@60Hz on video ports 0, 1 and 2.
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For now only HDMI0 output is supported, hence add the related PLL clock.
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Tested-by: FUKAUMI Naoki <naoki@radxa.com>
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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@@ -1261,14 +1261,16 @@
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<&cru DCLK_VOP1>,
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<&cru DCLK_VOP2>,
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<&cru DCLK_VOP3>,
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- <&cru PCLK_VOP_ROOT>;
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+ <&cru PCLK_VOP_ROOT>,
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+ <&hdptxphy_hdmi0>;
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clock-names = "aclk",
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"hclk",
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"dclk_vp0",
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"dclk_vp1",
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"dclk_vp2",
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"dclk_vp3",
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- "pclk_vop";
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+ "pclk_vop",
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+ "pll_hdmiphy0";
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iommus = <&vop_mmu>;
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power-domains = <&power RK3588_PD_VOP>;
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rockchip,grf = <&sys_grf>;
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