86e3c31bcc
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/23139 Signed-off-by: Nick Hainke <vincent@systemli.org>
49 lines
1.5 KiB
Diff
49 lines
1.5 KiB
Diff
From b2e668a60ed866ba960acb5310d1fb6bf81d154f Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Sun, 23 Feb 2025 11:31:40 +0200
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Subject: arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on
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RK3588
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VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
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more accurate pixel clock source to improve handling of display modes up
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to 4K@60Hz on video ports 0, 1 and 2.
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The HDMI1 PHY PLL clock source cannot be added directly to vop node in
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rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an
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optional feature and its PHY node belongs to a separate (extra) DT file.
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Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its
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clocks & clock-names properties in the extra DT file.
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-4-f4cec5e06fbe@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
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@@ -509,3 +509,24 @@
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status = "disabled";
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};
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};
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+
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+&vop {
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+ clocks = <&cru ACLK_VOP>,
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+ <&cru HCLK_VOP>,
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+ <&cru DCLK_VOP0>,
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+ <&cru DCLK_VOP1>,
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+ <&cru DCLK_VOP2>,
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+ <&cru DCLK_VOP3>,
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+ <&cru PCLK_VOP_ROOT>,
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+ <&hdptxphy0>,
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+ <&hdptxphy1>;
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+ clock-names = "aclk",
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+ "hclk",
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+ "dclk_vp0",
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+ "dclk_vp1",
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+ "dclk_vp2",
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+ "dclk_vp3",
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+ "pclk_vop",
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+ "pll_hdmiphy0",
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+ "pll_hdmiphy1";
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+};
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