86e3c31bcc
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/23139 Signed-off-by: Nick Hainke <vincent@systemli.org>
89 lines
2.9 KiB
Diff
89 lines
2.9 KiB
Diff
From 0327238991ba2d1de25e1116b1c064f433e45b8d Mon Sep 17 00:00:00 2001
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From: Shreeya Patel <shreeya.patel@collabora.com>
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Date: Fri, 7 Mar 2025 12:18:56 +0300
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Subject: arm64: dts: rockchip: Add device tree support for HDMI RX Controller
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Add device tree support for Synopsys DesignWare HDMI RX
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Controller.
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Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
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Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
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Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
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Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
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Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
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Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
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Link: https://lore.kernel.org/r/20250307091857.646581-2-dmitry.osipenko@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
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@@ -23,6 +23,30 @@
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};
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};
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+ reserved-memory {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ /*
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+ * The 4k HDMI capture controller works only with 32bit
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+ * phys addresses and doesn't support IOMMU. HDMI RX CMA
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+ * must be reserved below 4GB.
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+ * The size of 160MB was determined as follows:
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+ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB
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+ * To ensure sufficient support for practical use-cases,
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+ * we doubled the 66MB value.
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+ */
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+ hdmi_receiver_cma: hdmi-receiver-cma {
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+ compatible = "shared-dma-pool";
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+ alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
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+ size = <0x0 (160 * 0x100000)>; /* 160MiB */
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+ alignment = <0x0 0x40000>; /* 64K */
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+ no-map;
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+ status = "disabled";
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+ };
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+ };
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+
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usb_host1_xhci: usb@fc400000 {
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compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
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reg = <0x0 0xfc400000 0x0 0x400000>;
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@@ -198,6 +222,37 @@
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};
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};
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+ hdmi_receiver: hdmi_receiver@fdee0000 {
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+ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
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+ reg = <0x0 0xfdee0000 0x0 0x6000>;
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+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
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+ interrupt-names = "cec", "hdmi", "dma";
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+ clocks = <&cru ACLK_HDMIRX>,
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+ <&cru CLK_HDMIRX_AUD>,
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+ <&cru CLK_CR_PARA>,
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+ <&cru PCLK_HDMIRX>,
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+ <&cru CLK_HDMIRX_REF>,
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+ <&cru PCLK_S_HDMIRX>,
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+ <&cru HCLK_VO1>;
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+ clock-names = "aclk",
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+ "audio",
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+ "cr_para",
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+ "pclk",
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+ "ref",
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+ "hclk_s_hdmirx",
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+ "hclk_vo1";
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+ memory-region = <&hdmi_receiver_cma>;
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+ power-domains = <&power RK3588_PD_VO1>;
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+ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
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+ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
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+ reset-names = "axi", "apb", "ref", "biu";
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+ rockchip,grf = <&sys_grf>;
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+ rockchip,vo1-grf = <&vo1_grf>;
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+ status = "disabled";
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+ };
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+
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pcie3x4: pcie@fe150000 {
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compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
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#address-cells = <3>;
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