86e3c31bcc
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/23139 Signed-off-by: Nick Hainke <vincent@systemli.org>
95 lines
3.1 KiB
Diff
95 lines
3.1 KiB
Diff
From e684f02492f99d6f6f037a35a613607339cf8e8f Mon Sep 17 00:00:00 2001
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From: Heiko Stuebner <heiko@sntech.de>
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Date: Fri, 6 Sep 2024 10:25:11 +0200
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Subject: arm64: dts: rockchip: fix the pcie refclock oscillator on Rock 5 ITX
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The Rock 5 ITX uses two PCIe controllers to drive both a M.2 slot and its
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SATA controller with 2 lanes each. The supply for the refclk oscillator is
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the same that supplies the M.2 slot, but the SATA controller port is
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supplied by a different rail.
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This leads to the effect that if the PCIe30x4 controller for the M.2
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probes first, everything works normally. But if the PCIe30x2 controller
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that is connected to the SATA controller probes first, it will hang on
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the first DBI read as nothing will have enabled the refclock before.
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Fix this by describing the clock generator with its supplies so that
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both controllers can reference it as needed.
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://lore.kernel.org/r/20240906082511.2963890-6-heiko@sntech.de
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--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
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@@ -72,6 +72,15 @@
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};
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};
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+ /* Unnamed gated oscillator: 100MHz,3.3V,3225 */
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+ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
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+ compatible = "gated-fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <100000000>;
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+ clock-output-names = "pcie30_refclk";
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+ vdd-supply = <&vcc3v3_pi6c_05>;
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+ };
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+
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fan0: pwm-fan {
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compatible = "pwm-fan";
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#cooling-cells = <2>;
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@@ -146,13 +155,14 @@
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vin-supply = <&vcc_3v3_s3>;
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};
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- vcc3v3_mkey: regulator-vcc3v3-mkey {
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+ /* The PCIE30x4_PWREN_H controls two regulators */
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+ vcc3v3_mkey: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
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compatible = "regulator-fixed";
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enable-active-high;
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gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie30x4_pwren_h>;
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- regulator-name = "vcc3v3_mkey";
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+ regulator-name = "vcc3v3_pi6c_05";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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startup-delay-us = <5000>;
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@@ -513,6 +523,18 @@
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/* ASMedia ASM1164 Sata controller */
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&pcie3x2 {
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+ /*
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+ * The board has a "pcie_refclk" oscillator that needs enabling,
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+ * so add it to the list of clocks.
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+ */
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+ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
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+ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
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+ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>,
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+ <&pcie30_port1_refclk>;
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+ clock-names = "aclk_mst", "aclk_slv",
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+ "aclk_dbi", "pclk",
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+ "aux", "pipe",
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+ "ref";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie30x2_perstn_m1_l>;
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reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
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@@ -522,6 +544,18 @@
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/* M.2 M.key */
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&pcie3x4 {
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+ /*
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+ * The board has a "pcie_refclk" oscillator that needs enabling,
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+ * so add it to the list of clocks.
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+ */
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+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
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+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
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+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
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+ <&pcie30_port0_refclk>;
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+ clock-names = "aclk_mst", "aclk_slv",
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+ "aclk_dbi", "pclk",
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+ "aux", "pipe",
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+ "ref";
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num-lanes = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie30x4_perstn_m1_l>;
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