86e3c31bcc
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/23139 Signed-off-by: Nick Hainke <vincent@systemli.org>
55 lines
1.9 KiB
Diff
55 lines
1.9 KiB
Diff
From 651aabc9fb0f354ad2ba5fd06a6011e652447489 Mon Sep 17 00:00:00 2001
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From: Yao Zi <ziyao@disroot.org>
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Date: Mon, 17 Feb 2025 06:11:43 +0000
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Subject: [PATCH] clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE
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RK3528 comes with a new PLL variant: its "PPLL", which mainly generates
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clocks for the PCIe controller, operates in normal mode only. Let's
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describe it with flag ROCKCHIP_PLL_FIXED_MODE and handle it in code.
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Signed-off-by: Yao Zi <ziyao@disroot.org>
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Link: https://lore.kernel.org/r/20250217061142.38480-7-ziyao@disroot.org
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-pll.c | 10 ++++++----
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drivers/clk/rockchip/clk.h | 2 ++
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2 files changed, 8 insertions(+), 4 deletions(-)
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--- a/drivers/clk/rockchip/clk-pll.c
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+++ b/drivers/clk/rockchip/clk-pll.c
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@@ -204,10 +204,12 @@ static int rockchip_rk3036_pll_set_param
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rockchip_rk3036_pll_get_params(pll, &cur);
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cur.rate = 0;
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- cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
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- if (cur_parent == PLL_MODE_NORM) {
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- pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
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- rate_change_remuxed = 1;
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+ if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {
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+ cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
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+ if (cur_parent == PLL_MODE_NORM) {
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+ pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
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+ rate_change_remuxed = 1;
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+ }
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}
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/* update pll values */
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--- a/drivers/clk/rockchip/clk.h
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+++ b/drivers/clk/rockchip/clk.h
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@@ -469,6 +469,7 @@ struct rockchip_pll_rate_table {
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* Flags:
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* ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
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* rate_table parameters and ajust them if necessary.
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+ * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only
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*/
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struct rockchip_pll_clock {
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unsigned int id;
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@@ -486,6 +487,7 @@ struct rockchip_pll_clock {
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};
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#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
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+#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
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#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
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_lshift, _pflags, _rtable) \
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